AMDGPUTargetMachine.cpp revision 25f259cde28860ea76c2f5628010968945a28edb 
1//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief The AMDGPU target machine contains all of the hardware specific
12/// information  needed to emit code for R600 and SI GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#include "AMDGPUTargetMachine.h"
17#include "AMDGPU.h"
18#include "R600ISelLowering.h"
19#include "R600InstrInfo.h"
20#include "R600MachineScheduler.h"
21#include "SIISelLowering.h"
22#include "SIInstrInfo.h"
23#include "llvm/Analysis/Passes.h"
24#include "llvm/Analysis/Verifier.h"
25#include "llvm/CodeGen/MachineFunctionAnalysis.h"
26#include "llvm/CodeGen/MachineModuleInfo.h"
27#include "llvm/CodeGen/Passes.h"
28#include "llvm/MC/MCAsmInfo.h"
29#include "llvm/PassManager.h"
30#include "llvm/Support/TargetRegistry.h"
31#include "llvm/Support/raw_os_ostream.h"
32#include "llvm/Transforms/IPO.h"
33#include "llvm/Transforms/Scalar.h"
34#include <llvm/CodeGen/Passes.h>
35
36using namespace llvm;
37
38extern "C" void LLVMInitializeR600Target() {
39  // Register the target
40  RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
41}
42
43static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
44  return new ScheduleDAGMI(C, new R600SchedStrategy());
45}
46
47static MachineSchedRegistry
48SchedCustomRegistry("r600", "Run R600's custom scheduler",
49                    createR600MachineScheduler);
50
51AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
52    StringRef CPU, StringRef FS,
53  TargetOptions Options,
54  Reloc::Model RM, CodeModel::Model CM,
55  CodeGenOpt::Level OptLevel
56)
57:
58  LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
59  Subtarget(TT, CPU, FS),
60  Layout(Subtarget.getDataLayout()),
61  FrameLowering(TargetFrameLowering::StackGrowsUp,
62      Subtarget.device()->getStackAlignment(), 0),
63  IntrinsicInfo(this),
64  InstrItins(&Subtarget.getInstrItineraryData()) {
65  // TLInfo uses InstrInfo so it must be initialized after.
66  if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
67    InstrInfo = new R600InstrInfo(*this);
68    TLInfo = new R600TargetLowering(*this);
69  } else {
70    InstrInfo = new SIInstrInfo(*this);
71    TLInfo = new SITargetLowering(*this);
72  }
73}
74
75AMDGPUTargetMachine::~AMDGPUTargetMachine() {
76}
77
78namespace {
79class AMDGPUPassConfig : public TargetPassConfig {
80public:
81  AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
82    : TargetPassConfig(TM, PM) {
83    const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
84    if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
85      enablePass(&MachineSchedulerID);
86      MachineSchedRegistry::setDefault(createR600MachineScheduler);
87    }
88  }
89
90  AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
91    return getTM<AMDGPUTargetMachine>();
92  }
93
94  virtual bool addPreISel();
95  virtual bool addInstSelector();
96  virtual bool addPreRegAlloc();
97  virtual bool addPostRegAlloc();
98  virtual bool addPreSched2();
99  virtual bool addPreEmitPass();
100};
101} // End of anonymous namespace
102
103TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
104  return new AMDGPUPassConfig(this, PM);
105}
106
107bool
108AMDGPUPassConfig::addPreISel() {
109  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
110  if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
111    addPass(createAMDGPUStructurizeCFGPass());
112    addPass(createSIAnnotateControlFlowPass());
113  }
114  return false;
115}
116
117bool AMDGPUPassConfig::addInstSelector() {
118  addPass(createAMDGPUPeepholeOpt(*TM));
119  addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
120
121  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
122  if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
123    // This callbacks this pass uses are not implemented yet on SI.
124    addPass(createAMDGPUIndirectAddressingPass(*TM));
125  }
126  return false;
127}
128
129bool AMDGPUPassConfig::addPreRegAlloc() {
130  addPass(createAMDGPUConvertToISAPass(*TM));
131  return false;
132}
133
134bool AMDGPUPassConfig::addPostRegAlloc() {
135  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
136
137  if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
138    addPass(createSIInsertWaits(*TM));
139  }
140  return false;
141}
142
143bool AMDGPUPassConfig::addPreSched2() {
144
145  addPass(&IfConverterID);
146  return false;
147}
148
149bool AMDGPUPassConfig::addPreEmitPass() {
150  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
151  if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
152    addPass(createAMDGPUCFGPreparationPass(*TM));
153    addPass(createAMDGPUCFGStructurizerPass(*TM));
154    addPass(createR600EmitClauseMarkers(*TM));
155    addPass(createR600ExpandSpecialInstrsPass(*TM));
156    addPass(&FinalizeMachineBundlesID);
157    addPass(createR600Packetizer(*TM));
158    addPass(createR600ControlFlowFinalizer(*TM));
159  } else {
160    addPass(createSILowerControlFlowPass(*TM));
161  }
162
163  return false;
164}
165
166