AMDGPUTargetMachine.cpp revision f2cfef8172fd2eceb036b8caff50623a189ba2ff 
1//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief The AMDGPU target machine contains all of the hardware specific
12/// information  needed to emit code for R600 and SI GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#include "AMDGPUTargetMachine.h"
17#include "AMDGPU.h"
18#include "R600ISelLowering.h"
19#include "R600InstrInfo.h"
20#include "R600MachineScheduler.h"
21#include "SIISelLowering.h"
22#include "SIInstrInfo.h"
23#include "llvm/Analysis/Passes.h"
24#include "llvm/Analysis/Verifier.h"
25#include "llvm/CodeGen/MachineFunctionAnalysis.h"
26#include "llvm/CodeGen/MachineModuleInfo.h"
27#include "llvm/CodeGen/Passes.h"
28#include "llvm/MC/MCAsmInfo.h"
29#include "llvm/PassManager.h"
30#include "llvm/Support/TargetRegistry.h"
31#include "llvm/Support/raw_os_ostream.h"
32#include "llvm/Transforms/IPO.h"
33#include "llvm/Transforms/Scalar.h"
34#include <llvm/CodeGen/Passes.h>
35
36using namespace llvm;
37
38extern "C" void LLVMInitializeR600Target() {
39  // Register the target
40  RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
41}
42
43static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
44  return new ScheduleDAGMI(C, new R600SchedStrategy());
45}
46
47static MachineSchedRegistry
48SchedCustomRegistry("r600", "Run R600's custom scheduler",
49                    createR600MachineScheduler);
50
51AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
52    StringRef CPU, StringRef FS,
53  TargetOptions Options,
54  Reloc::Model RM, CodeModel::Model CM,
55  CodeGenOpt::Level OptLevel
56)
57:
58  LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
59  Subtarget(TT, CPU, FS),
60  Layout(Subtarget.getDataLayout()),
61  FrameLowering(TargetFrameLowering::StackGrowsUp, 16 // Stack Alignment
62                                                 , 0),
63  IntrinsicInfo(this),
64  InstrItins(&Subtarget.getInstrItineraryData()) {
65  // TLInfo uses InstrInfo so it must be initialized after.
66  if (Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
67    InstrInfo.reset(new R600InstrInfo(*this));
68    TLInfo.reset(new R600TargetLowering(*this));
69  } else {
70    InstrInfo.reset(new SIInstrInfo(*this));
71    TLInfo.reset(new SITargetLowering(*this));
72  }
73  initAsmInfo();
74}
75
76AMDGPUTargetMachine::~AMDGPUTargetMachine() {
77}
78
79namespace {
80class AMDGPUPassConfig : public TargetPassConfig {
81public:
82  AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
83    : TargetPassConfig(TM, PM) {
84    const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
85    if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
86      enablePass(&MachineSchedulerID);
87      MachineSchedRegistry::setDefault(createR600MachineScheduler);
88    }
89  }
90
91  AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
92    return getTM<AMDGPUTargetMachine>();
93  }
94
95  virtual bool addPreISel();
96  virtual bool addInstSelector();
97  virtual bool addPreRegAlloc();
98  virtual bool addPostRegAlloc();
99  virtual bool addPreSched2();
100  virtual bool addPreEmitPass();
101};
102} // End of anonymous namespace
103
104TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
105  return new AMDGPUPassConfig(this, PM);
106}
107
108bool
109AMDGPUPassConfig::addPreISel() {
110  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
111  if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
112    addPass(createStructurizeCFGPass());
113    addPass(createSIAnnotateControlFlowPass());
114  } else {
115    addPass(createR600TextureIntrinsicsReplacer());
116  }
117  return false;
118}
119
120bool AMDGPUPassConfig::addInstSelector() {
121  addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
122
123  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
124  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
125    // This callbacks this pass uses are not implemented yet on SI.
126    addPass(createAMDGPUIndirectAddressingPass(*TM));
127  }
128  return false;
129}
130
131bool AMDGPUPassConfig::addPreRegAlloc() {
132  addPass(createAMDGPUConvertToISAPass(*TM));
133  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
134
135  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
136    addPass(createR600VectorRegMerger(*TM));
137  }
138  return false;
139}
140
141bool AMDGPUPassConfig::addPostRegAlloc() {
142  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
143
144  if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
145    addPass(createSIInsertWaits(*TM));
146  }
147  return false;
148}
149
150bool AMDGPUPassConfig::addPreSched2() {
151  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
152
153  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
154    addPass(createR600EmitClauseMarkers(*TM));
155  }
156  addPass(&IfConverterID);
157  return false;
158}
159
160bool AMDGPUPassConfig::addPreEmitPass() {
161  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
162  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
163    addPass(createAMDGPUCFGPreparationPass(*TM));
164    addPass(createAMDGPUCFGStructurizerPass(*TM));
165    addPass(createR600ExpandSpecialInstrsPass(*TM));
166    addPass(&FinalizeMachineBundlesID);
167    addPass(createR600Packetizer(*TM));
168    addPass(createR600ControlFlowFinalizer(*TM));
169  } else {
170    addPass(createSILowerControlFlowPass(*TM));
171  }
172
173  return false;
174}
175
176