SparcTargetMachine.cpp revision 5aefa8a6fec1cdf2e8be74195df8d3739ce73c14
168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===// 268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)// 368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)// The LLVM Compiler Infrastructure 468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)// 54e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)// This file was developed by the LLVM research group and is distributed under 64e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)// the University of Illinois Open Source License. See LICENSE.TXT for details. 768043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)// 868043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//===----------------------------------------------------------------------===// 968043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)// 1068043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)// 1168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//===----------------------------------------------------------------------===// 1268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 1368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "SparcV8TargetMachine.h" 1468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "SparcV8.h" 1568043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "llvm/Module.h" 1668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "llvm/PassManager.h" 1768043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "llvm/CodeGen/MachineFunction.h" 1868043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "llvm/CodeGen/Passes.h" 1968043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "llvm/Target/TargetOptions.h" 2068043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "llvm/Target/TargetMachineRegistry.h" 2168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "llvm/Transforms/Scalar.h" 2268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include <iostream> 2368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)using namespace llvm; 2468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 254e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)namespace { 26 // Register the target. 27 RegisterTarget<SparcV8TargetMachine> X("sparcv8"," SPARC V8 (experimental)"); 28} 29 30/// SparcV8TargetMachine ctor - Create an ILP32 architecture model 31/// 32SparcV8TargetMachine::SparcV8TargetMachine(const Module &M, 33 IntrinsicLowering *IL) 34 : TargetMachine("SparcV8", IL, false, 4, 4, 8, 4, 8, 4, 2, 1, 4), 35 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), JITInfo(*this) { 36} 37 38unsigned SparcV8TargetMachine::getJITMatchQuality() { 39 return 0; // No JIT yet. 40} 41 42unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) { 43 if (M.getEndianness() == Module::BigEndian && 44 M.getPointerSize() == Module::Pointer32) 45#ifdef __sparc__ 46 return 20; // BE/32 ==> Prefer sparcv8 on sparc 47#else 48 return 5; // BE/32 ==> Prefer ppc elsewhere 49#endif 50 else if (M.getEndianness() != Module::AnyEndianness || 51 M.getPointerSize() != Module::AnyPointerSize) 52 return 0; // Match for some other target 53 54 return getJITMatchQuality()/2; 55} 56 57/// addPassesToEmitAssembly - Add passes to the specified pass manager 58/// to implement a static compiler for this target. 59/// 60bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM, 61 std::ostream &Out) { 62 // FIXME: Implement efficient support for garbage collection intrinsics. 63 PM.add(createLowerGCPass()); 64 65 // Replace malloc and free instructions with library calls. 66 PM.add(createLowerAllocationsPass()); 67 68 // FIXME: implement the switch instruction in the instruction selector. 69 PM.add(createLowerSwitchPass()); 70 71 // FIXME: implement the invoke/unwind instructions! 72 PM.add(createLowerInvokePass()); 73 74 PM.add(createLowerConstantExpressionsPass()); 75 76 // Make sure that no unreachable blocks are instruction selected. 77 PM.add(createUnreachableBlockEliminationPass()); 78 79 // FIXME: implement the select instruction in the instruction selector. 80 PM.add(createLowerSelectPass()); 81 82 PM.add(createSparcV8SimpleInstructionSelector(*this)); 83 84 // Print machine instructions as they were initially generated. 85 if (PrintMachineCode) 86 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 87 88 PM.add(createRegisterAllocator()); 89 PM.add(createPrologEpilogCodeInserter()); 90 91 // Print machine instructions after register allocation and prolog/epilog 92 // insertion. 93 if (PrintMachineCode) 94 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 95 96 PM.add(createSparcV8FPMoverPass(*this)); 97 PM.add(createSparcV8DelaySlotFillerPass(*this)); 98 99 // Print machine instructions after filling delay slots. 100 if (PrintMachineCode) 101 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 102 103 // Output assembly language. 104 PM.add(createSparcV8CodePrinterPass(Out, *this)); 105 106 // Delete the MachineInstrs we generated, since they're no longer needed. 107 PM.add(createMachineCodeDeleter()); 108 return false; 109} 110 111/// addPassesToJITCompile - Add passes to the specified pass manager to 112/// implement a fast dynamic compiler for this target. 113/// 114void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) { 115 // FIXME: Implement efficient support for garbage collection intrinsics. 116 PM.add(createLowerGCPass()); 117 118 // Replace malloc and free instructions with library calls. 119 PM.add(createLowerAllocationsPass()); 120 121 // FIXME: implement the switch instruction in the instruction selector. 122 PM.add(createLowerSwitchPass()); 123 124 // FIXME: implement the invoke/unwind instructions! 125 PM.add(createLowerInvokePass()); 126 127 PM.add(createLowerConstantExpressionsPass()); 128 129 // Make sure that no unreachable blocks are instruction selected. 130 PM.add(createUnreachableBlockEliminationPass()); 131 132 // FIXME: implement the select instruction in the instruction selector. 133 PM.add(createLowerSelectPass()); 134 135 PM.add(createSparcV8SimpleInstructionSelector(TM)); 136 137 // Print machine instructions as they were initially generated. 138 if (PrintMachineCode) 139 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 140 141 PM.add(createRegisterAllocator()); 142 PM.add(createPrologEpilogCodeInserter()); 143 144 // Print machine instructions after register allocation and prolog/epilog 145 // insertion. 146 if (PrintMachineCode) 147 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 148 149 PM.add(createSparcV8FPMoverPass(TM)); 150 PM.add(createSparcV8DelaySlotFillerPass(TM)); 151 152 // Print machine instructions after filling delay slots. 153 if (PrintMachineCode) 154 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 155} 156