SparcTargetMachine.cpp revision 79aa3417eb6f58d668aadfedf075240a41d35a26
19e49fb63d355446b91d20ff78ad78b297e89a50dcaryclark@google.com//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 29e49fb63d355446b91d20ff78ad78b297e89a50dcaryclark@google.com// 39e49fb63d355446b91d20ff78ad78b297e89a50dcaryclark@google.com// The LLVM Compiler Infrastructure 49e49fb63d355446b91d20ff78ad78b297e89a50dcaryclark@google.com// 59e49fb63d355446b91d20ff78ad78b297e89a50dcaryclark@google.com// This file is distributed under the University of Illinois Open Source 69e49fb63d355446b91d20ff78ad78b297e89a50dcaryclark@google.com// License. See LICENSE.TXT for details. 7d88e0894d0156f4d427b812fec69bfba3eec7a8dcaryclark@google.com// 878e17130f396d8b2157116c2504e357192f87ed1caryclark@google.com//===----------------------------------------------------------------------===// 903f970652e07c6832cae41fa374cb68ca80d472ccaryclark@google.com// 1078e17130f396d8b2157116c2504e357192f87ed1caryclark@google.com// 11cd4421df5012b75c792c6c8bf2c5ee0410921c15caryclark@google.com//===----------------------------------------------------------------------===// 1259823f7f3ba43c7c6bc1fa8c600b093ecb4236aacaryclark@google.com 13198e054b33051a6cd5f606ccbc8d539cefc5631fcaryclark@google.com#include "SparcTargetMachine.h" 14198e054b33051a6cd5f606ccbc8d539cefc5631fcaryclark@google.com#include "Sparc.h" 15be584d782020fe0d413a9ab4e9a57a13b1ac1032reed@google.com#include "llvm/PassManager.h" 16cd4421df5012b75c792c6c8bf2c5ee0410921c15caryclark@google.com#include "llvm/CodeGen/Passes.h" 17752b60e633a349c5b9f7bcc6a28b8064fc77bb41caryclark@google.com#include "llvm/Support/TargetRegistry.h" 182e7f4c810dc717383df42d27bdba862514ab6d51caryclark@google.comusing namespace llvm; 192e7f4c810dc717383df42d27bdba862514ab6d51caryclark@google.com 20198e054b33051a6cd5f606ccbc8d539cefc5631fcaryclark@google.comextern "C" void LLVMInitializeSparcTarget() { 21be584d782020fe0d413a9ab4e9a57a13b1ac1032reed@google.com // Register the target. 2224bec79d6f3d71ff97b50db72461a3892bd4f6b5caryclark@google.com RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); 2359823f7f3ba43c7c6bc1fa8c600b093ecb4236aacaryclark@google.com RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); 248dcf114db9762c02d217beba6e29dffa4e92d298caryclark@google.com} 2578e17130f396d8b2157116c2504e357192f87ed1caryclark@google.com 2678e17130f396d8b2157116c2504e357192f87ed1caryclark@google.com/// SparcTargetMachine ctor - Create an ILP32 architecture model 2778e17130f396d8b2157116c2504e357192f87ed1caryclark@google.com/// 282ddff9388694263c7be9347de7eb768cd0847997caryclark@google.comSparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, 292ddff9388694263c7be9347de7eb768cd0847997caryclark@google.com StringRef CPU, StringRef FS, 302ddff9388694263c7be9347de7eb768cd0847997caryclark@google.com const TargetOptions &Options, 312ddff9388694263c7be9347de7eb768cd0847997caryclark@google.com Reloc::Model RM, CodeModel::Model CM, 322ddff9388694263c7be9347de7eb768cd0847997caryclark@google.com CodeGenOpt::Level OL, 332ddff9388694263c7be9347de7eb768cd0847997caryclark@google.com bool is64bit) 342ddff9388694263c7be9347de7eb768cd0847997caryclark@google.com : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 352ddff9388694263c7be9347de7eb768cd0847997caryclark@google.com Subtarget(TT, CPU, FS, is64bit), 3678e17130f396d8b2157116c2504e357192f87ed1caryclark@google.com DataLayout(Subtarget.getDataLayout()), 3778e17130f396d8b2157116c2504e357192f87ed1caryclark@google.com TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), 3878e17130f396d8b2157116c2504e357192f87ed1caryclark@google.com FrameLowering(Subtarget) { 3959823f7f3ba43c7c6bc1fa8c600b093ecb4236aacaryclark@google.com} 4027c449af06cd1d05db441593d08b84f3530fba52caryclark@google.com 4147580694fbe974a065caf7c39c3d2075708c2018caryclark@google.comnamespace { 42d6176b0dcacb124539e0cfd051e6d93a9782f020rmistry@google.com/// Sparc Code Generator Pass Configuration Options. 4378e17130f396d8b2157116c2504e357192f87ed1caryclark@google.comclass SparcPassConfig : public TargetPassConfig { 4478e17130f396d8b2157116c2504e357192f87ed1caryclark@google.compublic: 4578e17130f396d8b2157116c2504e357192f87ed1caryclark@google.com SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM) 4678e17130f396d8b2157116c2504e357192f87ed1caryclark@google.com : TargetPassConfig(TM, PM) {} 4759823f7f3ba43c7c6bc1fa8c600b093ecb4236aacaryclark@google.com 4859823f7f3ba43c7c6bc1fa8c600b093ecb4236aacaryclark@google.com SparcTargetMachine &getSparcTargetMachine() const { 4924bec79d6f3d71ff97b50db72461a3892bd4f6b5caryclark@google.com return getTM<SparcTargetMachine>(); 5024bec79d6f3d71ff97b50db72461a3892bd4f6b5caryclark@google.com } 5159823f7f3ba43c7c6bc1fa8c600b093ecb4236aacaryclark@google.com 5259823f7f3ba43c7c6bc1fa8c600b093ecb4236aacaryclark@google.com virtual bool addInstSelector(); 53 virtual bool addPreEmitPass(); 54}; 55} // namespace 56 57TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { 58 return new SparcPassConfig(this, PM); 59} 60 61bool SparcPassConfig::addInstSelector() { 62 PM.add(createSparcISelDag(getSparcTargetMachine())); 63 return false; 64} 65 66/// addPreEmitPass - This pass may be implemented by targets that want to run 67/// passes immediately before machine code is emitted. This should return 68/// true if -print-machineinstrs should print out the code after the passes. 69bool SparcPassConfig::addPreEmitPass(){ 70 PM.add(createSparcFPMoverPass(getSparcTargetMachine())); 71 PM.add(createSparcDelaySlotFillerPass(getSparcTargetMachine())); 72 return true; 73} 74 75void SparcV8TargetMachine::anchor() { } 76 77SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, 78 StringRef TT, StringRef CPU, 79 StringRef FS, 80 const TargetOptions &Options, 81 Reloc::Model RM, 82 CodeModel::Model CM, 83 CodeGenOpt::Level OL) 84 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 85} 86 87void SparcV9TargetMachine::anchor() { } 88 89SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, 90 StringRef TT, StringRef CPU, 91 StringRef FS, 92 const TargetOptions &Options, 93 Reloc::Model RM, 94 CodeModel::Model CM, 95 CodeGenOpt::Level OL) 96 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 97} 98