SystemZISelLowering.h revision 14a926f13b768ee3771bb944bbbb29529a40dbe1
1//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that SystemZ uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H 16#define LLVM_TARGET_SystemZ_ISELLOWERING_H 17 18#include "SystemZ.h" 19#include "llvm/CodeGen/MachineBasicBlock.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/Target/TargetLowering.h" 22 23namespace llvm { 24namespace SystemZISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 // Return with a flag operand. Operand 0 is the chain operand. 29 RET_FLAG, 30 31 // Calls a function. Operand 0 is the chain operand and operand 1 32 // is the target address. The arguments start at operand 2. 33 // There is an optional glue operand at the end. 34 CALL, 35 36 // Wraps a TargetGlobalAddress that should be loaded using PC-relative 37 // accesses (LARL). Operand 0 is the address. 38 PCREL_WRAPPER, 39 40 // Signed integer and floating-point comparisons. The operands are the 41 // two values to compare. 42 CMP, 43 44 // Likewise unsigned integer comparison. 45 UCMP, 46 47 // Branches if a condition is true. Operand 0 is the chain operand; 48 // operand 1 is the 4-bit condition-code mask, with bit N in 49 // big-endian order meaning "branch if CC=N"; operand 2 is the 50 // target block and operand 3 is the flag operand. 51 BR_CCMASK, 52 53 // Selects between operand 0 and operand 1. Operand 2 is the 54 // mask of condition-code values for which operand 0 should be 55 // chosen over operand 1; it has the same form as BR_CCMASK. 56 // Operand 3 is the flag operand. 57 SELECT_CCMASK, 58 59 // Evaluates to the gap between the stack pointer and the 60 // base of the dynamically-allocatable area. 61 ADJDYNALLOC, 62 63 // Extracts the value of a 32-bit access register. Operand 0 is 64 // the number of the register. 65 EXTRACT_ACCESS, 66 67 // Wrappers around the ISD opcodes of the same name. The output and 68 // first input operands are GR128s. The trailing numbers are the 69 // widths of the second operand in bits. 70 UMUL_LOHI64, 71 SDIVREM64, 72 UDIVREM32, 73 UDIVREM64, 74 75 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 76 // ATOMIC_LOAD_<op>. 77 // 78 // Operand 0: the address of the containing 32-bit-aligned field 79 // Operand 1: the second operand of <op>, in the high bits of an i32 80 // for everything except ATOMIC_SWAPW 81 // Operand 2: how many bits to rotate the i32 left to bring the first 82 // operand into the high bits 83 // Operand 3: the negative of operand 2, for rotating the other way 84 // Operand 4: the width of the field in bits (8 or 16) 85 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 86 ATOMIC_LOADW_ADD, 87 ATOMIC_LOADW_SUB, 88 ATOMIC_LOADW_AND, 89 ATOMIC_LOADW_OR, 90 ATOMIC_LOADW_XOR, 91 ATOMIC_LOADW_NAND, 92 ATOMIC_LOADW_MIN, 93 ATOMIC_LOADW_MAX, 94 ATOMIC_LOADW_UMIN, 95 ATOMIC_LOADW_UMAX, 96 97 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 98 // 99 // Operand 0: the address of the containing 32-bit-aligned field 100 // Operand 1: the compare value, in the low bits of an i32 101 // Operand 2: the swap value, in the low bits of an i32 102 // Operand 3: how many bits to rotate the i32 left to bring the first 103 // operand into the high bits 104 // Operand 4: the negative of operand 2, for rotating the other way 105 // Operand 5: the width of the field in bits (8 or 16) 106 ATOMIC_CMP_SWAPW 107 }; 108} 109 110class SystemZSubtarget; 111class SystemZTargetMachine; 112 113class SystemZTargetLowering : public TargetLowering { 114public: 115 explicit SystemZTargetLowering(SystemZTargetMachine &TM); 116 117 // Override TargetLowering. 118 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE { 119 return MVT::i32; 120 } 121 virtual EVT getSetCCResultType(LLVMContext &, EVT) const { 122 return MVT::i32; 123 } 124 virtual bool isFMAFasterThanMulAndAdd(EVT) const LLVM_OVERRIDE { 125 return true; 126 } 127 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 128 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const; 129 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE; 130 virtual std::pair<unsigned, const TargetRegisterClass *> 131 getRegForInlineAsmConstraint(const std::string &Constraint, 132 EVT VT) const LLVM_OVERRIDE; 133 virtual TargetLowering::ConstraintType 134 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE; 135 virtual TargetLowering::ConstraintWeight 136 getSingleConstraintMatchWeight(AsmOperandInfo &info, 137 const char *constraint) const LLVM_OVERRIDE; 138 virtual void 139 LowerAsmOperandForConstraint(SDValue Op, 140 std::string &Constraint, 141 std::vector<SDValue> &Ops, 142 SelectionDAG &DAG) const LLVM_OVERRIDE; 143 virtual MachineBasicBlock * 144 EmitInstrWithCustomInserter(MachineInstr *MI, 145 MachineBasicBlock *BB) const LLVM_OVERRIDE; 146 virtual SDValue LowerOperation(SDValue Op, 147 SelectionDAG &DAG) const LLVM_OVERRIDE; 148 virtual SDValue 149 LowerFormalArguments(SDValue Chain, 150 CallingConv::ID CallConv, bool isVarArg, 151 const SmallVectorImpl<ISD::InputArg> &Ins, 152 SDLoc DL, SelectionDAG &DAG, 153 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE; 154 virtual SDValue 155 LowerCall(CallLoweringInfo &CLI, 156 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE; 157 158 virtual SDValue 159 LowerReturn(SDValue Chain, 160 CallingConv::ID CallConv, bool IsVarArg, 161 const SmallVectorImpl<ISD::OutputArg> &Outs, 162 const SmallVectorImpl<SDValue> &OutVals, 163 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE; 164 165private: 166 const SystemZSubtarget &Subtarget; 167 const SystemZTargetMachine &TM; 168 169 // Implement LowerOperation for individual opcodes. 170 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 171 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 172 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 173 SelectionDAG &DAG) const; 174 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 175 SelectionDAG &DAG) const; 176 SDValue lowerBlockAddress(BlockAddressSDNode *Node, 177 SelectionDAG &DAG) const; 178 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 179 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 180 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 181 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 182 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 183 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 184 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 185 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 186 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 187 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 188 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG, 189 unsigned Opcode) const; 190 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 191 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 192 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 193 194 // If the last instruction before MBBI in MBB was some form of COMPARE, 195 // try to replace it with a COMPARE AND BRANCH just before MBBI. 196 // CCMask and Target are the BRC-like operands for the branch. 197 // Return true if the change was made. 198 bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 199 MachineBasicBlock::iterator MBBI, 200 unsigned CCMask, 201 MachineBasicBlock *Target) const; 202 203 // Implement EmitInstrWithCustomInserter for individual operation types. 204 MachineBasicBlock *emitSelect(MachineInstr *MI, 205 MachineBasicBlock *BB) const; 206 MachineBasicBlock *emitExt128(MachineInstr *MI, 207 MachineBasicBlock *MBB, 208 bool ClearEven, unsigned SubReg) const; 209 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI, 210 MachineBasicBlock *BB, 211 unsigned BinOpcode, unsigned BitSize, 212 bool Invert = false) const; 213 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI, 214 MachineBasicBlock *MBB, 215 unsigned CompareOpcode, 216 unsigned KeepOldMask, 217 unsigned BitSize) const; 218 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI, 219 MachineBasicBlock *BB) const; 220}; 221} // end namespace llvm 222 223#endif // LLVM_TARGET_SystemZ_ISELLOWERING_H 224