SystemZISelLowering.h revision 225ed7069caae9ece32d8bd3d15c6e41e21cc04b 
1//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that SystemZ uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16#define LLVM_TARGET_SystemZ_ISELLOWERING_H
17
18#include "SystemZ.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/Target/TargetLowering.h"
21
22namespace llvm {
23namespace SystemZISD {
24  enum {
25    FIRST_NUMBER = ISD::BUILTIN_OP_END,
26
27    // Return with a flag operand.  Operand 0 is the chain operand.
28    RET_FLAG,
29
30    // Calls a function.  Operand 0 is the chain operand and operand 1
31    // is the target address.  The arguments start at operand 2.
32    // There is an optional glue operand at the end.
33    CALL,
34
35    // Wraps a TargetGlobalAddress that should be loaded using PC-relative
36    // accesses (LARL).  Operand 0 is the address.
37    PCREL_WRAPPER,
38
39    // Signed integer and floating-point comparisons.  The operands are the
40    // two values to compare.
41    CMP,
42
43    // Likewise unsigned integer comparison.
44    UCMP,
45
46    // Branches if a condition is true.  Operand 0 is the chain operand;
47    // operand 1 is the 4-bit condition-code mask, with bit N in
48    // big-endian order meaning "branch if CC=N"; operand 2 is the
49    // target block and operand 3 is the flag operand.
50    BR_CCMASK,
51
52    // Selects between operand 0 and operand 1.  Operand 2 is the
53    // mask of condition-code values for which operand 0 should be
54    // chosen over operand 1; it has the same form as BR_CCMASK.
55    // Operand 3 is the flag operand.
56    SELECT_CCMASK,
57
58    // Evaluates to the gap between the stack pointer and the
59    // base of the dynamically-allocatable area.
60    ADJDYNALLOC,
61
62    // Extracts the value of a 32-bit access register.  Operand 0 is
63    // the number of the register.
64    EXTRACT_ACCESS,
65
66    // Wrappers around the ISD opcodes of the same name.  The output and
67    // first input operands are GR128s.  The trailing numbers are the
68    // widths of the second operand in bits.
69    UMUL_LOHI64,
70    SDIVREM64,
71    UDIVREM32,
72    UDIVREM64,
73
74    // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
75    // ATOMIC_LOAD_<op>.
76    //
77    // Operand 0: the address of the containing 32-bit-aligned field
78    // Operand 1: the second operand of <op>, in the high bits of an i32
79    //            for everything except ATOMIC_SWAPW
80    // Operand 2: how many bits to rotate the i32 left to bring the first
81    //            operand into the high bits
82    // Operand 3: the negative of operand 2, for rotating the other way
83    // Operand 4: the width of the field in bits (8 or 16)
84    ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
85    ATOMIC_LOADW_ADD,
86    ATOMIC_LOADW_SUB,
87    ATOMIC_LOADW_AND,
88    ATOMIC_LOADW_OR,
89    ATOMIC_LOADW_XOR,
90    ATOMIC_LOADW_NAND,
91    ATOMIC_LOADW_MIN,
92    ATOMIC_LOADW_MAX,
93    ATOMIC_LOADW_UMIN,
94    ATOMIC_LOADW_UMAX,
95
96    // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
97    //
98    // Operand 0: the address of the containing 32-bit-aligned field
99    // Operand 1: the compare value, in the low bits of an i32
100    // Operand 2: the swap value, in the low bits of an i32
101    // Operand 3: how many bits to rotate the i32 left to bring the first
102    //            operand into the high bits
103    // Operand 4: the negative of operand 2, for rotating the other way
104    // Operand 5: the width of the field in bits (8 or 16)
105    ATOMIC_CMP_SWAPW
106  };
107}
108
109class SystemZSubtarget;
110class SystemZTargetMachine;
111
112class SystemZTargetLowering : public TargetLowering {
113public:
114  explicit SystemZTargetLowering(SystemZTargetMachine &TM);
115
116  // Override TargetLowering.
117  virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
118    return MVT::i32;
119  }
120  virtual EVT getSetCCResultType(LLVMContext &, EVT) const {
121    return MVT::i32;
122  }
123  virtual bool isFMAFasterThanMulAndAdd(EVT) const LLVM_OVERRIDE {
124    return true;
125  }
126  virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
127  virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
128  virtual std::pair<unsigned, const TargetRegisterClass *>
129    getRegForInlineAsmConstraint(const std::string &Constraint,
130                                 EVT VT) const LLVM_OVERRIDE;
131  virtual TargetLowering::ConstraintType
132    getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
133  virtual TargetLowering::ConstraintWeight
134    getSingleConstraintMatchWeight(AsmOperandInfo &info,
135                                   const char *constraint) const LLVM_OVERRIDE;
136  virtual void
137    LowerAsmOperandForConstraint(SDValue Op,
138                                 std::string &Constraint,
139                                 std::vector<SDValue> &Ops,
140                                 SelectionDAG &DAG) const LLVM_OVERRIDE;
141  virtual MachineBasicBlock *
142    EmitInstrWithCustomInserter(MachineInstr *MI,
143                                MachineBasicBlock *BB) const LLVM_OVERRIDE;
144  virtual SDValue LowerOperation(SDValue Op,
145                                 SelectionDAG &DAG) const LLVM_OVERRIDE;
146  virtual SDValue
147    LowerFormalArguments(SDValue Chain,
148                         CallingConv::ID CallConv, bool isVarArg,
149                         const SmallVectorImpl<ISD::InputArg> &Ins,
150                         DebugLoc DL, SelectionDAG &DAG,
151                         SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
152  virtual SDValue
153    LowerCall(CallLoweringInfo &CLI,
154              SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
155
156  virtual SDValue
157    LowerReturn(SDValue Chain,
158                CallingConv::ID CallConv, bool IsVarArg,
159                const SmallVectorImpl<ISD::OutputArg> &Outs,
160                const SmallVectorImpl<SDValue> &OutVals,
161                DebugLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
162
163private:
164  const SystemZSubtarget &Subtarget;
165  const SystemZTargetMachine &TM;
166
167  // Implement LowerOperation for individual opcodes.
168  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
169  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
170  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
171                             SelectionDAG &DAG) const;
172  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
173                                SelectionDAG &DAG) const;
174  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
175                            SelectionDAG &DAG) const;
176  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
177  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
178  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
179  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
180  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
181  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
182  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
183  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
184  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
185  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
186  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
187                           unsigned Opcode) const;
188  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
189  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
190  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
191
192  // Implement EmitInstrWithCustomInserter for individual operation types.
193  MachineBasicBlock *emitSelect(MachineInstr *MI,
194                                MachineBasicBlock *BB) const;
195  MachineBasicBlock *emitExt128(MachineInstr *MI,
196                                MachineBasicBlock *MBB,
197                                bool ClearEven, unsigned SubReg) const;
198  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
199                                          MachineBasicBlock *BB,
200                                          unsigned BinOpcode, unsigned BitSize,
201                                          bool Invert = false) const;
202  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
203                                          MachineBasicBlock *MBB,
204                                          unsigned CompareOpcode,
205                                          unsigned KeepOldMask,
206                                          unsigned BitSize) const;
207  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
208                                        MachineBasicBlock *BB) const;
209};
210} // end namespace llvm
211
212#endif // LLVM_TARGET_SystemZ_ISELLOWERING_H
213