SystemZISelLowering.h revision 80f54784da0bd42fb79176bbf447a31d69287fe3
1//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that SystemZ uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H 16#define LLVM_TARGET_SystemZ_ISELLOWERING_H 17 18#include "SystemZ.h" 19#include "llvm/CodeGen/MachineBasicBlock.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/Target/TargetLowering.h" 22 23namespace llvm { 24namespace SystemZISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 // Return with a flag operand. Operand 0 is the chain operand. 29 RET_FLAG, 30 31 // Calls a function. Operand 0 is the chain operand and operand 1 32 // is the target address. The arguments start at operand 2. 33 // There is an optional glue operand at the end. 34 CALL, 35 SIBCALL, 36 37 // Wraps a TargetGlobalAddress that should be loaded using PC-relative 38 // accesses (LARL). Operand 0 is the address. 39 PCREL_WRAPPER, 40 41 // Signed integer and floating-point comparisons. The operands are the 42 // two values to compare. 43 CMP, 44 45 // Likewise unsigned integer comparison. 46 UCMP, 47 48 // Branches if a condition is true. Operand 0 is the chain operand; 49 // operand 1 is the 4-bit condition-code mask, with bit N in 50 // big-endian order meaning "branch if CC=N"; operand 2 is the 51 // target block and operand 3 is the flag operand. 52 BR_CCMASK, 53 54 // Selects between operand 0 and operand 1. Operand 2 is the 55 // mask of condition-code values for which operand 0 should be 56 // chosen over operand 1; it has the same form as BR_CCMASK. 57 // Operand 3 is the flag operand. 58 SELECT_CCMASK, 59 60 // Evaluates to the gap between the stack pointer and the 61 // base of the dynamically-allocatable area. 62 ADJDYNALLOC, 63 64 // Extracts the value of a 32-bit access register. Operand 0 is 65 // the number of the register. 66 EXTRACT_ACCESS, 67 68 // Wrappers around the ISD opcodes of the same name. The output and 69 // first input operands are GR128s. The trailing numbers are the 70 // widths of the second operand in bits. 71 UMUL_LOHI64, 72 SDIVREM32, 73 SDIVREM64, 74 UDIVREM32, 75 UDIVREM64, 76 77 // Use MVC to copy bytes from one memory location to another. 78 // The first operand is the target address, the second operand is the 79 // source address, and the third operand is the constant length. 80 // This isn't a memory opcode because we'd need to attach two 81 // MachineMemOperands rather than one. 82 MVC, 83 84 // Use CLC to compare two blocks of memory, with the same comments 85 // as for MVC. 86 CLC, 87 88 // Use an MVST-based sequence to implement stpcpy(). 89 STPCPY, 90 91 // Use a CLST-based sequence to implement strcmp(). The two input operands 92 // are the addresses of the strings to compare. 93 STRCMP, 94 95 // Use an SRST-based sequence to search a block of memory. The first 96 // operand is the end address, the second is the start, and the third 97 // is the character to search for. CC is set to 1 on success and 2 98 // on failure. 99 SEARCH_STRING, 100 101 // Store the CC value in bits 29 and 28 of an integer. 102 IPM, 103 104 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 105 // ATOMIC_LOAD_<op>. 106 // 107 // Operand 0: the address of the containing 32-bit-aligned field 108 // Operand 1: the second operand of <op>, in the high bits of an i32 109 // for everything except ATOMIC_SWAPW 110 // Operand 2: how many bits to rotate the i32 left to bring the first 111 // operand into the high bits 112 // Operand 3: the negative of operand 2, for rotating the other way 113 // Operand 4: the width of the field in bits (8 or 16) 114 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 115 ATOMIC_LOADW_ADD, 116 ATOMIC_LOADW_SUB, 117 ATOMIC_LOADW_AND, 118 ATOMIC_LOADW_OR, 119 ATOMIC_LOADW_XOR, 120 ATOMIC_LOADW_NAND, 121 ATOMIC_LOADW_MIN, 122 ATOMIC_LOADW_MAX, 123 ATOMIC_LOADW_UMIN, 124 ATOMIC_LOADW_UMAX, 125 126 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 127 // 128 // Operand 0: the address of the containing 32-bit-aligned field 129 // Operand 1: the compare value, in the low bits of an i32 130 // Operand 2: the swap value, in the low bits of an i32 131 // Operand 3: how many bits to rotate the i32 left to bring the first 132 // operand into the high bits 133 // Operand 4: the negative of operand 2, for rotating the other way 134 // Operand 5: the width of the field in bits (8 or 16) 135 ATOMIC_CMP_SWAPW 136 }; 137} 138 139class SystemZSubtarget; 140class SystemZTargetMachine; 141 142class SystemZTargetLowering : public TargetLowering { 143public: 144 explicit SystemZTargetLowering(SystemZTargetMachine &TM); 145 146 // Override TargetLowering. 147 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE { 148 return MVT::i32; 149 } 150 virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE { 151 return MVT::i32; 152 } 153 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE; 154 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE; 155 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const 156 LLVM_OVERRIDE; 157 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const 158 LLVM_OVERRIDE; 159 virtual bool isTruncateFree(Type *, Type *) const LLVM_OVERRIDE; 160 virtual bool isTruncateFree(EVT, EVT) const LLVM_OVERRIDE; 161 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE; 162 virtual std::pair<unsigned, const TargetRegisterClass *> 163 getRegForInlineAsmConstraint(const std::string &Constraint, 164 MVT VT) const LLVM_OVERRIDE; 165 virtual TargetLowering::ConstraintType 166 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE; 167 virtual TargetLowering::ConstraintWeight 168 getSingleConstraintMatchWeight(AsmOperandInfo &info, 169 const char *constraint) const LLVM_OVERRIDE; 170 virtual void 171 LowerAsmOperandForConstraint(SDValue Op, 172 std::string &Constraint, 173 std::vector<SDValue> &Ops, 174 SelectionDAG &DAG) const LLVM_OVERRIDE; 175 virtual MachineBasicBlock * 176 EmitInstrWithCustomInserter(MachineInstr *MI, 177 MachineBasicBlock *BB) const LLVM_OVERRIDE; 178 virtual SDValue LowerOperation(SDValue Op, 179 SelectionDAG &DAG) const LLVM_OVERRIDE; 180 virtual bool allowTruncateForTailCall(Type *, Type *) const LLVM_OVERRIDE; 181 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const LLVM_OVERRIDE; 182 virtual SDValue 183 LowerFormalArguments(SDValue Chain, 184 CallingConv::ID CallConv, bool isVarArg, 185 const SmallVectorImpl<ISD::InputArg> &Ins, 186 SDLoc DL, SelectionDAG &DAG, 187 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE; 188 virtual SDValue 189 LowerCall(CallLoweringInfo &CLI, 190 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE; 191 192 virtual SDValue 193 LowerReturn(SDValue Chain, 194 CallingConv::ID CallConv, bool IsVarArg, 195 const SmallVectorImpl<ISD::OutputArg> &Outs, 196 const SmallVectorImpl<SDValue> &OutVals, 197 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE; 198 199private: 200 const SystemZSubtarget &Subtarget; 201 const SystemZTargetMachine &TM; 202 203 // Implement LowerOperation for individual opcodes. 204 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 205 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 206 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 207 SelectionDAG &DAG) const; 208 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 209 SelectionDAG &DAG) const; 210 SDValue lowerBlockAddress(BlockAddressSDNode *Node, 211 SelectionDAG &DAG) const; 212 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 213 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 214 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 215 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 216 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 217 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 218 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 219 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 220 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 221 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 222 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG, 223 unsigned Opcode) const; 224 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 225 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 226 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 227 228 // If the last instruction before MBBI in MBB was some form of COMPARE, 229 // try to replace it with a COMPARE AND BRANCH just before MBBI. 230 // CCMask and Target are the BRC-like operands for the branch. 231 // Return true if the change was made. 232 bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 233 MachineBasicBlock::iterator MBBI, 234 unsigned CCMask, 235 MachineBasicBlock *Target) const; 236 237 // Implement EmitInstrWithCustomInserter for individual operation types. 238 MachineBasicBlock *emitSelect(MachineInstr *MI, 239 MachineBasicBlock *BB) const; 240 MachineBasicBlock *emitCondStore(MachineInstr *MI, 241 MachineBasicBlock *BB, 242 unsigned StoreOpcode, unsigned STOCOpcode, 243 bool Invert) const; 244 MachineBasicBlock *emitExt128(MachineInstr *MI, 245 MachineBasicBlock *MBB, 246 bool ClearEven, unsigned SubReg) const; 247 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI, 248 MachineBasicBlock *BB, 249 unsigned BinOpcode, unsigned BitSize, 250 bool Invert = false) const; 251 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI, 252 MachineBasicBlock *MBB, 253 unsigned CompareOpcode, 254 unsigned KeepOldMask, 255 unsigned BitSize) const; 256 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI, 257 MachineBasicBlock *BB) const; 258 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI, 259 MachineBasicBlock *BB, 260 unsigned Opcode) const; 261 MachineBasicBlock *emitStringWrapper(MachineInstr *MI, 262 MachineBasicBlock *BB, 263 unsigned Opcode) const; 264}; 265} // end namespace llvm 266 267#endif // LLVM_TARGET_SystemZ_ISELLOWERING_H 268