SystemZISelLowering.h revision fb2e752e4175920d0531f2afc93a23d0cdf4db14 
1//==-- SystemZISelLowering.h - SystemZ DAG Lowering Interface ----*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that SystemZ uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16#define LLVM_TARGET_SystemZ_ISELLOWERING_H
17
18#include "SystemZ.h"
19#include "SystemZRegisterInfo.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22
23namespace llvm {
24  namespace SystemZISD {
25    enum {
26      FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28      /// Return with a flag operand. Operand 0 is the chain operand.
29      RET_FLAG,
30
31      /// CALL - These operations represent an abstract call
32      /// instruction, which includes a bunch of information.
33      CALL,
34
35      /// PCRelativeWrapper - PC relative address
36      PCRelativeWrapper,
37
38      /// CMP, UCMP - Compare instruction
39      CMP,
40      UCMP,
41
42      /// BRCOND - Conditional branch. Operand 0 is chain operand, operand 1 is
43      /// the block to branch if condition is true, operand 2 is condition code
44      /// and operand 3 is the flag operand produced by a CMP instruction.
45      BRCOND,
46
47      /// SELECT - Operands 0 and 1 are selection variables, operand 2 is
48      /// condition code and operand 3 is the flag operand.
49      SELECT
50    };
51  }
52
53  class SystemZSubtarget;
54  class SystemZTargetMachine;
55
56  class SystemZTargetLowering : public TargetLowering {
57  public:
58    explicit SystemZTargetLowering(SystemZTargetMachine &TM);
59
60    /// LowerOperation - Provide custom lowering hooks for some operations.
61    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
62
63    /// getTargetNodeName - This method returns the name of a target specific
64    /// DAG node.
65    virtual const char *getTargetNodeName(unsigned Opcode) const;
66
67    /// getFunctionAlignment - Return the Log2 alignment of this function.
68    virtual unsigned getFunctionAlignment(const Function *F) const {
69      return 1;
70    }
71
72    std::pair<unsigned, const TargetRegisterClass*>
73    getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
74    TargetLowering::ConstraintType
75    getConstraintType(const std::string &Constraint) const;
76
77    SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
78    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
79    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
80    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
81    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
82
83    SDValue EmitCmp(SDValue LHS, SDValue RHS,
84                    ISD::CondCode CC, SDValue &SystemZCC,
85                    SelectionDAG &DAG);
86
87
88    MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
89                                                   MachineBasicBlock *BB,
90                    DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
91
92  private:
93    SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
94                           CallingConv::ID CallConv, bool isVarArg,
95                           bool isTailCall,
96                           const SmallVectorImpl<ISD::OutputArg> &Outs,
97                           const SmallVectorImpl<ISD::InputArg> &Ins,
98                           DebugLoc dl, SelectionDAG &DAG,
99                           SmallVectorImpl<SDValue> &InVals);
100
101    SDValue LowerCCCArguments(SDValue Chain,
102                              CallingConv::ID CallConv,
103                              bool isVarArg,
104                              const SmallVectorImpl<ISD::InputArg> &Ins,
105                              DebugLoc dl,
106                              SelectionDAG &DAG,
107                              SmallVectorImpl<SDValue> &InVals);
108
109    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
110                            CallingConv::ID CallConv, bool isVarArg,
111                            const SmallVectorImpl<ISD::InputArg> &Ins,
112                            DebugLoc dl, SelectionDAG &DAG,
113                            SmallVectorImpl<SDValue> &InVals);
114
115    virtual SDValue
116      LowerFormalArguments(SDValue Chain,
117                           CallingConv::ID CallConv, bool isVarArg,
118                           const SmallVectorImpl<ISD::InputArg> &Ins,
119                           DebugLoc dl, SelectionDAG &DAG,
120                           SmallVectorImpl<SDValue> &InVals);
121    virtual SDValue
122      LowerCall(SDValue Chain, SDValue Callee,
123                CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
124                const SmallVectorImpl<ISD::OutputArg> &Outs,
125                const SmallVectorImpl<ISD::InputArg> &Ins,
126                DebugLoc dl, SelectionDAG &DAG,
127                SmallVectorImpl<SDValue> &InVals);
128
129    virtual SDValue
130      LowerReturn(SDValue Chain,
131                  CallingConv::ID CallConv, bool isVarArg,
132                  const SmallVectorImpl<ISD::OutputArg> &Outs,
133                  DebugLoc dl, SelectionDAG &DAG);
134
135    const SystemZSubtarget &Subtarget;
136    const SystemZTargetMachine &TM;
137    const SystemZRegisterInfo *RegInfo;
138  };
139} // namespace llvm
140
141#endif // LLVM_TARGET_SystemZ_ISELLOWERING_H
142