/external/llvm/lib/Target/XCore/ |
H A D | XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local 42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true); 44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); 54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local 56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); 65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local 67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC [all...] |
/external/llvm/lib/CodeGen/ |
H A D | LiveStackAnalysis.cpp | 59 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument 65 S2RCMap.insert(std::make_pair(Slot, RC)); 69 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 81 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local 82 if (RC) 83 OS << " [" << RC->getName() << "]\n";
|
H A D | AggressiveAntiDepBreaker.h | 44 /// RC - The register class 45 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::__anon25719
|
H A D | RegisterClassInfo.cpp | 76 /// compute - Compute the preferred allocation order for RC with reserved 79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 80 RCInfo &RCI = RegClass[RC->getID()]; 83 unsigned NumRegs = RC->getNumRegs(); 96 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); 132 // Check if RC is a proper sub-class. 133 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC)) 134 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 141 dbgs() << "AllocationOrder(" << RC->getName() << ") = ["; 155 const TargetRegisterClass *RC local [all...] |
H A D | CriticalAntiDepBreaker.cpp | 403 const TargetRegisterClass *RC, 406 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); 637 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] local 639 assert((AntiDepReg == 0 || RC != nullptr) && 641 if (RC == reinterpret_cast<TargetRegisterClass *>(-1)) 655 RC, ForbidRegs)) { 399 findSuitableFreeRegister(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, const TargetRegisterClass *RC, SmallVectorImpl<unsigned> &Forbid) argument
|
/external/llvm/lib/Target/ARM/ |
H A D | Thumb1InstrInfo.cpp | 53 const TargetRegisterClass *RC, 55 assert((RC == &ARM::tGPRRegClass || 59 if (RC == &ARM::tGPRRegClass || 81 const TargetRegisterClass *RC, 83 assert((RC == &ARM::tGPRRegClass || 87 if (RC == &ARM::tGPRRegClass || 51 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 79 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
|
H A D | Thumb2InstrInfo.cpp | 128 const TargetRegisterClass *RC, 141 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || 142 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || 143 RC == &ARM::GPRnopcRegClass) { 150 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 165 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI); 171 const TargetRegisterClass *RC, 183 if (RC 126 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 169 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIFixSGPRLiveRanges.cpp | 95 const TargetRegisterClass *RC = MRI.getRegClass(Def.getReg()); local 97 if (!TRI->isSGPRClass(RC))
|
H A D | SIRegisterInfo.cpp | 35 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument 37 return RC->getNumRegs(); 72 bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const { 73 if (!RC) { 76 return !hasVGPRs(RC); 79 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { 80 return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) || 81 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) || 82 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) || 83 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) || 108 getSubRegClass( const TargetRegisterClass *RC, unsigned SubIdx) const argument [all...] |
H A D | SIFixSGPRCopies.cpp | 143 const TargetRegisterClass *RC = MRI.getRegClass(Reg); local 144 RC = TRI->getSubRegClass(RC, SubReg); 149 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, 156 return RC; 165 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); local 166 return TRI->getSubRegClass(RC, SubReg); 224 const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg, local 226 MRI.constrainRegClass(Reg, RC); 229 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, local [all...] |
/external/chromium_org/third_party/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
H A D | SkPdfAppearanceCharacteristicsDictionary_autogen.cpp | 59 SkString SkPdfAppearanceCharacteristicsDictionary::RC(SkPdfNativeDoc* doc) { function in class:SkPdfAppearanceCharacteristicsDictionary 60 SkPdfNativeObject* ret = get("RC", ""); 68 return get("RC", "") != NULL;
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsMachineFunction.cpp | 83 const TargetRegisterClass *RC; local 85 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass; 87 RC = ST.isABI_N64() ? 90 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); 101 const TargetRegisterClass *RC; local 102 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass; 103 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC); 109 const TargetRegisterClass *RC = ST.isABI_N64() ? local 112 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 113 RC [all...] |
H A D | Mips16RegisterInfo.cpp | 65 const TargetRegisterClass *RC, 61 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument
|
H A D | MipsRegisterInfo.cpp | 57 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument 59 switch (RC->getID()) {
|
H A D | MipsSERegisterInfo.cpp | 169 const TargetRegisterClass *RC = local 172 unsigned Reg = RegInfo.createVirtualRegister(RC);
|
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.cpp | 29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument 30 if (RC == &NVPTX::Float32RegsRegClass) { 33 if (RC == &NVPTX::Float64RegsRegClass) { 35 } else if (RC == &NVPTX::Int64RegsRegClass) { 37 } else if (RC == &NVPTX::Int32RegsRegClass) { 39 } else if (RC == &NVPTX::Int16RegsRegClass) { 41 } else if (RC == &NVPTX::Int1RegsRegClass) { 43 } else if (RC == &NVPTX::SpecialRegsRegClass) { 51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { argument 52 if (RC [all...] |
/external/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 36 const CodeGenRegisterClass *RC; member in struct:__anon26590::InstructionMemo 255 const CodeGenRegisterClass *RC = nullptr; 259 RC = &Target.getRegisterClass(OpLeafRec); 261 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 263 RC = OrigDstRC; 268 if (!RC) 274 if (DstRC != RC && !DstRC->hasSubClass(RC)) 277 DstRC = RC; 651 OS << "&" << InstNS << Memo.RC [all...] |
/external/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
H A D | SkPdfAppearanceCharacteristicsDictionary_autogen.cpp | 59 SkString SkPdfAppearanceCharacteristicsDictionary::RC(SkPdfNativeDoc* doc) { function in class:SkPdfAppearanceCharacteristicsDictionary 60 SkPdfNativeObject* ret = get("RC", ""); 68 return get("RC", "") != NULL;
|
/external/clang/test/Layout/ |
H A D | ms-x86-pack-and-align.cpp | 450 struct RC { struct 456 RC c; 488 // CHECK-NEXT: 0 | struct RC 496 // CHECK-NEXT: 1 | struct RC c 531 // CHECK-X64-NEXT: 0 | struct RC 539 // CHECK-X64-NEXT: 1 | struct RC c 569 sizeof(RC)+
|
/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 66 // Compute all information about RC. 67 void compute(const TargetRegisterClass *RC) const; 69 // Return an up-to-date RCInfo for RC. 70 const RCInfo &get(const TargetRegisterClass *RC) const { 71 const RCInfo &RCI = RegClass[RC->getID()]; 73 compute(RC); 85 /// registers in RC in the current function. 86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { 87 return get(RC).NumRegs; 90 /// getOrder - Returns the preferred allocation order for RC 119 getMinCost(const TargetRegisterClass *RC) argument 127 getLastCostChange(const TargetRegisterClass *RC) argument [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 40 const TargetRegisterClass *RC, 53 if (RC == &MSP430::GR16RegClass) 57 else if (RC == &MSP430::GR8RegClass) 68 const TargetRegisterClass *RC, 81 if (RC == &MSP430::GR16RegClass) 84 else if (RC == &MSP430::GR8RegClass) 37 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 65 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
|
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 314 const TargetRegisterClass *RC, 320 VirtualRegister = MRI.createVirtualRegister(RC); 313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
|
H A D | AMDGPUInstrInfo.cpp | 126 const TargetRegisterClass *RC, 135 const TargetRegisterClass *RC, 233 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
|
/external/clang/lib/AST/ |
H A D | RawCommentList.cpp | 213 void RawCommentList::addComment(const RawComment &RC, argument 215 if (RC.isInvalid()) 221 RC.getLocStart())) { 228 if (RC.isOrdinary()) 234 Comments.push_back(new (Allocator) RawComment(RC)); 239 const RawComment &C2 = RC; 249 RC.isParseAllComments()); 251 Comments.push_back(new (Allocator) RawComment(RC));
|
/external/llvm/include/llvm/IR/ |
H A D | InlineAsm.h | 251 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) { argument 252 // Store RC + 1, reserve the value 0 to mean 'no register class'. 253 ++RC; 254 assert(RC <= 0x7fff && "Too large register class ID"); 256 return InputFlag | (RC << 16); 289 /// class constraint. Sets RC to the register class ID. 290 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) { argument 295 // stores RC + 1. 298 RC = High - 1;
|