/art/compiler/dex/ |
H A D | mir_graph.h | 261 static uint32_t GetStartUseIndex(Instruction::Code opcode); 270 * TODO: remove embedded DecodedInstruction to save space, keeping only opcode. Recover 280 Instruction::Code opcode; member in struct:art::MIR::DecodedInstruction 282 explicit DecodedInstruction():vA(0), vB(0), vB_wide(0), vC(0), opcode(Instruction::NOP) { 291 static bool IsPseudoMirOp(Instruction::Code opcode) { argument 292 return static_cast<int>(opcode) >= static_cast<int>(kMirOpFirst); 295 static bool IsPseudoMirOp(int opcode) { argument 296 return opcode >= static_cast<int>(kMirOpFirst); 300 return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) [all...] |
H A D | mir_graph.cc | 142 decoded_instruction->opcode = inst->Opcode(); 233 DCHECK(static_cast<int>(insn->dalvikInsn.opcode) == kMirOpCheck || 234 !MIR::DecodedInstruction::IsPseudoMirOp(insn->dalvikInsn.opcode)); 242 int opcode = p->dalvikInsn.opcode; local 249 if ((opcode == kMirOpCheck) || !MIR::DecodedInstruction::IsPseudoMirOp(opcode)) { 403 switch (insn->dalvikInsn.opcode) { 428 LOG(FATAL) << "Unexpected opcode(" << insn->dalvikInsn.opcode << ") wit 728 Instruction::Code opcode = insn->dalvikInsn.opcode; local 861 GetDataFlowAttributes(Instruction::Code opcode) argument 868 Instruction::Code opcode = mir->dalvikInsn.opcode; local 915 int opcode = mir->dalvikInsn.opcode; local 1219 int opcode = insn.opcode; local 1925 GetStartUseIndex(Instruction::Code opcode) argument [all...] |
H A D | mir_analysis.cc | 875 uint32_t ending_flags = analysis_attributes_[ending_bb->last_mir_insn->dalvikInsn.opcode]; 878 ending_flags = analysis_attributes_[ending_bb->last_mir_insn->dalvikInsn.opcode]; 905 if (MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) { 909 uint32_t flags = analysis_attributes_[mir->dalvikInsn.opcode]; 1125 if (mir->dalvikInsn.opcode >= Instruction::IGET && 1126 mir->dalvikInsn.opcode <= Instruction::SPUT_SHORT) { 1131 if (mir->dalvikInsn.opcode <= Instruction::IPUT_SHORT) { 1198 // Sort INVOKEs by method index, then by opcode, then by devirtualization target. 1241 if (mir->dalvikInsn.opcode >= Instruction::INVOKE_VIRTUAL && 1242 mir->dalvikInsn.opcode < [all...] |
H A D | vreg_analysis.cc | 218 if ((mir->dalvikInsn.opcode == Instruction::RETURN) || 219 (mir->dalvikInsn.opcode == Instruction::RETURN_WIDE) || 220 (mir->dalvikInsn.opcode == Instruction::RETURN_OBJECT)) { 253 Instruction::Code opcode = mir->dalvikInsn.opcode; local 254 int flags = MIR::DecodedInstruction::IsPseudoMirOp(opcode) ? 255 0 : Instruction::FlagsOf(mir->dalvikInsn.opcode); 265 if (move_result_mir && (move_result_mir->dalvikInsn.opcode != 279 if (((mir->dalvikInsn.opcode != Instruction::INVOKE_STATIC) && 280 (mir->dalvikInsn.opcode ! [all...] |
H A D | local_value_numbering.cc | 27 // Operations used for value map keys instead of actual opcode. 467 if ((Instruction::FlagsOf(mir->dalvikInsn.opcode) & Instruction::kInvoke) != 0) { 1080 uint16_t LocalValueNumbering::HandleAGet(MIR* mir, uint16_t opcode) { argument 1081 // uint16_t type = opcode - Instruction::AGET; 1086 uint16_t type = opcode - Instruction::AGET; 1097 if (opcode == Instruction::AGET_WIDE) { 1105 void LocalValueNumbering::HandleAPut(MIR* mir, uint16_t opcode) { argument 1106 int array_idx = (opcode == Instruction::APUT_WIDE) ? 2 : 1; 1113 uint16_t type = opcode - Instruction::APUT; 1114 uint16_t value = (opcode 1143 HandleIGet(MIR* mir, uint16_t opcode) argument 1178 HandleIPut(MIR* mir, uint16_t opcode) argument 1247 HandleSGet(MIR* mir, uint16_t opcode) argument 1282 HandleSPut(MIR* mir, uint16_t opcode) argument 1347 uint16_t opcode = mir->dalvikInsn.opcode; local [all...] |
H A D | local_value_numbering.h | 304 uint16_t HandleAGet(MIR* mir, uint16_t opcode); 305 void HandleAPut(MIR* mir, uint16_t opcode); 306 uint16_t HandleIGet(MIR* mir, uint16_t opcode); 307 void HandleIPut(MIR* mir, uint16_t opcode); 308 uint16_t HandleSGet(MIR* mir, uint16_t opcode); 309 void HandleSPut(MIR* mir, uint16_t opcode);
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H A D | mir_optimization_test.cc | 47 Instruction::Code opcode; member in struct:art::ClassInitCheckEliminationTest::MIRDef 75 #define DEF_MIR(opcode, bb, field_info) \ 76 { opcode, bb, field_info } 163 mir->dalvikInsn.opcode = def->opcode; 167 if (def->opcode >= Instruction::SGET && def->opcode <= Instruction::SPUT_SHORT) { 174 merged_df_flags |= MIRGraph::GetDataFlowAttributes(def->opcode);
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H A D | global_value_numbering_test.cc | 58 Instruction::Code opcode; member in struct:art::GlobalValueNumberingTest::MIRDef 90 #define DEF_CONST(bb, opcode, reg, value) \ 91 { bb, opcode, value, 0u, 0, { }, 1, { reg } } 92 #define DEF_CONST_WIDE(bb, opcode, reg, value) \ 93 { bb, opcode, value, 0u, 0, { }, 2, { reg, reg + 1 } } 94 #define DEF_CONST_STRING(bb, opcode, reg, index) \ 95 { bb, opcode, index, 0u, 0, { }, 1, { reg } } 96 #define DEF_IGET(bb, opcode, reg, obj, field_info) \ 97 { bb, opcode, 0u, field_info, 1, { obj }, 1, { reg } } 98 #define DEF_IGET_WIDE(bb, opcode, re [all...] |
H A D | frontend.cc | 584 int opcode = mir->dalvikInsn.opcode; local 587 opcode) != unsupport_list + unsupport_list_size) { 588 if (!MIR::DecodedInstruction::IsPseudoMirOp(opcode)) { 590 << mir->dalvikInsn.opcode; 592 VLOG(compiler) << "Unsupported extended MIR opcode : " 593 << MIRGraph::extended_mir_op_names_[opcode - kMirOpFirst]; 598 if (Instruction::INVOKE_VIRTUAL == opcode || 599 Instruction::INVOKE_SUPER == opcode || 600 Instruction::INVOKE_DIRECT == opcode || [all...] |
/art/compiler/dex/quick/arm/ |
H A D | target_arm.cc | 167 int opcode = lir->opcode; local 226 if (opcode == kThumbPush || opcode == kThumbPop) { 228 if ((opcode == kThumbPush) && (use_mask->Intersects(r8Mask))) { 231 } else if ((opcode == kThumbPop) && (def_mask->Intersects(r8Mask))) { 297 static char* DecodeRegList(int opcode, int vector, char* buf, size_t buf_size) { argument 304 if (opcode == kThumbPush && i == 8) { 306 } else if (opcode == kThumbPop && i == 8) { 470 DecodeRegList(lir->opcode, operan 736 GetTargetInstFlags(int opcode) argument 741 GetTargetInstName(int opcode) argument 746 GetTargetInstFmt(int opcode) argument [all...] |
H A D | assemble_arm.cc | 24 * opcode: ArmOpcode enum 25 * skeleton: pre-designated bit-pattern for this opcode 39 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \ 42 {k3, k3s, k3e}}, opcode, flags, name, fmt, size, fixup} 1073 int opcode = lir->opcode; local 1074 if (IsPseudoLirOp(opcode)) { 1075 if (UNLIKELY(opcode == kPseudoPseudoAlign4)) { 1076 // Note: size for this opcode will be either 0 or 2 depending on final alignment. 1084 const ArmEncodingMap *encoder = &EncodingMap[lir->opcode]; [all...] |
H A D | fp_arm.cc | 23 void ArmMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, argument 32 switch (opcode) { 60 LOG(FATAL) << "Unexpected opcode: " << opcode; 69 void ArmMir2Lir::GenArithOpDouble(Instruction::Code opcode, argument 74 switch (opcode) { 102 LOG(FATAL) << "Unexpected opcode: " << opcode; 116 void ArmMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) { argument 121 switch (opcode) { 265 GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument [all...] |
/art/compiler/dex/quick/x86/ |
H A D | codegen_x86.h | 134 const char* GetTargetInstFmt(int opcode) OVERRIDE; 135 const char* GetTargetInstName(int opcode) OVERRIDE; 138 uint64_t GetTargetInstFlags(int opcode) OVERRIDE; 151 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 153 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 155 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 157 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 170 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 172 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 174 void GenShiftImmOpLong(Instruction::Code opcode, RegLocatio [all...] |
H A D | assemble_x86.cc | 100 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */, 106 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */, 112 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */, 118 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */, 124 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */, 130 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */, 136 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */, 142 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */, 326 #define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 327 { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, [all...] |
H A D | target_x86.cc | 291 if (lir->opcode == kX86RepneScasw) { 557 bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) { argument 558 switch (opcode) { 594 if (ProvidesFullMemoryBarrier(static_cast<X86OpCode>(mem_barrier->opcode)) == false) { 756 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 789 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 792 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 894 uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { argument 895 DCHECK(!IsPseudoLirOp(opcode)); 899 GetTargetInstName(int opcode) argument 904 GetTargetInstFmt(int opcode) argument 1803 AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir) argument 1883 int opcode = 0; local 1913 int opcode = 0; local 1944 int opcode = 0; local 1974 int opcode = 0; local 2024 int opcode = 0; local 2052 int opcode = 0; local 2077 int opcode = 0; local 2128 MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m0, uint32_t m1, uint32_t m2, uint32_t m3) argument 2150 int opcode = 0; local [all...] |
H A D | fp_x86.cc | 24 void X86Mir2Lir::GenArithOpFloat(Instruction::Code opcode, argument 33 switch (opcode) { 58 LOG(FATAL) << "Unexpected opcode: " << opcode; 75 void X86Mir2Lir::GenArithOpDouble(Instruction::Code opcode, argument 86 switch (opcode) { 111 LOG(FATAL) << "Unexpected opcode: " << opcode; 159 int opcode = is_double ? kX86Fstp64M : kX86Fstp32M; local 161 LIR *fstp = NewLIR2NoDest(opcode, rs_rX86_S 193 GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) argument 419 int opcode = is_double ? kX86Fst64M : kX86Fst32M; local [all...] |
H A D | int_x86.cc | 108 // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode 291 // TODO: use GenSelectConst32 and handle additional opcode patterns such as 1295 void X86Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, argument 1299 switch (opcode) { 1305 Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 1314 switch (opcode) { 1321 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1326 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, false); 1331 GenMulLong(opcode, rl_dest, rl_src1, rl_src2); 1336 GenDivRemLong(opcode, rl_des 2024 X86OpCode opcode = kX86Bkpt; local 2037 X86OpCode opcode = kX86Bkpt; local 2167 GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, int shift_amount) argument 2252 GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift) argument 2275 GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument 2692 GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, RegLocation rl_rhs) argument 2967 GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_shift) argument [all...] |
/art/compiler/dex/quick/arm64/ |
H A D | fp_arm64.cc | 24 void Arm64Mir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, argument 29 switch (opcode) { 57 LOG(FATAL) << "Unexpected opcode: " << opcode; 66 void Arm64Mir2Lir::GenArithOpDouble(Instruction::Code opcode, argument 71 switch (opcode) { 105 LOG(FATAL) << "Unexpected opcode: " << opcode; 119 void Arm64Mir2Lir::GenConversion(Instruction::Code opcode, argument 126 switch (opcode) { 251 GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument [all...] |
H A D | int_arm64.cc | 63 void Arm64Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, argument 66 switch (opcode) { 80 LOG(FATAL) << "Unexpected case: " << opcode; 103 int opcode; // The opcode. local 119 opcode = kA64Csinc4rrrc; 122 opcode = kA64Csinv4rrrc; 125 opcode = kA64Csinc4rrrc; 128 opcode = kA64Csneg4rrrc; 131 opcode 207 int opcode = is_wide ? WIDE(kA64Csel4rrrc) : kA64Csel4rrrc; local 265 ArmOpcode opcode = (arm_cond == kArmCondEq) ? kA64Cbz2rt : kA64Cbnz2rt; local 271 ArmOpcode opcode = kA64Cbz2rt; local 304 ArmOpcode opcode = kA64Brk1d; local 946 ArmOpcode opcode = reg.Is64Bit() ? WIDE(kA64Subs3rRd) : UNWIDE(kA64Subs3rRd); local 1003 GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_div) argument 1050 GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument 1295 GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift) argument 1327 GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument [all...] |
H A D | assemble_arm64.cc | 50 * opcode: ArmOpcode enum 60 #define ENCODING_MAP(opcode, variants, a0k, a0s, a0e, a1k, a1s, a1e, a2k, a2s, a2e, \ 63 {a3k, a3s, a3e}}, opcode, flags, name, fmt, 4, fixup} 654 bool opcode_is_wide = IS_WIDE(lir->opcode); 655 ArmOpcode opcode = UNWIDE(lir->opcode); local 657 if (UNLIKELY(IsPseudoLirOp(opcode))) { 662 const ArmEncodingMap *encoder = &EncodingMap[opcode]; 666 DCHECK(!opcode_is_wide || IS_WIDE(encoder->opcode)); 750 << "(" << UNWIDE(encoder->opcode) << ", " << encode 954 ArmOpcode opcode = UNWIDE(lir->opcode); local 965 ArmOpcode opcode = UNWIDE(lir->opcode); local [all...] |
H A D | target_arm64.cc | 357 int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) : 407 snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_FWIDE(lir->opcode)) ? 'd' : 's', 411 bool is_wide = IS_WIDE(lir->opcode); 453 snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4)); 465 strcpy(tbuf, (IS_WIDE(lir->opcode)) ? ", lsl #3" : ", lsl #2"); 476 bool is_wide = IS_WIDE(lir->opcode); 486 bool is_wide = IS_WIDE(lir->opcode); 567 return (lir->opcode == kA64B1t); 584 if (UNWIDE(Arm64Mir2Lir::EncodingMap[i].opcode) != i) { 587 << static_cast<int>(Arm64Mir2Lir::EncodingMap[i].opcode); 774 GetTargetInstFlags(int opcode) argument 779 GetTargetInstName(int opcode) argument 784 GetTargetInstFmt(int opcode) argument [all...] |
H A D | codegen_arm64.h | 128 const char* GetTargetInstFmt(int opcode) OVERRIDE; 129 const char* GetTargetInstName(int opcode) OVERRIDE; 132 uint64_t GetTargetInstFlags(int opcode) OVERRIDE; 140 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 142 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 148 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 150 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 152 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 154 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 156 void GenConversion(Instruction::Code opcode, RegLocatio [all...] |
/art/compiler/dex/quick/mips/ |
H A D | target_mips.cc | 559 return (lir->opcode == kMipsB); 577 if (MipsMir2Lir::EncodingMap[i].opcode != i) { 580 << static_cast<int>(MipsMir2Lir::EncodingMap[i].opcode); 590 uint64_t MipsMir2Lir::GetTargetInstFlags(int opcode) { argument 591 DCHECK(!IsPseudoLirOp(opcode)); 592 return MipsMir2Lir::EncodingMap[opcode].flags; 595 const char* MipsMir2Lir::GetTargetInstName(int opcode) { argument 596 DCHECK(!IsPseudoLirOp(opcode)); 597 return MipsMir2Lir::EncodingMap[opcode].name; 600 const char* MipsMir2Lir::GetTargetInstFmt(int opcode) { argument [all...] |
/art/compiler/dex/quick/ |
H A D | mir_to_lir.h | 170 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 171 int16_t opcode; member in struct:art::LIR 242 DexOffset vaddr; // Dalvik offset of parent opcode. 544 LIR* GenerateTargetLabel(int opcode = kPseudoTargetLabel); 605 static bool IsPseudoLirOp(int opcode) { argument 606 return (opcode < 0); 676 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 678 LIR* NewLIR0(int opcode); 679 LIR* NewLIR1(int opcode, int dest); 680 LIR* NewLIR2(int opcode, in 1447 InexpensiveConstantInt(int32_t value, Instruction::Code opcode) argument [all...] |
/art/compiler/utils/arm/ |
H A D | assembler_thumb2.cc | 613 Opcode opcode, 622 bool can_contain_high_register = (opcode == MOV) 623 || ((opcode == ADD || opcode == SUB) && (rn == rd)); 627 // There are high register instructions available for this opcode. 634 if ((opcode == ADD || opcode == SUB) && so.IsImmediate()) { 646 } else if (opcode == ADD && rd != SP && rn == SP) { // 10 bit immediate. 650 } else if (opcode == SUB && rd != SP && rn == SP) { 673 if (opcode 612 Is32BitDataProcessing(Condition cond, Opcode opcode, int set_cc, Register rn, Register rd, const ShifterOperand& so) argument 730 Emit32BitDataProcessing(Condition cond, Opcode opcode, int set_cc, Register rn, Register rd, const ShifterOperand& so) argument 810 Emit16BitDataProcessing(Condition cond, Opcode opcode, int set_cc, Register rn, Register rd, const ShifterOperand& so) argument 939 Emit16BitAddSub(Condition cond, Opcode opcode, int set_cc, Register rn, Register rd, const ShifterOperand& so) argument 1076 EmitDataProcessing(Condition cond, Opcode opcode, int set_cc, Register rn, Register rd, const ShifterOperand& so) argument 1095 uint16_t opcode = 0; local 1115 uint16_t opcode = 0; local 1137 uint16_t opcode = 0; local 1153 uint16_t opcode = 0; local 1861 EmitVFPsss(Condition cond, int32_t opcode, SRegister sd, SRegister sn, SRegister sm) argument 1879 EmitVFPddd(Condition cond, int32_t opcode, DRegister dd, DRegister dn, DRegister dm) argument 1897 EmitVFPsd(Condition cond, int32_t opcode, SRegister sd, DRegister dm) argument 1912 EmitVFPds(Condition cond, int32_t opcode, DRegister dd, SRegister sm) argument [all...] |