/art/test/065-mismatched-implements/src/ |
H A D | Indirect.java | 25 Base base = new Base();
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/art/test/066-mismatched-super/src/ |
H A D | Indirect.java | 25 Base base = new Base();
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/art/compiler/utils/arm64/ |
H A D | assembler_arm64.cc | 18 #include "base/logging.h" 93 Register base, int32_t offset) { 96 ___ Strb(reg_w(source), MEM_OP(reg_x(base), offset)); 99 ___ Strh(reg_w(source), MEM_OP(reg_x(base), offset)); 102 ___ Str(reg_w(source), MEM_OP(reg_x(base), offset)); 109 void Arm64Assembler::StoreToOffset(Register source, Register base, int32_t offset) { argument 111 ___ Str(reg_x(source), MEM_OP(reg_x(base), offset)); 114 void Arm64Assembler::StoreSToOffset(SRegister source, Register base, int32_t offset) { argument 115 ___ Str(reg_s(source), MEM_OP(reg_x(base), offset)); 118 void Arm64Assembler::StoreDToOffset(DRegister source, Register base, int32_ argument 92 StoreWToOffset(StoreOperandType type, WRegister source, Register base, int32_t offset) argument 215 LoadWFromOffset(LoadOperandType type, WRegister dest, Register base, int32_t offset) argument 240 LoadFromOffset(Register dest, Register base, int32_t offset) argument 246 LoadSFromOffset(SRegister dest, Register base, int32_t offset) argument 251 LoadDFromOffset(DRegister dest, Register base, int32_t offset) argument 256 Load(Arm64ManagedRegister dest, Register base, int32_t offset, size_t size) argument 296 Arm64ManagedRegister base = m_base.AsArm64(); local 304 Arm64ManagedRegister base = m_base.AsArm64(); local 395 Arm64ManagedRegister base = src_base.AsArm64(); local 414 Arm64ManagedRegister base = m_dest_base.AsArm64(); local 509 Arm64ManagedRegister base = m_base.AsArm64(); local 518 Arm64ManagedRegister base = m_base.AsArm64(); local 529 Call(FrameOffset base, Offset offs, ManagedRegister m_scratch) argument [all...] |
H A D | assembler_arm64.h | 24 #include "base/logging.h" 130 void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE; 131 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE; 184 // Call to address held at [base+offset]. 185 void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE; 186 void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE; 223 Register base, int32_t offset); 224 void StoreToOffset(Register source, Register base, int32_t offset); 225 void StoreSToOffset(SRegister source, Register base, int32_t offset); 226 void StoreDToOffset(DRegister source, Register base, int32_ [all...] |
/art/test/106-exceptions2/src/ |
H A D | Main.java | 134 Main base = new Main(); 138 base.ifoo = x; 139 return base.noThrow(a,b,c); 143 Main base = new Main(); 150 base.ifoo = x; 151 return base.checkThrow(a,b,c,d,e,f);
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/art/compiler/dex/ |
H A D | local_value_numbering.h | 160 // Maps instance field "location" (derived from base, field_id and type) to value name. 167 uint16_t base; // Or array. member in struct:art::LocalValueNumbering::EscapedIFieldClobberKey 173 return base == other.base && type == other.type && field_id == other.field_id; 179 // Compare base first. This makes sequential iteration respect the order of base. 180 if (lhs.base != rhs.base) { 181 return lhs.base < rhs.base; 197 uint16_t base; member in struct:art::LocalValueNumbering::EscapedArrayClobberKey [all...] |
H A D | global_value_numbering.h | 20 #include "base/macros.h" 141 uint16_t base; member in struct:art::GlobalValueNumbering::ArrayLocation 147 if (lhs.base != rhs.base) { 148 return lhs.base < rhs.base; 157 uint16_t GetArrayLocation(uint16_t base, uint16_t index); 159 // Get the array base from an array location. 161 return array_location_reverse_map_[location]->first.base;
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/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64.h | 21 #include "base/macros.h" 79 Register base() const { function in class:art::x86_64::Operand 118 void SetSIB(ScaleFactor scale, CpuRegister index, CpuRegister base) { argument 121 if (base.NeedsRex()) { 128 static_cast<uint8_t>(base.LowBits()); 166 Address(CpuRegister base, int32_t disp) { argument 167 Init(base, disp); 170 Address(CpuRegister base, Offset disp) { argument 171 Init(base, disp.Int32Value()); 174 Address(CpuRegister base, FrameOffse argument 179 Address(CpuRegister base, MemberOffset disp) argument 183 Init(CpuRegister base, int32_t disp) argument 212 Address(CpuRegister base, CpuRegister index, ScaleFactor scale, int32_t disp) argument [all...] |
/art/test/003-omnibus-opcodes/src/ |
H A D | MethodCall.java | 56 MethodCallBase base = inst; 57 base.tryThing();
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/art/compiler/utils/ |
H A D | assembler_test.h | 60 std::string base = fmt; local 62 size_t reg_index = base.find("{reg}"); 67 base.replace(reg_index, 5, reg_string); 73 str += base; 86 std::string base = fmt; local 88 size_t reg1_index = base.find("{reg1}"); 93 base.replace(reg1_index, 6, reg_string); 96 size_t reg2_index = base.find("{reg2}"); 101 base.replace(reg2_index, 6, reg_string); 107 str += base; 124 std::string base = fmt; local 160 std::string base = fmt; local [all...] |
/art/runtime/arch/x86/ |
H A D | thread_x86.cc | 23 #include "base/macros.h" 47 const uintptr_t base = reinterpret_cast<uintptr_t>(this); local 64 entry.base0 = (base & 0x0000ffff); 65 entry.base1 = (base & 0x00ff0000) >> 16; 66 entry.base2 = (base & 0xff000000) >> 24; 100 ldt_entry.base_addr = base;
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/art/compiler/utils/x86/ |
H A D | assembler_x86.h | 21 #include "base/macros.h" 67 Register base() const { function in class:art::x86::Operand 98 void SetSIB(ScaleFactor scale, Register index, Register base) { argument 101 encoding_[1] = (scale << 6) | (index << 3) | base; 138 Address(Register base, int32_t disp) { argument 139 Init(base, disp); 142 Address(Register base, Offset disp) { argument 143 Init(base, disp.Int32Value()); 146 Address(Register base, FrameOffset disp) { argument 147 CHECK_EQ(base, ES 151 Address(Register base, MemberOffset disp) argument 155 Init(Register base, int32_t disp) argument 178 Address(Register base, Register index, ScaleFactor scale, int32_t disp) argument [all...] |
/art/runtime/ |
H A D | Android.mk | 24 base/allocator.cc \ 25 base/bit_vector.cc \ 26 base/hex_dump.cc \ 27 base/logging.cc \ 28 base/mutex.cc \ 29 base/scoped_flock.cc \ 30 base/stringpiece.cc \ 31 base/stringprintf.cc \ 32 base/timing_logger.cc \ 33 base/unix_fil [all...] |
H A D | monitor_pool.h | 22 #include "base/allocator.h" 28 #include "base/stl_util.h" // STLDeleteElements 121 uintptr_t base = *(monitor_chunks_.LoadRelaxed()+index); local 122 return reinterpret_cast<Monitor*>(base + offset_in_chunk);
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/art/test/072-precise-gc/src/ |
H A D | Main.java | 61 static String generateString(String base, int num) { argument 62 return base + num;
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/art/compiler/utils/mips/ |
H A D | assembler_mips.cc | 19 #include "base/casts.h" 477 void MipsAssembler::LoadFromOffset(LoadOperandType type, Register reg, Register base, argument 481 Lb(reg, base, offset); 484 Lbu(reg, base, offset); 487 Lh(reg, base, offset); 490 Lhu(reg, base, offset); 493 Lw(reg, base, offset); 503 void MipsAssembler::LoadSFromOffset(FRegister reg, Register base, int32_t offset) { argument 504 Lwc1(reg, base, offset); 507 void MipsAssembler::LoadDFromOffset(DRegister reg, Register base, int32_ argument 511 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset) argument 531 StoreFToOffset(FRegister reg, Register base, int32_t offset) argument 535 StoreDToOffset(DRegister reg, Register base, int32_t offset) argument 683 LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs) argument 694 LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) argument 906 MipsManagedRegister base = mbase.AsMips(); local 916 Call(FrameOffset base, Offset offset, ManagedRegister mscratch) argument [all...] |
H A D | assembler_mips.h | 22 #include "base/macros.h" 141 void LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset); 142 void LoadSFromOffset(FRegister reg, Register base, int32_t offset); 143 void LoadDFromOffset(DRegister reg, Register base, int32_t offset); 144 void StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset); 145 void StoreFToOffset(FRegister reg, Register base, int32_t offset); 146 void StoreDToOffset(DRegister reg, Register base, int32_t offset); 195 void LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs) OVERRIDE; 197 void LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) OVERRIDE; 261 // Call to address held at [base [all...] |
/art/runtime/gc/space/ |
H A D | dlmalloc_space.h | 43 // base address is not guaranteed to be granted, if it is required, 140 void* CreateAllocator(void* base, size_t morecore_start, size_t initial_size, 142 return CreateMspace(base, morecore_start, initial_size); 144 static void* CreateMspace(void* base, size_t morecore_start, size_t initial_size);
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H A D | rosalloc_space.h | 38 // base address is not guaranteed to be granted, if it is required, 137 void* CreateAllocator(void* base, size_t morecore_start, size_t initial_size, 139 return CreateRosAlloc(base, morecore_start, initial_size, maximum_size, low_memory_mode); 141 static allocator::RosAlloc* CreateRosAlloc(void* base, size_t morecore_start, size_t initial_size,
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/art/build/ |
H A D | Android.oat.mk | 36 --base=$$(LIBART_IMG_HOST_BASE_ADDRESS) --instruction-set=$$($(1)ART_HOST_ARCH) \ 59 --base=$$(LIBART_IMG_TARGET_BASE_ADDRESS) --instruction-set=$$($(1)TARGET_ARCH) \
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H A D | Android.gtest.mk | 73 runtime/base/bit_field_test.cc \ 74 runtime/base/bit_vector_test.cc \ 75 runtime/base/hash_set_test.cc \ 76 runtime/base/hex_dump_test.cc \ 77 runtime/base/histogram_test.cc \ 78 runtime/base/mutex_test.cc \ 79 runtime/base/scoped_flock_test.cc \ 80 runtime/base/stringprintf_test.cc \ 81 runtime/base/timing_logger_test.cc \ 82 runtime/base/unix_fil [all...] |
/art/compiler/ |
H A D | common_compiler_test.cc | 147 const byte* base = reinterpret_cast<const byte*>(code); // Base of data points at code. local 148 base -= kPointerSize; // Move backward so that code_offset != 0. 150 return OatFile::OatMethod(base, code_offset); 249 uintptr_t base = RoundDown(data, kPageSize); local 251 uintptr_t len = limit - base; 252 int result = mprotect(reinterpret_cast<void*>(base), len, PROT_READ | PROT_WRITE | PROT_EXEC); 258 __builtin___clear_cache(reinterpret_cast<void*>(base), reinterpret_cast<void*>(base + len));
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/art/compiler/utils/arm/ |
H A D | assembler_arm32.cc | 19 #include "base/logging.h" 264 Register base, 267 EmitMultiMemOp(cond, am, true, base, regs); 272 Register base, 275 EmitMultiMemOp(cond, am, false, base, regs); 601 Register base, 603 CHECK_NE(base, kNoRegister); 609 (static_cast<int32_t>(base) << kRnShift) | 1327 Register base, 1331 CHECK(base ! 263 ldm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument 271 stm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument 598 EmitMultiMemOp(Condition cond, BlockAddressMode am, bool load, Register base, RegList regs) argument 1325 LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument 1365 LoadSFromOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument 1383 LoadDFromOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument 1401 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument 1436 StoreSToOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument 1454 StoreDToOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument [all...] |
H A D | assembler_thumb2.cc | 19 #include "base/logging.h" 318 Register base, 333 ldr(static_cast<Register>(reg), Address(base, kRegisterSize, Address::PostIndex), cond); 335 EmitMultiMemOp(cond, am, true, base, regs); 341 Register base, 357 str(static_cast<Register>(reg), Address(base, -kRegisterSize, strmode), cond); 359 EmitMultiMemOp(cond, am, false, base, regs); 1410 Register base, 1412 CHECK_NE(base, kNoRegister); 1453 base << 1 317 ldm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument 340 stm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument 1407 EmitMultiMemOp(Condition cond, BlockAddressMode am, bool load, Register base, RegList regs) argument 2375 LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument 2415 LoadSFromOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument 2433 LoadDFromOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument 2451 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument 2486 StoreSToOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument 2504 StoreDToOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument [all...] |
/art/compiler/dex/quick/arm64/ |
H A D | int_arm64.cc | 470 uint64_t base = DecodeLogicalImmediate(/*is_wide*/true, magic_table[lit].magic64_base); local 473 reconstructed_imm = base ^ eor; 475 reconstructed_imm = base + 1; 1173 // Offset base, then use indexed load 1420 static void SpillCoreRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) { argument 1427 m2l->NewLIR3(WIDE(kA64Str3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset); 1430 RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset); 1436 static void SpillFPRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) { argument 1443 m2l->NewLIR3(FWIDE(kA64Str3fXD), RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(), 1447 RegStorage::FloatSolo64(reg1).GetReg(), base 1452 SpillRegsPreSub(Arm64Mir2Lir* m2l, RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size) argument 1474 SpillRegsPreIndexed(Arm64Mir2Lir* m2l, RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size) argument 1589 SpillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size) argument 1604 UnSpillCoreRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) argument 1620 UnSpillFPRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) argument 1636 UnspillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size) argument [all...] |