/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64.cc | 77 void X86_64Assembler::pushq(const Immediate& imm) { argument 79 CHECK(imm.is_int32()); // pushq only supports 32b immediate. 80 if (imm.is_int8()) { 82 EmitUint8(imm.value() & 0xFF); 85 EmitImmediate(imm); 105 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { argument 107 if (imm.is_int32()) { 112 EmitInt32(static_cast<int32_t>(imm.value())); 116 EmitInt64(imm.value()); 121 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { argument 177 movl(const Address& dst, const Immediate& imm) argument 234 movb(const Address& dst, const Immediate& imm) argument 841 cmpl(CpuRegister reg, const Immediate& imm) argument 872 cmpq(CpuRegister reg, const Immediate& imm) argument 912 cmpl(const Address& address, const Immediate& imm) argument 969 andl(CpuRegister dst, const Immediate& imm) argument 976 andq(CpuRegister reg, const Immediate& imm) argument 992 orl(CpuRegister dst, const Immediate& imm) argument 1015 xorq(CpuRegister dst, const Immediate& imm) argument 1075 addl(CpuRegister reg, const Immediate& imm) argument 1082 addq(CpuRegister reg, const Immediate& imm) argument 1115 addl(const Address& address, const Immediate& imm) argument 1130 subl(CpuRegister reg, const Immediate& imm) argument 1137 subq(CpuRegister reg, const Immediate& imm) argument 1192 imull(CpuRegister reg, const Immediate& imm) argument 1243 shll(CpuRegister reg, const Immediate& imm) argument 1253 shrl(CpuRegister reg, const Immediate& imm) argument 1258 shrq(CpuRegister reg, const Immediate& imm) argument 1268 sarl(CpuRegister reg, const Immediate& imm) argument 1294 enter(const Immediate& imm) argument 1316 ret(const Immediate& imm) argument 1432 AddImmediate(CpuRegister reg, const Immediate& imm) argument 1535 EmitImmediate(const Immediate& imm) argument 1585 EmitGenericShift(bool wide, int reg_or_opcode, CpuRegister reg, const Immediate& imm) argument 1851 StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister) argument 1856 StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister) argument [all...] |
H A D | assembler_x86_64.h | 268 void pushq(const Immediate& imm); 282 void movl(const Address& dst, const Immediate& imm); 290 void movb(const Address& dst, const Immediate& imm); 381 void cmpl(CpuRegister reg, const Immediate& imm); 385 void cmpl(const Address& address, const Immediate& imm); 388 void cmpq(CpuRegister reg0, const Immediate& imm); 392 void testl(CpuRegister reg, const Immediate& imm); 396 void andl(CpuRegister dst, const Immediate& imm); 398 void andq(CpuRegister dst, const Immediate& imm); 400 void orl(CpuRegister dst, const Immediate& imm); [all...] |
/art/compiler/utils/x86/ |
H A D | assembler_x86.h | 227 void pushl(const Immediate& imm); 237 void movl(const Address& dst, const Immediate& imm); 246 void movb(const Address& dst, const Immediate& imm); 340 void cmpl(Register reg, const Immediate& imm); 345 void cmpl(const Address& address, const Immediate& imm); 348 void testl(Register reg, const Immediate& imm); 351 void andl(Register dst, const Immediate& imm); 354 void orl(Register dst, const Immediate& imm); 358 void xorl(Register dst, const Immediate& imm); 361 void addl(Register reg, const Immediate& imm); [all...] |
H A D | assembler_x86.cc | 80 void X86Assembler::pushl(const Immediate& imm) { argument 82 if (imm.is_int8()) { 84 EmitUint8(imm.value() & 0xFF); 87 EmitImmediate(imm); 105 void X86Assembler::movl(Register dst, const Immediate& imm) { argument 108 EmitImmediate(imm); 133 void X86Assembler::movl(const Address& dst, const Immediate& imm) { argument 137 EmitImmediate(imm); 191 void X86Assembler::movb(const Address& dst, const Immediate& imm) { argument 195 CHECK(imm 755 cmpl(Register reg, const Immediate& imm) argument 796 cmpl(const Address& address, const Immediate& imm) argument 848 andl(Register dst, const Immediate& imm) argument 861 orl(Register dst, const Immediate& imm) argument 873 xorl(Register dst, const Immediate& imm) argument 878 addl(Register reg, const Immediate& imm) argument 891 addl(const Address& address, const Immediate& imm) argument 897 adcl(Register reg, const Immediate& imm) argument 924 subl(Register reg, const Immediate& imm) argument 958 imull(Register reg, const Immediate& imm) argument 1009 sbbl(Register reg, const Immediate& imm) argument 1048 shll(Register reg, const Immediate& imm) argument 1058 shrl(Register reg, const Immediate& imm) argument 1068 sarl(Register reg, const Immediate& imm) argument 1100 enter(const Immediate& imm) argument 1122 ret(const Immediate& imm) argument 1241 AddImmediate(Register reg, const Immediate& imm) argument 1339 EmitImmediate(const Immediate& imm) argument 1385 EmitGenericShift(int reg_or_opcode, Register reg, const Immediate& imm) argument 1492 StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister) argument 1497 StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister) argument [all...] |
/art/disassembler/ |
H A D | disassembler_arm.cc | 164 uint32_t imm = (instruction & 0xff); local 165 value = (imm >> (2 * rotate)) | (imm << (32 - (2 * rotate))); 408 uint64_t imm = imm8; local 410 case 3: imm <<= 8; // Fall through. 411 case 2: imm <<= 8; // Fall through. 412 case 1: imm <<= 8; // Fall through. 413 case 0: return static_cast<int64_t>((imm << 32) | imm); 414 case 5: imm << [all...] |
/art/compiler/dex/quick/x86/ |
H A D | assemble_x86.cc | 294 arr, arr_kind, arr_flags, imm, \ 297 { kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #reg, b_format "!0r" }, \ 298 { kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #mem, b_format "[!0r+!1d]" }, \ 299 { kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \ 300 { kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #reg, hw_format "!0r" }, \ 301 { kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #mem, hw_format "[!0r+!1d]" }, \ 302 { kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \ 303 { kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #reg, w_format "!0r" }, \ 304 { kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #mem, w_format "[!0r+!1d]" }, \ 305 { kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 1022 EmitImm(const X86EncodingMap* entry, int64_t imm) argument 1149 EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm) argument 1159 EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, int32_t disp, int32_t imm) argument 1201 EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm) argument 1214 EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) argument 1227 EmitMemRegImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) argument 1233 EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) argument 1247 EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) argument 1259 EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm) argument 1287 EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) argument 1339 EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm) argument [all...] |
H A D | codegen_x86.h | 434 void EmitImm(const X86EncodingMap* entry, int64_t imm); 447 void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 449 int32_t raw_disp, int32_t imm); 452 void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); 454 int32_t imm); 456 int32_t imm); 457 void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 458 void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); 459 void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); 460 void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); [all...] |
H A D | int_x86.cc | 602 int imm, bool is_div) { 606 if (imm == 1) { 615 } else if (imm == -1) { // handle 0x80000000 / -1 special case. 631 } else if (is_div && IsPowerOfTwo(std::abs(imm))) { 639 NewLIR3(kX86Lea32RM, rl_result.reg.GetReg(), rl_src.reg.GetReg(), std::abs(imm) - 1); 642 int shift_amount = LowestSetBit(imm); 644 if (imm < 0) { 648 CHECK(imm <= -2 || imm >= 2); 654 CalculateMagicAndShift((int64_t)imm, magi 601 GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int imm, bool is_div) argument 1775 GenDivRemLongLit(RegLocation rl_dest, RegLocation rl_src, int64_t imm, bool is_div) argument 1955 int64_t imm = mir_graph_->ConstantValueWide(rl_src2); local [all...] |
H A D | target_x86.cc | 1975 int imm = mir->dalvikInsn.vB; local 2007 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 2013 NewLIR2(opcode, rs_tmp.GetReg(), imm); 2023 int imm = mir->dalvikInsn.vB; local 2044 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 2051 int imm = mir->dalvikInsn.vB; local 2069 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 2076 int imm = mir->dalvikInsn.vB; local 2097 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 2279 int op_low = 0, op_high = 0, imm local [all...] |
/art/compiler/utils/ |
H A D | assembler.cc | 127 void Assembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, argument 132 void Assembler::StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, argument
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H A D | assembler_test.h | 120 for (int64_t imm : imms) { 121 Imm* new_imm = CreateImmediate(imm); 134 size_t imm_index = base.find("{imm}"); 137 sreg << imm; local 156 for (int64_t imm : imms) { 157 Imm* new_imm = CreateImmediate(imm); 162 size_t imm_index = base.find("{imm}"); 165 sreg << imm; local
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H A D | assembler.h | 387 virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, 390 virtual void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, 392 virtual void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm,
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/art/compiler/utils/mips/ |
H A D | assembler_mips.h | 175 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister mscratch) OVERRIDE; 177 void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister mscratch) 272 void EmitI(int opcode, Register rs, Register rt, uint16_t imm); 275 void EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm);
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H A D | assembler_mips.cc | 54 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument 60 imm; 83 void MipsAssembler::EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm) { argument 88 imm; 630 void MipsAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, argument 634 LoadImmediate(scratch.AsCoreRegister(), imm); 638 void MipsAssembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, argument 642 LoadImmediate(scratch.AsCoreRegister(), imm);
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/art/compiler/utils/arm64/ |
H A D | assembler_arm64.h | 117 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE; 118 void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister scratch)
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H A D | assembler_arm64.cc | 153 void Arm64Assembler::StoreImmediateToFrame(FrameOffset offs, uint32_t imm, argument 157 LoadImmediate(scratch.AsCoreRegister(), imm); 162 void Arm64Assembler::StoreImmediateToThread64(ThreadOffset<8> offs, uint32_t imm, argument 166 LoadImmediate(scratch.AsCoreRegister(), imm);
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/art/compiler/optimizing/ |
H A D | code_generator_x86_64.cc | 311 Immediate imm(instruction->AsIntConstant()->GetValue()); 313 __ movl(location.AsX86_64().AsCpuRegister(), imm); 315 __ movl(Address(CpuRegister(RSP), location.GetStackIndex()), imm); 788 Immediate imm(instruction->AsIntConstant()->GetValue()); 789 __ addl(locations->InAt(0).AsX86_64().AsCpuRegister(), imm); 854 Immediate imm(instruction->AsIntConstant()->GetValue()); 855 __ subl(locations->InAt(0).AsX86_64().AsCpuRegister(), imm); 1375 Immediate imm(constant->AsIntConstant()->GetValue()); 1377 __ movl(destination.AsX86_64().AsCpuRegister(), imm); 1379 __ movl(Address(CpuRegister(RSP), destination.GetStackIndex()), imm); [all...] |
H A D | code_generator_x86.cc | 425 Immediate imm(instruction->AsIntConstant()->GetValue()); 427 __ movl(location.AsX86().AsCpuRegister(), imm); 429 __ movl(Address(ESP, location.GetStackIndex()), imm); local 537 Immediate imm(instruction->AsIntConstant()->GetValue()); 538 __ cmpl(lhs.AsX86().AsCpuRegister(), imm); 609 Immediate imm(instruction->AsIntConstant()->GetValue()); 610 __ cmpl(locations->InAt(0).AsX86().AsCpuRegister(), imm); 841 Immediate imm(instruction->AsIntConstant()->GetValue()); 842 __ addl(locations->InAt(0).AsX86().AsCpuRegister(), imm); 914 Immediate imm(instructio 1525 __ movl(Address(ESP, destination.GetStackIndex()), imm); local [all...] |
/art/compiler/utils/arm/ |
H A D | assembler_arm.cc | 129 // RRX is encoded as an ROR with imm 0. 528 void ArmAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, 532 LoadImmediate(scratch.AsCoreRegister(), imm); 536 void ArmAssembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, 540 LoadImmediate(scratch.AsCoreRegister(), imm);
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H A D | assembler_thumb2.cc | 640 uint32_t imm = so.GetImmediate(); local 643 if (imm > (1 << 9)) { // 9 bit immediate. 647 if (imm > (1 << 10)) { 651 // SUB rd, SP, #imm is always 32 bit. 771 uint32_t imm = so.GetImmediate(); local 773 uint32_t i = (imm >> 11) & 1; 774 uint32_t imm3 = (imm >> 8) & 0b111; 775 uint32_t imm8 = imm & 0xff; 786 uint32_t imm = ModifiedImmediate(so.encodingThumb()); local 787 if (imm 1575 ldrex(Register rt, Register rn, uint16_t imm, Condition cond) argument 1598 strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond) argument [all...] |
H A D | assembler_thumb2.h | 145 void ldrex(Register rd, Register rn, uint16_t imm, Condition cond = AL); 146 void strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond = AL);
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H A D | assembler_arm.h | 631 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE; 633 void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister scratch)
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/art/compiler/dex/portable/ |
H A D | mir_to_gbc.h | 134 int32_t imm);
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H A D | mir_to_gbc.cc | 455 RegLocation rl_src1, int32_t imm) { 457 ::llvm::Value* src2 = irb_->getInt32(imm); 798 int64_t imm = static_cast<int32_t>(vB); local 799 ::llvm::Constant* imm_value = irb_->getJLong(imm); 820 int64_t imm = static_cast<int64_t>(vB) << 48; local 821 ::llvm::Constant* imm_value = irb_->getJLong(imm); 454 ConvertArithOpLit(OpKind op, RegLocation rl_dest, RegLocation rl_src1, int32_t imm) argument
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/art/compiler/dex/quick/arm64/ |
H A D | target_arm64.cc | 412 uint64_t imm = DecodeLogicalImmediate(is_wide, operand); local 413 snprintf(tbuf, arraysize(tbuf), "%" PRId64 " (%#" PRIx64 ")", imm, imm);
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