Searched refs:shift (Results 1 - 17 of 17) sorted by relevance

/art/runtime/gc/accounting/
H A Dspace_bitmap-inl.h110 const size_t shift = CTZ(left_edge); local
111 mirror::Object* obj = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment);
113 left_edge ^= (static_cast<uword>(1)) << shift;
123 const size_t shift = CTZ(w); local
124 mirror::Object* obj = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment);
126 w ^= (static_cast<uword>(1)) << shift;
149 const size_t shift = CTZ(right_edge); local
150 mirror::Object* obj = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment);
152 right_edge ^= (static_cast<uword>(1)) << shift;
H A Dspace_bitmap.cc115 const size_t shift = CTZ(w); local
116 mirror::Object* obj = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment);
118 w ^= (static_cast<uword>(1)) << shift;
163 const size_t shift = CTZ(garbage); local
164 garbage ^= (static_cast<uword>(1)) << shift;
165 *pb++ = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment);
254 // Need uint for unsigned shift.
259 const size_t shift = CTZ(w); local
260 mirror::Object* obj = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment);
262 w ^= (static_cast<uword>(1)) << shift;
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/art/compiler/dex/quick/arm64/
H A Dutility_arm64.cc288 for (int shift = 0; shift < 64; shift += 16) {
289 uint16_t halfword = static_cast<uint16_t>(value >> shift);
422 int shift; local
425 shift = 0;
429 shift = 1;
435 res = NewLIR3(kA64Movn3rdM, r_dest.GetReg(), ~useful_bits, shift);
437 res = NewLIR3(kA64Movz3rdM, r_dest.GetReg(), useful_bits, shift);
503 int shift; local
516 NewLIR3(WIDE(kA64Movk3rdM), r_dest.GetReg(), halfword, shift); local
566 OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) argument
695 OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, int shift) argument
943 bool shift; local
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H A Dint_arm64.cc379 uint32_t shift; member in struct:art::MagicTable
431 32 + magic_table[lit].shift);
437 OpRegRegImm(kOpAsr, r_long_mul, r_long_mul, magic_table[lit].shift);
497 OpRegRegImm(kOpAsr, r_long_mul, r_long_mul, magic_table[lit].shift);
502 OpRegRegImm(kOpAsr, r_long_mul, r_long_mul, magic_table[lit].shift);
554 int shift = EncodeShift(kA64Lsr, nbits - k); local
558 OpRegRegRegShift(kOpAdd, t_reg, rl_src.reg, rl_src.reg, shift);
562 OpRegRegRegShift(kOpAdd, t_reg, rl_src.reg, t_reg, shift);
567 OpRegRegRegShift(kOpAdd, t_reg, rl_src.reg, rl_src.reg, shift);
569 OpRegRegRegShift(kOpSub, rl_result.reg, t_reg, rl_src.reg, shift);
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H A Dcodegen_arm64.h367 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
369 int shift);
/art/compiler/dex/quick/arm/
H A Dutility_arm.cc239 int shift) {
241 ((shift == 0) && r_dest_src1.Low8() && r_src2.Low8());
254 DCHECK_EQ(shift, 0);
260 else if ((shift == 0) && !r_dest_src1.Low8() && !r_src2.Low8())
262 else if ((shift == 0) && r_dest_src1.Low8())
264 else if (shift == 0)
273 DCHECK_EQ(shift, 0);
284 DCHECK_EQ(shift, 0);
291 DCHECK_EQ(shift, 0);
304 DCHECK_EQ(shift,
238 OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) argument
390 OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, int shift) argument
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H A Dint_arm.cc468 uint32_t shift; member in struct:art::MagicTable
521 EncodeShift(kArmAsr, magic_table[lit].shift));
527 EncodeShift(kArmAsr, magic_table[lit].shift));
563 op->shift = LowestSetBit(lit);
569 op->shift = LowestSetBit(lit - 1);
575 op->shift = LowestSetBit(lit + 1);
580 op->shift = 0;
589 ops[1].shift = 0;
594 uint32_t shift = LowestSetBit(lit1); local
595 if (GetEasyMultiplyOp(lit1 >> shift,
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H A Dcodegen_arm.h167 int shift);
168 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
208 uint32_t shift; member in struct:art::FINAL::__anon10
/art/compiler/utils/arm/
H A Dconstants_arm.h154 LSL = 0, // Logical shift left
155 LSR = 1, // Logical shift right
156 ASR = 2, // Arithmetic shift right
260 int Bits(int shift, int count) const { argument
261 return (InstructionBits() >> shift) & ((1 << count) - 1);
H A Dassembler_arm.h50 ShifterOperand(Register rm, Shift shift, uint32_t shift_imm = 0) : type_(kRegister), rm_(rm), argument
52 is_rotate_(false), is_shift_(true), shift_(shift), rotate_(0), immed_(shift_imm) {
55 // Data-processing operands - Logical shift/rotate by register
56 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), argument
58 is_rotate_(false), is_shift_(true), shift_(shift), rotate_(0), immed_(0) {
207 Address(Register rn, Register rm, Shift shift, uint32_t count, Mode am = Offset) : argument
209 am_(am), is_immed_offset_(false), shift_(shift) {
265 int32_t offset_; // Used as shift amount for register offset.
581 // Convenience shift instructions. Use mov instruction with shifter operand
582 // for variants setting the status flags or using a register shift coun
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H A Dassembler_arm.cc97 // Immediate shift.
102 // Register shift.
127 // Immediate shift.
196 uint32_t shift = shift_;
197 if (shift == RRX) {
199 shift = ROR;
201 encoding = am_ | static_cast<uint32_t>(rm_) | shift << 5 | offset_ << 7 | B25;
H A Dassembler_thumb2.cc1092 void Thumb2Assembler::EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, bool setcc) { argument
1094 if (IsHighRegister(rd) || IsHighRegister(rm) || shift == ROR || shift == RRX) {
1096 switch (shift) {
1103 LOG(FATAL) << "Unsupported thumb2 shift opcode";
1114 // 16 bit shift
1116 switch (shift) {
1121 LOG(FATAL) << "Unsupported thumb2 shift opcode";
1129 void Thumb2Assembler::EmitShift(Register rd, Register rn, Shift shift, Register rm, bool setcc) { argument
1130 CHECK_NE(shift, RR
1952 ToItMask(ItState s, uint8_t firstcond0, uint8_t shift) argument
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H A Dassembler_thumb2.h419 void EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, bool setcc = false);
420 void EmitShift(Register rd, Register rn, Shift shift, Register rm, bool setcc = false);
/art/compiler/dex/quick/x86/
H A Dint_x86.cc525 void X86Mir2Lir::CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long) { argument
526 // It does not make sense to calculate magic and shift for zero divisor.
531 * The magic number M and shift S can be calculated in the following way:
540 * So the shift p is the smallest p satisfying
549 * the shift number S.
593 shift = (is_long) ? p - 64 : p - 32;
653 int shift; local
654 CalculateMagicAndShift((int64_t)imm, magic, shift, false /* is_long */);
709 // Do we need the shift?
710 if (shift !
1847 int shift; local
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H A Dcodegen_x86.h587 * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector.
597 * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector.
607 * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector.
714 * @brief Calculate magic number and shift for a given divisor
717 * @param shift hold calculated shift
720 void CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long);
743 * Generate code to implement long shift operations.
744 * @param opcode The DEX opcode to specify the shift type.
747 * @param shift_amount How much to shift
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/art/disassembler/
H A Ddisassembler_arm.cc149 explicit Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {}
150 uint32_t shift; member in struct:art::arm::Rm
155 if (r.shift != 0) {
156 os << "-shift-" << r.shift; // TODO
668 // TODO: use canonical form if there is a shift (lsl, ...).
1629 // shift (immediate), add, subtract, move, and compare
1634 // Logical shift left - 00 000xx iii mmm ddd
1635 // Logical shift right - 00 001xx iii mmm ddd
1636 // Arithmetic shift righ
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/art/runtime/arch/mips/
H A Dquick_entrypoints_mips.S499 srl $t0, $t0, 4 # shift the frame size right 4
500 sll $t0, $t0, 4 # shift the frame size left 4 to align to 16 bytes
1124 * Long integer shift. This is different from the generic 32/64-bit
1125 * binary operations because vAA/vBB are 64-bit but vCC (the shift
1131 * $a2: shift count
1135 sll $v0, $a0, $a2 # rlo<- alo << (shift&31)
1136 not $v1, $a2 # rhi<- 31-shift (shift is 5b)
1138 srl $a0, $v1 # alo<- alo >> (32-(shift&31))
1139 sll $v1, $a1, $a2 # rhi<- ahi << (shift
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