Searched refs:src1 (Results 1 - 17 of 17) sorted by relevance

/art/runtime/arch/arm64/
H A Dmemcmp16_arm64.S28 #define src1 x0 define
53 eor tmp1, src1, src2
56 ands tmp1, src1, #7
62 ldr data1, [src1], #8
109 bic src1, src1, #7
113 ldr data1, [src1], #8
134 ldrh data1w, [src1], #2
/art/compiler/dex/quick/
H A Dmir_to_lir-inl.h89 inline LIR* Mir2Lir::NewLIR2(int opcode, int dest, int src1) { argument
94 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1);
109 inline LIR* Mir2Lir::NewLIR3(int opcode, int dest, int src1, int src2) { argument
114 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2);
119 inline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) { argument
124 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info);
129 inline LIR* Mir2Lir::NewLIR5(int opcode, int dest, int src1, int src2, int info1, argument
135 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info1, info2);
H A Dcodegen_util.cc934 bool Mir2Lir::EvaluateBranch(Instruction::Code opcode, int32_t src1, int32_t src2) { argument
937 case Instruction::IF_EQ: is_taken = (src1 == src2); break;
938 case Instruction::IF_NE: is_taken = (src1 != src2); break;
939 case Instruction::IF_LT: is_taken = (src1 < src2); break;
940 case Instruction::IF_GE: is_taken = (src1 >= src2); break;
941 case Instruction::IF_GT: is_taken = (src1 > src2); break;
942 case Instruction::IF_LE: is_taken = (src1 <= src2); break;
943 case Instruction::IF_EQZ: is_taken = (src1 == 0); break;
944 case Instruction::IF_NEZ: is_taken = (src1 != 0); break;
945 case Instruction::IF_LTZ: is_taken = (src1 <
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H A Dmir_to_lir.h187 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2].
680 LIR* NewLIR2(int opcode, int dest, int src1);
682 LIR* NewLIR3(int opcode, int dest, int src1, int src2);
683 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info);
684 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2);
696 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2);
1387 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0;
/art/compiler/dex/portable/
H A Dmir_to_gbc.cc314 ::llvm::Value* src1, ::llvm::Value* src2) {
316 DCHECK_EQ(src1->getType(), src2->getType());
318 case kCondEq: res = irb_->CreateICmpEQ(src1, src2); break;
319 case kCondNe: res = irb_->CreateICmpNE(src1, src2); break;
320 case kCondLt: res = irb_->CreateICmpSLT(src1, src2); break;
321 case kCondGe: res = irb_->CreateICmpSGE(src1, src2); break;
322 case kCondGt: res = irb_->CreateICmpSGT(src1, src2); break;
323 case kCondLe: res = irb_->CreateICmpSLE(src1, src2); break;
334 ::llvm::Value* src1 = GetLLVMValue(rl_src1.orig_sreg); local
336 ::llvm::Value* cond_value = ConvertCompare(cc, src1, src
313 ConvertCompare(ConditionCode cc, ::llvm::Value* src1, ::llvm::Value* src2) argument
349 ::llvm::Value* src1 = GetLLVMValue(rl_src1.orig_sreg); local
363 GenDivModOp(bool is_div, bool is_long, ::llvm::Value* src1, ::llvm::Value* src2) argument
386 GenArithOp(OpKind op, bool is_long, ::llvm::Value* src1, ::llvm::Value* src2) argument
410 ::llvm::Value* src1 = GetLLVMValue(rl_src1.orig_sreg); local
447 ::llvm::Value* src1 = GetLLVMValue(rl_src1.orig_sreg); local
456 ::llvm::Value* src1 = GetLLVMValue(rl_src1.orig_sreg); local
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H A Dmir_to_gbc.h116 ::llvm::Value* src1, ::llvm::Value* src2);
121 ::llvm::Value* GenDivModOp(bool is_div, bool is_long, ::llvm::Value* src1,
123 ::llvm::Value* GenArithOp(OpKind op, bool is_long, ::llvm::Value* src1,
/art/compiler/dex/
H A Dssa_transformation.cc435 * Perform dest U= src1 ^ ~src2
438 void MIRGraph::ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1, argument
440 if (dest->GetStorageSize() != src1->GetStorageSize() ||
442 dest->IsExpandable() != src1->IsExpandable() ||
449 dest->GetRawStorage()[idx] |= src1->GetRawStorageWord(idx) & ~(src2->GetRawStorageWord(idx));
H A Dmir_graph.h1082 void ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1,
H A Dglobal_value_numbering_test.cc128 #define DEF_PHI2(bb, reg, src1, src2) \
129 { bb, static_cast<Instruction::Code>(kMirOpPhi), 0, 0u, 2u, { src1, src2 }, 1, { reg } }
/art/compiler/dex/quick/mips/
H A Dint_mips.cc65 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { argument
116 branch = NewLIR2(br_op, src1.GetReg(), src2.GetReg());
120 NewLIR3(slt_op, t_reg.GetReg(), src2.GetReg(), src1.GetReg());
122 NewLIR3(slt_op, t_reg.GetReg(), src1.GetReg(), src2.GetReg());
H A Dcodegen_mips.h137 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
/art/compiler/dex/quick/arm/
H A Dcodegen_arm.h139 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
H A Dint_arm.cc28 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { argument
29 OpRegReg(kOpCmp, src1, src2);
1168 * tmp1 = src1.hi * src2.lo; // src1.hi is no longer needed
1169 * dest = src1.lo * src2.lo;
1170 * tmp1 += src1.lo * src2.hi;
/art/compiler/dex/quick/arm64/
H A Dcodegen_arm64.h205 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
H A Dint_arm64.cc29 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { argument
30 OpRegReg(kOpCmp, src1, src2);
/art/compiler/dex/quick/x86/
H A Dcodegen_x86.h264 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
H A Dint_x86.cc42 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0
43 NewLIR2(kX86Set8R, temp_reg.GetReg(), kX86CondL); // temp = (src1 >= src2) ? 0 : 1
96 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { argument
97 NewLIR2(src1.Is64Bit() ? kX86Cmp64RR : kX86Cmp32RR, src1.GetReg(), src2.GetReg());

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