/art/compiler/dex/quick/ |
H A D | mir_to_lir-inl.h | 44 inline LIR* Mir2Lir::RawLIR(DexOffset dalvik_offset, int opcode, int op0, argument 48 insn->opcode = opcode; 56 if ((opcode == kPseudoTargetLabel) || (opcode == kPseudoSafepointPC) || 57 (opcode == kPseudoExportedPC)) { 69 inline LIR* Mir2Lir::NewLIR0(int opcode) { argument 70 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & NO_OPERAND)) 71 << GetTargetInstName(opcode) << " " << opcod 79 NewLIR1(int opcode, int dest) argument 89 NewLIR2(int opcode, int dest, int src1) argument 99 NewLIR2NoDest(int opcode, int src, int info) argument 109 NewLIR3(int opcode, int dest, int src1, int src2) argument 119 NewLIR4(int opcode, int dest, int src1, int src2, int info) argument 129 NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2) argument 162 int opcode = lir->opcode; local [all...] |
H A D | mir_to_lir.cc | 325 switch (special.opcode) { 328 DCHECK_EQ(mir->dalvikInsn.opcode, Instruction::RETURN_VOID); 366 if (special.opcode != kInlineOpReturnArg) { 393 Instruction::Code opcode = mir->dalvikInsn.opcode; local 403 uint64_t attrs = MIRGraph::GetDataFlowAttributes(opcode); 437 switch (opcode) { 615 GenCmpFP(opcode, rl_dest, rl_src[0], rl_src[1]); 632 bool is_taken = EvaluateBranch(opcode, mir_graph_->ConstantValue(rl_src[0].orig_sreg), 646 GenCompareAndBranch(opcode, rl_sr 1166 int opcode = mir->dalvikInsn.opcode; local 1266 GenerateTargetLabel(int opcode) argument [all...] |
H A D | local_optimizations.cc | 156 if (this_lir->flags.is_nop || IsPseudoLirOp(this_lir->opcode)) { 160 uint64_t target_flags = GetTargetInstFlags(this_lir->opcode); 210 if (check_lir->flags.is_nop || IsPseudoLirOp(check_lir->opcode)) { 221 uint64_t check_flags = GetTargetInstFlags(check_lir->opcode); 333 if (IsPseudoLirOp(this_lir->opcode)) { 337 uint64_t target_flags = GetTargetInstFlags(this_lir->opcode); 412 if (stop_here || !IsPseudoLirOp(check_lir->opcode)) { 443 if (!IsPseudoLirOp(dep_lir->opcode) && 444 (GetTargetInstFlags(dep_lir->opcode) & IS_LOAD)) { 461 if (GetTargetInstFlags(cur_lir->opcode) [all...] |
H A D | dex_file_method_inliner.cc | 111 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); 112 if (Instruction::FormatOf(invoke->dalvikInsn.opcode) == Instruction::k3rc) { 115 DCHECK_EQ(Instruction::FormatOf(invoke->dalvikInsn.opcode), Instruction::k35c); 122 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); 123 return Instruction::FormatOf(invoke->dalvikInsn.opcode) == Instruction::k3rc || 433 if (kIntrinsicIsStatic[intrinsic.opcode] != (info->type == kStatic)) { 437 switch (intrinsic.opcode) { 505 LOG(FATAL) << "Unexpected intrinsic opcode: " << intrinsic.opcode; 543 switch (method.opcode) { 741 Instruction::Code opcode = Instruction::MOVE_FROM16; local 779 Instruction::Code opcode = static_cast<Instruction::Code>(Instruction::IGET + data.op_variant); local 831 Instruction::Code opcode = static_cast<Instruction::Code>(Instruction::IPUT + data.op_variant); local [all...] |
/art/disassembler/ |
H A D | disassembler_x86.cc | 60 // 64-bit opcode REX modifier. 202 std::ostringstream opcode; local 205 bool byte_operand = false; // true when the opcode is dealing with byte operands 210 bool reg_in_opcode = false; // low 3-bits of opcode encode register parameter 219 case rm8_r8: opcode << #opname; store = true; has_modrm = true; byte_operand = true; break; \ 220 case rm32_r32: opcode << #opname; store = true; has_modrm = true; break; \ 221 case r8_rm8: opcode << #opname; load = true; has_modrm = true; byte_operand = true; break; \ 222 case r32_rm32: opcode << #opname; load = true; has_modrm = true; break; \ 223 case ax8_i8: opcode << #opname; ax = true; immediate_bytes = 1; byte_operand = true; break; \ 224 case ax32_i32: opcode << #opnam [all...] |
H A D | disassembler_arm.cc | 248 std::string opcode; local 256 opcode = "bkpt"; 263 opcode = (((instruction >> 5) & 1) ? "blx" : "bx"); 270 opcode = kDataProcessingOperations[op]; 309 opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : "")); 339 opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a')); 346 opcode = (bl ? "bl" : "b"); 353 opcode = "???"; 356 opcode += kConditionCodeNames[cond]; 357 opcode 454 std::ostringstream opcode; local 1625 std::ostringstream opcode; local [all...] |
H A D | disassembler_mips.cc | 179 std::string opcode; local 185 opcode = StringPrintf("op=%d fn=%d", op, function); 189 opcode = gMipsInstructions[i].name; 210 case 0: opcode += ".s"; break; 211 case 1: opcode += ".d"; break; 212 case 4: opcode += ".w"; break; 213 case 5: opcode += ".l"; break; 214 case 6: opcode += ".ps"; break; 215 default: opcode += ".?"; break; 259 << StringPrintf(": %08x\t%-7s ", instruction, opcode [all...] |
/art/compiler/dex/quick/x86/ |
H A D | utility_x86.cc | 30 int opcode; local 35 opcode = kX86MovsdRR; 39 opcode = kX86MovssRR; 41 opcode = kX86MovdxrRR; 45 opcode = kX86MovdrxRR; 48 DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); 49 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); 121 X86OpCode opcode = kX86Bkpt; local 123 case kOpNeg: opcode = r_dest_src.Is64Bit() ? kX86Neg64R : kX86Neg32R; break; 124 case kOpNot: opcode 134 X86OpCode opcode = kX86Bkpt; local 197 X86OpCode opcode = kX86Nop; local 253 X86OpCode opcode = kX86Nop; local 307 X86OpCode opcode = kX86Nop; local 366 X86OpCode opcode = kX86Nop; local 396 X86OpCode opcode = kX86Nop; local 424 X86OpCode opcode = kX86Nop; local 499 X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI; local 525 X86OpCode opcode = kX86Bkpt; local 538 X86OpCode opcode = kX86Bkpt; local 550 X86OpCode opcode = kX86Bkpt; local 641 X86OpCode opcode = kX86Nop; local 788 X86OpCode opcode = kX86Nop; local 929 int opcode = mir->dalvikInsn.opcode; local 939 AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir) argument 955 AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir) argument 991 AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir) argument 1053 AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir) argument [all...] |
H A D | x86_lir.h | 385 // MR - Memory Register - opcode [base + disp], reg 387 // AR - Array Register - opcode [base + index * scale + disp], reg 389 // TR - Thread Register - opcode fs:[disp], reg - where fs: is equal to Thread::Current() 391 // RR - Register Register - opcode reg1, reg2 393 // RM - Register Memory - opcode reg, [base + disp] 395 // RA - Register Array - opcode reg, [base + index * scale + disp] 397 // RT - Register Thread - opcode reg, fs:[disp] - where fs: is equal to Thread::Current() 399 // RI - Register Immediate - opcode reg, #immediate 401 // MI - Memory Immediate - opcode [base + disp], #immediate 403 // AI - Array Immediate - opcode [bas 690 X86OpCode opcode; // e.g. kOpAddRI member in struct:art::X86EncodingMap 698 uint8_t opcode; // 1 byte opcode. member in struct:art::X86EncodingMap::__anon18 [all...] |
/art/compiler/dex/quick/mips/ |
H A D | utility_mips.cc | 26 int opcode; local 30 opcode = kMipsFmovd; 34 opcode = kMipsFmovs; 40 opcode = kMipsMtc1; 44 opcode = kMipsMfc1; 47 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_src.GetReg(), r_dest.GetReg()); 117 MipsOpCode opcode = kMipsNop; local 120 opcode = kMipsJalr; 128 return NewLIR2(opcode, rRA, r_dest_src.GetReg()); 136 MipsOpCode opcode local 162 MipsOpCode opcode = kMipsNop; local 204 MipsOpCode opcode = kMipsNop; local 286 MipsOpCode opcode = kMipsNop; local 360 MipsOpCode opcode = kMipsNop; local 412 MipsOpCode opcode = kMipsNop; local 468 MipsOpCode opcode = kMipsNop; local 579 MipsOpCode opcode = kMipsNop; local [all...] |
H A D | fp_mips.cc | 24 void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode, argument 33 switch (opcode) { 61 LOG(FATAL) << "Unexpected opcode: " << opcode; 70 void MipsMir2Lir::GenArithOpDouble(Instruction::Code opcode, argument 75 switch (opcode) { 103 LOG(FATAL) << "Unpexpected opcode: " << opcode; 116 void MipsMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, argument 120 switch (opcode) { 168 GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument [all...] |
H A D | assemble_mips.cc | 26 * opcode: MipsOpCode enum 27 * skeleton: pre-designated bit-pattern for this opcode 41 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \ 44 {k3, k3s, k3e}}, opcode, flags, name, fmt, size} 463 int opcode = lir->opcode; local 465 switch (opcode) { 471 case kMipsBeq: opcode = kMipsBne; break; 472 case kMipsBne: opcode = kMipsBeq; break; 473 case kMipsBeqz: opcode [all...] |
H A D | codegen_mips.h | 75 const char* GetTargetInstFmt(int opcode); 76 const char* GetTargetInstName(int opcode); 79 uint64_t GetTargetInstFlags(int opcode); 87 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 93 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 95 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 97 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 99 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 101 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 109 void GenArithOpLong(Instruction::Code opcode, RegLocatio [all...] |
/art/runtime/ |
H A D | dex_instruction.cc | 62 #define INSTRUCTION_SIZE(opcode, c, p, format, r, i, a, v) \ 63 ((opcode == NOP) ? -1 : \ 92 Code opcode = static_cast<Code>(insn & 0xFF); local 93 return FlagsOf(opcode) & Instruction::kContinue; 138 const char* opcode = kInstructionNames[Opcode()]; local 140 case k10x: os << opcode; break; local 141 case k12x: os << StringPrintf("%s v%d, v%d", opcode, VRegA_12x(), VRegB_12x()); break; 142 case k11n: os << StringPrintf("%s v%d, #%+d", opcode, VRegA_11n(), VRegB_11n()); break; 143 case k11x: os << StringPrintf("%s v%d", opcode, VRegA_11x()); break; 144 case k10t: os << StringPrintf("%s %+d", opcode, VRegA_10 304 os << opcode << " {"; local 321 os << opcode << " {"; local 334 os << opcode << " {"; local [all...] |
H A D | dex_instruction.h | 86 #define INSTRUCTION_ENUM(opcode, cname, p, f, r, i, a, v) cname = opcode, 140 kStore = 0x080000, // store opcode 141 kLoad = 0x100000, // load opcode 226 // Returns the name of this instruction's opcode. 231 // Returns the name of the given opcode. 232 static const char* Name(Code opcode) { argument 233 return kInstructionNames[opcode]; 396 // Returns the opcode field of the instruction. The given "inst_data" parameter must be the first 403 // Returns the opcode fiel 408 SetOpcode(Code opcode) argument 439 FormatOf(Code opcode) argument 444 FlagsOf(Code opcode) argument 449 VerifyFlagsOf(Code opcode) argument [all...] |
/art/compiler/dex/quick/arm/ |
H A D | utility_arm.cc | 224 ArmOpcode opcode = kThumbBkpt; local 227 opcode = kThumbBlxR; 230 opcode = kThumbBx; 233 LOG(FATAL) << "Bad opcode " << op; 235 return NewLIR1(opcode, r_dest_src.GetReg()); 242 ArmOpcode opcode = kThumbBkpt; local 245 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR; 248 opcode = (thumb_form) ? kThumbAndRR : kThumb2AndRRR; 251 opcode = (thumb_form) ? kThumbBicRR : kThumb2BicRRR; 255 opcode 392 ArmOpcode opcode = kThumbBkpt; local 467 ArmOpcode opcode = kThumbBkpt; local 604 ArmOpcode opcode = kThumbBkpt; local 696 ArmOpcode opcode = kThumbBkpt; local 762 ArmOpcode opcode = kThumbBkpt; local 824 LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base, int displacement, RegStorage r_src_dest, RegStorage r_work) argument 857 ArmOpcode opcode = kThumbBkpt; local 998 ArmOpcode opcode = kThumbBkpt; local 1142 int opcode; local [all...] |
H A D | codegen_arm.h | 75 const char* GetTargetInstFmt(int opcode); 76 const char* GetTargetInstName(int opcode); 79 uint64_t GetTargetInstFlags(int opcode); 87 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 89 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 95 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 97 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 99 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 101 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 103 void GenConversion(Instruction::Code opcode, RegLocatio [all...] |
/art/runtime/quick/ |
H A D | inline_method_analyser.h | 109 // The op_variant below is opcode-Instruction::IGET for IGETs and 110 // opcode-Instruction::IPUT for IPUTs. This is because the runtime 133 InlineMethodOpcode opcode; member in struct:art::InlineMethod 155 static constexpr bool IsInstructionIGet(Instruction::Code opcode) { argument 156 return Instruction::IGET <= opcode && opcode <= Instruction::IGET_SHORT; 159 static constexpr bool IsInstructionIPut(Instruction::Code opcode) { argument 160 return Instruction::IPUT <= opcode && opcode <= Instruction::IPUT_SHORT; 163 static constexpr uint16_t IGetVariant(Instruction::Code opcode) { argument 167 IPutVariant(Instruction::Code opcode) argument [all...] |
H A D | inline_method_analyser.cc | 97 Instruction::Code opcode = instruction->Opcode(); local 99 switch (opcode) { 102 method->opcode = kInlineOpNop; 155 result->opcode = kInlineOpReturnArg; 192 result->opcode = kInlineOpNonWideConst; 203 Instruction::Code opcode = instruction->Opcode(); local 204 DCHECK(IsInstructionIGet(opcode)); 208 if (!(return_opcode == Instruction::RETURN_WIDE && opcode == Instruction::IGET_WIDE) && 209 !(return_opcode == Instruction::RETURN_OBJECT && opcode == Instruction::IGET_OBJECT) && 210 !(return_opcode == Instruction::RETURN && opcode ! 266 Instruction::Code opcode = instruction->Opcode(); local [all...] |
/art/compiler/dex/quick/arm64/ |
H A D | utility_arm64.cc | 91 bool opcode_is_wide = IS_WIDE(lir->opcode); 92 ArmOpcode opcode = UNWIDE(lir->opcode); local 93 DCHECK(!IsPseudoLirOp(opcode)); 94 const ArmEncodingMap *encoder = &EncodingMap[opcode]; 101 uint64_t check_flags = GetTargetInstFlags(lir->opcode); 334 bool Arm64Mir2Lir::InexpensiveConstantInt(int32_t value, Instruction::Code opcode) { argument 335 switch (opcode) { 418 ArmOpcode opcode = LIKELY(low_bits == 0) ? kA64Mov2rr : kA64Mvn2rr; local 419 res = NewLIR2(opcode, r_des 469 ArmOpcode opcode = LIKELY(value == 0) ? WIDE(kA64Mov2rr) : WIDE(kA64Mvn2rr); local 551 ArmOpcode opcode = kA64Brk1d; local 569 ArmOpcode opcode = kA64Brk1d; local 637 ArmOpcode opcode = kA64Brk1d; local 697 ArmOpcode opcode = kA64Brk1d; local 765 ArmOpcode opcode = kA64Brk1d; local 813 ArmOpcode opcode = kA64Brk1d; local 941 ArmOpcode opcode = kA64Brk1d; local 1028 ArmOpcode opcode = kA64Brk1d; local 1116 ArmOpcode opcode = kA64Brk1d; local 1200 ArmOpcode opcode = kA64Brk1d; local 1297 ArmOpcode opcode = kA64Brk1d; local [all...] |
/art/compiler/dex/ |
H A D | mir_optimization.cc | 64 switch (d_insn->opcode) { 135 if ((mir->dalvikInsn.opcode == Instruction::MOVE_RESULT) || 136 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) || 137 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_WIDE)) { 141 if (MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) { 175 if (static_cast<int>(mir->dalvikInsn.opcode) == kMirOpPhi) { 187 switch (mir->dalvikInsn.opcode) { 215 static constexpr bool IsInstructionIfCcZ(Instruction::Code opcode) { argument 216 return Instruction::IF_EQZ <= opcode && opcode < 219 ConditionCodeForIfCcZ(Instruction::Code opcode) argument 342 Instruction::Code opcode = mir->dalvikInsn.opcode; local 633 Instruction::Code opcode = prev->last_mir_insn->dalvikInsn.opcode; local [all...] |
H A D | local_value_numbering_test.cc | 44 Instruction::Code opcode; member in struct:art::LocalValueNumberingTest::MIRDef 53 #define DEF_CONST(opcode, reg, value) \ 54 { opcode, value, 0u, 0, { }, 1, { reg } } 55 #define DEF_CONST_WIDE(opcode, reg, value) \ 56 { opcode, value, 0u, 0, { }, 2, { reg, reg + 1 } } 57 #define DEF_CONST_STRING(opcode, reg, index) \ 58 { opcode, index, 0u, 0, { }, 1, { reg } } 59 #define DEF_IGET(opcode, reg, obj, field_info) \ 60 { opcode, 0u, field_info, 1, { obj }, 1, { reg } } 61 #define DEF_IGET_WIDE(opcode, re [all...] |
H A D | global_value_numbering.cc | 111 (bb->last_mir_insn->dalvikInsn.opcode == Instruction::RETURN_VOID || 112 bb->last_mir_insn->dalvikInsn.opcode == Instruction::RETURN || 113 bb->last_mir_insn->dalvikInsn.opcode == Instruction::RETURN_OBJECT || 114 bb->last_mir_insn->dalvikInsn.opcode == Instruction::RETURN_WIDE) && 116 (static_cast<int>(bb->first_mir_insn->dalvikInsn.opcode) == kMirOpPhi && 118 (static_cast<int>(bb->first_mir_insn->next->dalvikInsn.opcode) == kMirOpPhi && 187 Instruction::Code last_opcode = pred_bb->last_mir_insn->dalvikInsn.opcode;
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H A D | post_opt_passes.cc | 64 Instruction::Code opcode = mir->dalvikInsn.opcode; local 66 if (opcode == static_cast<Instruction::Code> (kMirOpPhi)) {
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/art/runtime/arch/x86/ |
H A D | fault_handler_x86.cc | 101 uint8_t opcode = *pc++; local 111 switch (opcode) { 130 opcode = *pc++; 139 if (x86_64 && opcode >= 0x40 && opcode <= 0x4f) { 140 opcode = *pc++; 143 if (opcode == 0x0f) { 144 // Two byte opcode 146 opcode = *pc++; 152 switch (opcode) { [all...] |