Lines Matching refs:v4i32
422 // We promote all non-typed operations to v4i32.
424 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
490 setOperationAction(ISD::AND , MVT::v4i32, Legal);
491 setOperationAction(ISD::OR , MVT::v4i32, Legal);
492 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
493 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
494 setOperationAction(ISD::SELECT, MVT::v4i32,
496 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
497 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
500 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
507 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
521 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
523 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
529 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
562 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
2056 DAG.getSetCC(dl, MVT::v4i32,
2057 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2058 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2473 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2552 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2680 case MVT::v4i32:
3128 case MVT::v4i32:
3327 case MVT::v4i32:
3362 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3508 case MVT::v4i32:
4602 case MVT::v4i32:
4964 case MVT::v4i32:
5182 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5413 case MVT::v4i32:
5483 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
6472 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6637 // Now load from v4i32 into the QPX register; this will extend it to
6653 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6686 // Canonicalize all zero vectors to be v4i32.
6687 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6689 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6717 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6731 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6738 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
7254 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7255 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7336 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7549 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7585 if (Op.getValueType() == MVT::v4i32) {
7588 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7589 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7602 LHS, RHS, DAG, dl, MVT::v4i32);
7605 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7609 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
8991 VT = MVT::v4i32;
9035 VT = MVT::v4i32;
9942 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
9956 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
9969 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10010 PermTy = MVT::v4i32;
10011 LDTy = MVT::v4i32;
10911 VT = MVT::v4i32;
10947 VT = MVT::v4i32;
11001 VT = MVT::v4i32;
11036 VT = MVT::v4i32;
11089 return MVT::v4i32;
11179 VT != MVT::v4f32 && VT != MVT::v4i32)