| 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 |
|
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
(cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
|
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| daf6b948b98b886f5f0fba130e91e01c9ca7c2f2 |
|
26-Sep-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Fix PR17354: Generate nop after local calls for PIC code.
When generating code for shared libraries, even local calls may be
intercepted, so we need a nop after the call for the linker to fix up the
TOC. Test case adapted from the one provided in PR17354.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3789209b79ba8097cc489630c005898365134f65 |
|
17-Sep-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Add a FIXME.
Documenting a design choice to generate only medium model sequences for TLS
addresses at this time. Small and large code models could be supported if
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fabfb5d5880354983c89c6f475312dd359e5bb03 |
|
16-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Don't restrict lvsl generation to after type legalization
This is a re-commit of r190764, with an extra check to make sure that we're not
performing the transformation on illegal types (a small test case has been
added for this as well).
Original commit message:
The PPC backend uses a target-specific DAG combine to turn unaligned Altivec
loads into a permutation-based sequence when possible. Unfortunately, the
target-specific DAG combine is not always called on all loads of interest
(sometimes the routines in DAGCombine call CombineTo such that the new node and
users are not added to the worklist); allowing the combine to trigger early
(before type legalization) mitigates this problem. Because the autovectorizers
only create legal vector types, I don't expect a lot of cases where this
optimization is enabled by type legalization in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 19b59e66afa8d19c35444e0a739b467d368725d3 |
|
15-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Revert r190764: PPC: Don't restrict lvsl generation to after type legalization
This is causing test-suite failures.
Original commit message:
The PPC backend uses a target-specific DAG combine to turn unaligned Altivec
loads into a permutation-based sequence when possible. Unfortunately, the
target-specific DAG combine is not always called on all loads of interest
(sometimes the routines in DAGCombine call CombineTo such that the new node and
users are not added to the worklist); allowing the combine to trigger early
(before type legalization) mitigates this problem. Because the autovectorizers
only create legal vector types, I don't expect a lot of cases where this
optimization is enabled by type legalization in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 55532adc687a87574fd79822c876b10db95cd9ee |
|
15-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Don't restrict lvsl generation to after type legalization
The PPC backend uses a target-specific DAG combine to turn unaligned Altivec
loads into a permutation-based sequence when possible. Unfortunately, the
target-specific DAG combine is not always called on all loads of interest
(sometimes the routines in DAGCombine call CombineTo such that the new node and
users are not added to the worklist); allowing the combine to trigger early
(before type legalization) mitigates this problem. Because the autovectorizers
only create legal vector types, I don't expect a lot of cases where this
optimization is enabled by type legalization in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 98bae99266d8e527e7399c717a79c6dc9a073331 |
|
13-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add missing break statement in PPCISelLowering
As it turns out, not a problem in practice, but it should be there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a2c982129ed93f4bcb9738e0749a0b08e51a8b83 |
|
13-Sep-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Remove an unused variable, fixing -Werror build with latest Clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6671cd4db079eb993f9bd340e0c33d61f0f27d81 |
|
13-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC ABI for ByVal structs with vector members
When a structure is passed by value, and that structure contains a vector
member, according to the PPC ABI, the structure will receive enhanced alignment
(so that the vector within the structure will always be aligned).
This should resolve PR16641.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4a1535c0383254741bcddd3500081782aad11864 |
|
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Make the PPC fast-math sqrt expansion safe at 0
In fast-math mode sqrt(x) is calculated using the fast expansion of the
reciprocal of the reciprocal sqrt expansion. The reciprocal and reciprocal
sqrt expansions use the associated estimate instructions along with some Newton
iterations. Unfortunately, as a result, sqrt(0) was being calculated as NaN,
which is not correct. Now we explicitly return a result of zero if the input is
zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b7fbc5baad87eb5cc143193e66139824993883d3 |
|
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Enable MI scheduling (and CodeGen AA) by default for embedded PPC cores
For embedded PPC cores (especially the A2 core), using the MI scheduler with AA
is far superior to the other scheduling options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 11addd2a2f584571ffcfd51711972b27aef0133f |
|
31-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Call support for fast-isel.
This patch adds fast-isel support for calls (but not intrinsic calls
or varargs calls). It also removes a badly-formed assert. There are
some new tests just for calls, and also for folding loads into
arguments on calls to avoid extra extends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7248968fa529726b44d41bd25403d50c74db4bc4 |
|
30-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Add loads, stores, and related things to fast-isel.
This is the next big chunk of fast-isel code. The primary purpose is
to implement selection of loads and stores, but there is a lot of
drag-along to support this. The common code to analyze addresses for
both loads and stores is substantial. It's also necessary to add the
materialization code for global values.
Related to load-store processing is the code to fold loads into
integer extends, since otherwise we generate lots of redundant
instructions. We also need to add some overrides to some FastEmit
routines to ensure we don't assign GPR 0 to a virtual register when
this would change the meaning of an instruction.
I added handling selection of a few binary arithmetic instructions, to
enable committing some test cases I wrote a while back.
Finally, ap couple of miscellaneous changes:
* I cleaned up some poor style from a previous patch in
PPCISelLowering.cpp, pointed out by David Blaikie.
* I enlarged the Addr.Offset field to avoid sign problems with 32-bit
offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7c42ede04579373a2d3e124b4417d89430d541f3 |
|
26-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Dummy code to silence warning from 4189266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 953a78084b85ea88cd2b208153a72df70e27133f |
|
19-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC fcpsgn instruction
Modern PPC cores support a floating-point copysign instruction, and we can use
this to lower the FCOPYSIGN node (which is created from calls to the libm
copysign function). A couple of extra patterns are necessary because the
operand types of FCOPYSIGN need not agree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5a0910b34959fa8e0b5a49908f51a15bc3a48069 |
|
15-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Replace getValueType().getSimpleVT() with getSimpleValueType(). Also remove one weird cast from MVT->EVT just to call getSimpleVT().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 341c1a50adeadd848b2e73e9184d81331ee1cb92 |
|
14-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Actually fix PPC64 64-bit GPR inline asm constraint matching
This is a follow-up to r187693, correcting that code to request the correct
register class. The previous version, with the wrong register class, was not
really correcting the constraints, but rather was removing them. Coincidentally,
this fixed the failing test case in r187693, but obviously created other
problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 05a4d2642b415e3332651733015b656bc3c7b9bc |
|
08-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Map frin to round() not nearbyint() and rint()
Making use of the recently-added ISD::FROUND, which allows for custom lowering
of round(), the PPC backend will now map frin to round(). Previously, we had
been using frin to lower nearbyint() (and rint() via some custom lowering to
handle the extra fenv flags requirements), but only in fast-math mode because
frin does not tie-to-even. Several users had complained about this behavior,
and this new mapping of frin to round is certainly more appropriate (and does
not require fast-math mode).
In effect, this reverts r178362 (and part of r178337, replacing the nearbyint
mapping with the round mapping).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5cad12d12a823d258fc60e3975ffa142d0e190ef |
|
03-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC64 64-bit GPR inline asm constraint matching
Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the
64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with
explicit register names, on PPC64 when an i64 MVT has been requested, we need
to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent)
registers.
At some point, we'll probably want to arrange things so that the generic code
in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order
to match these inline asm register constraints. If we do that, this change can
be reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 646cd7933b16b78443b06ce9ba2362e6695cb526 |
|
30-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Skeletal FastISel support for 64-bit PowerPC ELF.
This is the first of many upcoming patches for PowerPC fast
instruction selection support. This patch implements the minimum
necessary for a functional (but extremely limited) FastISel pass. It
allows the table-generated portions of the selector to be created and
used, but in most cases selection will fall back to the DAG selector.
None of the block terminator instructions are implemented yet, and
most interesting instructions require some special handling.
Therefore there aren't any new test cases with this patch. There will
be quite a few tests coming with future patches.
This patch adds the make/CMake support for the new code (including
tablegen -gen-fast-isel) and creates the FastISel object for PPC64 ELF
only. It instantiates the necessary virtual functions
(TargetSelectInstruction, TargetMaterializeConstant,
TargetMaterializeAlloca, tryToFoldLoadIntoMI, and FastLowerArguments),
but of these, only TargetMaterializeConstant contains any useful
implementation. This is present since the table-generated code
requires the ability to materialize integer constants for some
instructions.
This patch has been tested by building and running the
projects/test-suite code with -O0. All tests passed with the
exception of a couple of long-running tests that time out using -O0
code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6ebf55d811bab50e7f42ee8cec60c125f6fe0cd2 |
|
25-Jul-2013 |
Roman Divacky <rdivacky@freebsd.org> |
PPC32 va_list is an actual structure so va_copy needs to copy the whole
structure not just a pointer. This implements that and thus fixes va_copy
on PPC32. Fixes #15286. Both bug and patch by Florian Zeitz!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0541722de4beb2e53058dbf4ed1ebf0d96ddd6cb |
|
18-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add base-pointer support to builtin setjmp/longjmp
First, this changes the base-pointer implementation to remove an unnecessary
complication (and one that is incompatible with how builtin SjLj is
implemented): instead of using r31 as the base pointer when it is not needed as
a frame pointer, now the base pointer will always be r30 when needed.
Second, we introduce another pseudo register, BP, which is used just like the FP
pseudo register to refer to the base register before we know for certain what
register it will be.
Third, we now save BP into the jmp_buf, and restore r30 from that slot in
longjmp. If the function that called setjmp did not use a base pointer, then
r30 will be overwritten by the setjmp-calling-function's restore code. FP
restoration (which is restored into r31) works the same way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186545 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
|
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e355d850d6b3f595ce58a7b612502b57ca7f3271 |
|
10-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add a better comment about the i64 FI fixup
In discussing this change with Bill Schmidt, it was decided that the original
comment about negative FIs was incorrect. We'll still exclude them for now, but
now with a more-accurate explanation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7c2d8f7b5ea1d0abaed1176f87ea2509e65e82be |
|
09-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Better fix for PR16556.
A more complete example of the bug in PR16556 was recently provided,
showing that the previous fix was not sufficient. The previous fix is
reverted herein.
The real problem is that ReplaceNodeResults() uses LowerFP_TO_INT as
custom lowering for FP_TO_SINT during type legalization, without
checking whether the input type is handled by that routine.
LowerFP_TO_INT requires the input to be f32 or f64, so we fail when
the input is ppcf128.
I'm leaving the test case from the initial fix (r185821) in place, and
adding the new test as another crash-only check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e54885af9b54bfc7436a928a48d3db1ef88a2a70 |
|
09-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fa55969acb64da32acf6305064c9f6e3c237b74e |
|
09-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Allocate RS spill slot for unaligned i64 load/store
This fixes another bug found by llvm-stress!
If we happen to be doing an i64 load or store into a stack slot that has less
than a 4-byte alignment, then the frame-index elimination may need to use an
indexed load or store instruction (because the offset may not be a multiple of
4, a requirement of the STD/LD instructions). The extra register needed to hold
the offset comes from the register scavenger, and it is possible that the
scavenger will need to use an emergency spill slot. As a result, we need to
make sure that a spill slot is allocated when doing an i64 load/store into a
less-than-4-byte-aligned stack slot.
Because test cases for things like this tend to be fairly fragile, I've
concatenated a few small bugpoint-reduced test cases together to form the
regression test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 947d447ee0ac927cc308e5e53062e0edb71e7d8e |
|
08-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Mark vector CC action for SETO and SETONE as Expand
Another bug found by llvm-stress! This fixes hitting
llvm_unreachable("Invalid integer vector compare condition");
at the end of getVCmpInst in PPCISelDAGToDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ad3b34d1bc4eaa92a95c56fe32fd18a6f36f62f4 |
|
08-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Mark vector FREM as Expand by default
Another bug found by llvm-stress! This fixes crashing with:
LLVM ERROR: Cannot select: v4f32 = frem ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 12ae7fd2da24e53c795c0cc17d06c91a0f09fb3d |
|
08-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Fix PR16556 (handle undef ppcf128 in LowerFP_TO_INT).
PPCTargetLowering::LowerFP_TO_INT() expects its source operand to be
either an f32 or f64, but this is not checked. A long double
(ppcf128) operand will normally be custom-lowered to a conversion to
f64 in this context. However, this isn't the case for an UNDEF node.
This patch recognizes a ppcf128 as a legal source operand for
FP_TO_INT only if it's an undef, in which case it creates an undef of
the target type.
At some point we might want to do a wholesale custom lowering of
ISD::UNDEF when the type is ppcf128, but it's not really clear that's
a great idea, and probably more work than it's worth for a situation
that only arises in the case of a programming error. At this point I
think simple is best.
The test case comes from PR16556, and is a crash-test only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df |
|
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
add 3, 4, symbol@tls
The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant. This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS. This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.
As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f349a6e9e6ee0b589c403e0c5785266da121d05c |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c93822901aef17aaf8bb1303f27b47025fd1d582 |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 62204220e1dc2dc21256adf765728ae257b33eac |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 965b20e39c7fd73846e9b6ed55ba90e032ae3b1b |
|
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Always use mfocrf if available
When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.
Current code makes that distinction in many, but not all places
where a single CR register value is retrieved. One missing
location is PPCRegisterInfo::lowerCRSpilling.
To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.
On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.
This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.
The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.
Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
|
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 92cfa61c50d01307d658753f8d47f4e8555a6fa9 |
|
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Rename some more VK_PPC_ enums
This renames more VK_PPC_ enums, to make them more closely reflect
the @modifier string they represent. This also prepares for adding
a bunch of new VK_PPC_ enums in upcoming patches.
For consistency, some MO_ flags related to VK_PPC_ enums are
likewise renamed.
No change in behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184547 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d3f7766f2363862b9c8586d2f78bc413223240d3 |
|
12-Jun-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Expose some calling convention functions in PPCISelLowering.h.
This is a preparatory patch for fast-isel support. The instruction
selector will need to access some functions in PPCGenCallingConv.inc,
which in turn requires several helper functions to be defined. These
are currently defined near the only use of PCCGenCallingConv.inc,
inside PPCISelLowering.cpp. This patch moves the declaration of the
functions into the associated header file to provide the needed
visibility.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 80ada583f3b40ffb201e54cd57c42f9518039c9e |
|
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2 |
|
30-May-2013 |
Andrew Trick <atrick@apple.com> |
Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 119da2eb20fffce88fa659d761ef5cea43f09ab6 |
|
27-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add a isConsecutiveLS utility function
isConsecutiveLS is a slightly more general form of
SelectionDAG::isConsecutiveLoad. Aside from also handling stores, it also does
not assume equality of the chain operands is necessary. In the case of the PPC
backend, this chain condition is checked in a more general way by the
surrounding code.
Mostly, this part of the refactoring in preparation for supporting optimized
unaligned stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182723 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1907cad7c822f07894a1189886fa7577f109045a |
|
26-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Prefer to duplicate PPC Altivec loads when expanding unaligned loads
When expanding unaligned Altivec loads, we use the decremented offset trick to
prevent page faults. Unfortunately, if we have a sequence of consecutive
unaligned loads, this leads to suboptimal code generation because the 'extra'
load from the first unaligned load can be combined with the base load from the
second (but only if the decremented offset trick is not used for the first).
Search up and down the chain, through loads and token factors, looking for
consecutive loads, and if one is found, don't use the offset reduction trick.
These duplicate loads are later combined to yield the desired sequence (in the
future, we might want a more-powerful chain search, but that will require some
changes to allow the combiner routines to access the AA object).
This should complete the initial implementation of the optimized unaligned
Altivec load expansion. There is some refactoring that should be done, but
that will happen when the unaligned store expansion is added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5a0e60425f4f942afb7e901b401a130da48a4d21 |
|
25-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Combine duplicate (offset) lvsl Altivec intrinsics
The lvsl permutation control instruction is a function only of the alignment of
the pointer operand (relative to the 16-byte natural alignment of Altivec
vectors). As a result, multiple lvsl intrinsics where the operands differ by a
multiple of 16 can be combined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 80d10ded8cd4f34b87d82b03d6f63328ea337b26 |
|
25-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Initial support for permutation-based unaligned Altivec loads
Altivec only directly supports aligned loads, but the loads have a strange
property: If given an unaligned address, they truncate the address to the next
lower aligned address, and load from there. This property, along with an extra
load and some special-purpose permutation-control instructions that generate
the appropriate permutations from the original unaligned address, allow
efficient lowering of aligned loads. This code uses the trick explained in the
Apple Velocity Engine optimization overview document to prevent the needed
extra load from possibly causing a page fault if the original address happens
to be aligned.
As noted in the FIXMEs, there are several additional optimizations that can be
performed to reduce the cost of these loads even more. These will be
implemented in future commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
|
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 347a5079e18278803bc05b197d325b8580e95610 |
|
16-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use true offset value in "memrix" machine operands
This is the second part of the change to always return "true"
offset values from getPreIndexedAddressParts, tackling the
case of "memrix" type operands.
This is about instructions like LD/STD that only have a 14-bit
field to encode immediate offsets, which are implicitly extended
by two zero bits by the machine, so that in effect we can access
16-bit offsets as long as they are a multiple of 4.
The PowerPC back end currently handles such instructions by
carrying the 14-bit value (as it will get encoded into the
actual machine instructions) in the machine operand fields
for such instructions. This means that those values are
in fact not the true offset, but rather the offset divided
by 4 (and then truncated to an unsigned 14-bit value).
Like in the case fixed in r182012, this makes common code
operations on such offset values not work as expected.
Furthermore, there doesn't really appear to be any strong
reason why we should encode machine operands this way.
This patch therefore changes the encoding of "memrix" type
machine operands to simply contain the "true" offset value
as a signed immediate value, while enforcing the rules that
it must fit in a 16-bit signed value and must also be a
multiple of 4.
This change must be made simultaneously in all places that
access machine operands of this type. However, just about
all those changes make the code simpler; in many cases we
can now just share the same code for memri and memrix
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f0ef882828bd9ba13cefce9869bde8be5e854956 |
|
16-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Report true displacement value from getPreIndexedAddressParts
DAGCombiner::CombineToPreIndexedLoadStore calls a target routine to
decompose a memory address into a base/offset pair. It expects the
offset (if constant) to be the true displacement value in order to
perform optional additional optimizations; in particular, to convert
other uses of the original pointer into uses of the new base pointer
after pre-increment.
The PowerPC implementation of getPreIndexedAddressParts, however,
simply calls SelectAddressRegImm, which returns a TargetConstant.
This value is appropriate for encoding into the instruction, but
it is not always usable as true displacement value:
- Its type is always MVT::i32, even on 64-bit, where addresses
ought to be i64 ... this causes the optimization to simply
always fail on 64-bit due to this line in DAGCombiner:
// FIXME: In some cases, we can be smarter about this.
if (Op1.getValueType() != Offset.getValueType()) {
- Its value is truncated to an unsigned 16-bit value if negative.
This causes the above opimization to generate wrong code.
This patch fixes both problems by simply returning the true
displacement value (in its original type). This doesn't
affect any other user of the displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b1fd3cd78f8acd21dbf514b75fef991827c343b6 |
|
15-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5bbdb190412a55436b808cfa59820b1e6cf08db0 |
|
14-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Implement the PowerPC system call (sc) instruction.
Instruction added at request of Roman Divacky. Tested via asm-parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 240b9b6078cdf8048945107b4ff7d517729dab96 |
|
13-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.
This fixes warning messages observed in the oggenc application test in
projects/test-suite. Special handling is needed for the 64-bit
PowerPC SVR4 ABI when a constant is initialized with a pointer to a
function in a shared library. Because a function address is
implemented as the address of a function descriptor, the use of copy
relocations can lead to problems with initialization. GNU ld
therefore replaces copy relocations with dynamic relocations to be
resolved by the dynamic linker. This means the constant cannot reside
in the read-only data section, but instead belongs in .data.rel.ro,
which is designed for constants containing dynamic relocations.
The implementation creates a class PPC64LinuxTargetObjectFile
inheriting from TargetLoweringObjectFileELF, which behaves like its
parent except to place constants of this sort into .data.rel.ro.
The test case is reduced from the oggenc application.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181723 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fd94f0ab358ea12cf2b17c9628207b3fd11d40b4 |
|
08-May-2013 |
Roman Divacky <rdivacky@freebsd.org> |
Remove unused isLegalAddressImmediate() method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a7f2ce85e5bd8d2826537f50ac510ef9fbe83792 |
|
08-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix handling of anonymous aggregate parameters for powerpc*-apple-darwin8.
This fixes bug 15821 similarly to the powerpc64-linux fix for bug 14779.
Patch by David Fang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181449 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fa799112ddd69cebc6bacb9e24feb1298c9cdfb5 |
|
23-Apr-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Change commentary for PowerPC Boolean vector contents.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ed5707baf9be36c0d06c278f589b6c55db8b96c0 |
|
23-Apr-2013 |
Owen Anderson <resistor@mac.com> |
DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider VSETCC without first checking the target's vector boolean contents.
This exposed an issue with PowerPC AltiVec where it appears it was setting the wrong vector boolean contents. The included change
fixes the PowerPC tests, and was OK'd by Hal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 59889f7f496f549965764820a0150c4068c02f5b |
|
08-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup and improve PPC fsel generation
First, we should not cheat: fsel-based lowering of select_cc is a
finite-math-only optimization (the ISA manual, section F.3 of v2.06, makes
this clear, as does a note in our own README).
This also adds fsel-based lowering of EQ and NE condition codes. As it turned
out, fsel generation was covered by a grand total of zero regression test
cases. I've added some test cases to cover the existing behavior (which is now
finite-math only), as well as the new EQ cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179000 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ff56d1a2011f239e114267c13302ea26db4f8046 |
|
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Enable early if conversion on PPC
On cores for which we know the misprediction penalty, and we have
the isel instruction, we can profitably perform early if conversion.
This enables us to replace some small branch sequences with selects
and avoid the potential stalls from mispredicting the branches.
Enabling this feature required implementing canInsertSelect and
insertSelect in PPCInstrInfo; isel code in PPCISelLowering was
refactored to use these functions as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| caeeb1865043d5410b5b0356694fb1228a18ec78 |
|
05-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Rename the current PPC BCL definition to BCLalways
BCL is normally a conditional branch-and-link instruction, but has
an unconditional form (which is used in the SjLj code, for example).
To make clear that this BCL instruction definition is specifically
the special unconditional form (which does not meaningfully take
a condition-register input), rename it to BCLalways.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7530a9f7d1e62b28e04d771158613c2954cc8d8c |
|
05-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Improve code generation for mixed-precision reciprocal sqrt
The DAGCombine logic that recognized a/sqrt(b) and transformed it into
a multiplication by the reciprocal sqrt did not handle cases where the
sqrt and the division were separated by an fpext or fptrunc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 63c32a7a9fd30f67bc623c818f434e742d43c085 |
|
03-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC reciprocal-estimate functionality
Incorporating review feedback from Bill Schmidt on r178617. No functionality
change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| cd7a1558edd0bdae770c57b82b32291e54e014b2 |
|
03-Apr-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.
For this we need to use a libcall. Previously LLVM didn't implement
libcall support for frem, so I've added it in the usual
straightforward manner. A test case from the bug report is included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178639 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 827307b95fa909e35a3ddef612f9f50ffcf0963a |
|
03-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use PPC reciprocal estimates with Newton iteration in fast-math mode
When unsafe FP math operations are enabled, we can use the fre[s] and
frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together
with some Newton iteration, in order to quickly generate floating-point
division and sqrt results. All of these instructions are separately optional,
and so each has its own feature flag (except for the Altivec instructions,
which are covered under the existing Altivec flag). Doing this is not only
faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these
computations to be pipelined with other computations in order to hide their
overall latency.
I've also added a couple of missing fnmsub patterns which turned out to be
missing (but are necessary for good code generation of the Newton iterations).
Altivec needs a similar fix, but that will probably be more complicated because
fneg is expanded for Altivec's v4f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| debf7d345aa297ebedf2d3b1db234feb44c71483 |
|
02-Apr-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR15630: Replace faulty stdcx. with stwcx.
When doing a partword atomic operation, a lwarx was being paired with
a stdcx. instead of a stwcx. when compiling for a 64-bit target. The
target has nothing to do with it in this case; we always need a stwcx.
Thanks to Kai Nacke for reporting the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178559 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2a401959b9d5d7824e4296683e2467e5aafe01b7 |
|
02-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix typo in PPCISelLowering
Thanks to Bill Schmidt for finding this in review of r178480.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a1646ceb9a5da080607e503c8bd36241aa465613 |
|
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix a bad assert in PPCTargetLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 46479197843ecb651adc9417c49bbd1b00acfcb6 |
|
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add more PPC floating-point conversion instructions
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1fce88313e4d46fdd432b68f7c54fde972c0b526 |
|
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC popcntw instruction
The popcntw instruction is available whenever the popcntd instruction is
available, and performs a separate popcnt on the lower and upper 32-bits.
Ignoring the high-order count, this can be used for the 32-bit input case
(saving on the explicit zero extension otherwise required to use popcntd).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f170cc9b2eb98efee40ee22cff6bcf401c209b00 |
|
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Treat PPCISD::STFIWX like the memory opcode that it is
PPCISD::STFIWX is really a memory opcode, and so it should come after
FIRST_TARGET_MEMORY_OPCODE, and we should use DAG.getMemIntrinsicNode to create
nodes using it.
No functionality change intended (although there could be optimization benefits
from preserving the MMO information).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8049ab15e4b638a07d6f230329945c2310eca27b |
|
31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC lfiwax instruction
This instruction is available on modern PPC64 CPUs, and is now used
to improve the SINT_TO_FP lowering (by eliminating the need for the
separate sign extension instruction and decreasing the amount of
needed stack space).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405 |
|
31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC(64) i32 -> float/double conversion
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode. Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.
This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0882fd6c4f90f1cbaa4bb6f6ceec289428cca734 |
|
29-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement FRINT lowering on PPC using frin
Like nearbyint, rint can be implemented on PPC using the frin instruction. The
complication comes from the fact that rint needs to set the FE_INEXACT flag
when the result does not equal the input value (and frin does not do that). As
a result, we use a custom inserter which, after the rounding, compares the
rounded value with the original, and if they differ, explicitly sets the XX bit
in the FPSCR register (which corresponds to FE_INEXACT).
Once LLVM has better modeling of the floating-point environment we should be
able to (often) eliminate this extra complexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 74a4533a4290b7c6f1fe04a30ca13ec25c529e0a |
|
29-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f5d5c434606161fb017a34cb656fa4aa5a3e076b |
|
29-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC FP rounding instructions fri[mnpz]
These instructions are available on the P5x (and later) and on the A2. They
implement the standard floating-point rounding operations (floor, trunc, etc.).
One caveat: frin (round to nearest) does not implement "ties to even", and so
is only enabled in fast-math mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2544f221c5f4047d7bdf10ec911c86a1d8be4a29 |
|
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Only enable 64-bit bswap DAG combines for PPC64
Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were
added for bswap with load/store. This is because these combines are really only
valid in 64-bit mode, regardless of the CPU (and this was not being checked).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178286 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b52980be0788a907c98fc08de090ad61aef86716 |
|
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix bad indentation in r178276
Thanks to Bill Schmidt for pointing this out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| efdd4673d6e78f3d406c5d1f44316aef8a5a9a48 |
|
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC64 ldbrx/stdbrx instructions
These are 64-bit load/store with byte-swap, and available on the P7 and the A2.
Like the similar instructions for 16- and 32-bit words, these are matched in the
target DAG-combine phase against load/store-bswap pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c53ab4d77f4b3d2905cf9ad625c28ff6b1c04aff |
|
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC64 popcntd instruction
PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and
tell TTI about it so that popcount-loop recognition will know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e915047fed99221afb8c540d8a7e81038a6483f1 |
|
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix typo (common to both X86 and PPC)
Thanks to Bill Schmidt for pointing this out during code review!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7d35d3f432cb59d3d1c0884af3023de9b5cb10b1 |
|
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Simplify FADD in round-to-zero mode.
As part of the the sequence generated to implement long double -> int
conversions, we need to perform an FADD in round-to-zero mode. This is
problematical since the FPSCR is not at all modeled at the SelectionDAG
level, and thus there is a risk of getting floating point instructions
generated out of sequence with the instructions to modify FPSCR.
The current code handles this by somewhat "special" patterns that in part
have dummy operands, and/or duplicate existing instructions, making them
awkward to handle in the asm parser.
This commit changes this by leaving the "FADD in round-to-zero mode"
as an atomic operation on the SelectionDAG level, and only split it up into
real instructions at the MI level (via custom inserter). Since at *this*
level the FPSCR *is* modeled (via the "RM" hard register), much of the
"special" stuff can just go away, and the resulting patterns can be used by
the asm parser.
No significant change in generated code expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a01c7dbaabae7cf569410bedd71361b75f65875f |
|
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Use CCBITRC operand for ISEL patterns.
This commit changes the ISEL patterns to use a CCBITRC operand
instead of a "pred" operand. This matches the actual instruction
text more directly, and simplifies use of ISEL with the asm parser.
In addition, this change allows some simplification of handling
the "pred" operand, as this is now only used by BCC.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 86765fbe170198e7bb40fd8499d1354f4c786f60 |
|
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Remove ABI-duplicated call instruction patterns.
We currently have a duplicated set of call instruction patterns depending
on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the
different ABIs will result in different instruction sequences, the actual
instructions themselves ought to be independent of the ABI. And in fact it
turns out that the only nontrivial difference between the two sets of
patterns is that in the PPC64 Linux ABI, the instruction used for indirect
calls is marked to take X11 as extra input register (which is indeed used
only with that ABI to hold an incoming environment pointer for nested
functions). However, this does not need to be hard-coded at the .td
pattern level; instead, the C++ code expanding calls can simply add that
use, just like it adds uses for argument registers anyway.
No change in generated code expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 881a7154b9f9b85f6a8515e282cacdfc9df156cf |
|
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix swapped BasePtr and Offset in pre-inc memory addresses.
PPCTargetLowering::getPreIndexedAddressParts currently provides
the base part of a memory address in the offset result, and the
offset part in the base result. That swap is then undone again
when an MI instruction is generated (in PPCDAGToDAGISel::Select
for loads, and using .md Pat patterns for stores).
This patch reverts this double swap, to make common code and
back-end be in sync as to which part of the address is base
and which is offset.
To avoid performance regressions in certain cases, target code
now checks whether the choice of base register would be rejected
for pre-inc accesses by common code, and attempts to swap base
and offset again in such cases. (Overall, this means that now
pre-ice accesses are generated *more* frequently than before.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7697370adff8983e2a3de493362f0d8c9f9b0e17 |
|
22-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class
As Jakob pointed out in his review of r177423, having a shared ZERO
register between the 32- and 64-bit register classes causes this
odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended,
this adds a ZERO8 register which differentiates the 32- and 64-bit
zeros.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7ee74a663a3b4d4ee6b55d23362f347ed1d390c2 |
|
21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement builtin_{setjmp/longjmp} on PPC
This implements SJLJ lowering on PPC, making the Clang functions
__builtin_{setjmp/longjmp} functional on PPC platforms. The implementation
strategy is similar to that on X86, with the exception that a branch-and-link
variant is used to get the right jump address. Credit goes to Bill Schmidt for
suggesting the use of the unconditional bcl form (instead of the regular bl
instruction) to limit return-address-cache pollution.
Benchmarking the speed at -O3 of:
static jmp_buf env_sigill;
void foo() {
__builtin_longjmp(env_sigill,1);
}
main() {
...
for (int i = 0; i < c; ++i) {
if (__builtin_setjmp(env_sigill)) {
goto done;
} else {
foo();
}
done:;
}
...
}
vs. the same code using the libc setjmp/longjmp functions on a P7 shows that
this builtin implementation is ~4x faster with Altivec enabled and ~7.25x
faster with Altivec disabled. This comparison is somewhat unfair because the
libc version must also save/restore the VSX registers which we don't yet
support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6 |
|
21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Correct PPC FRAMEADDR lowering using a pseudo-register
The old code used to lower FRAMEADDR tried to replicate the logic in the real
frame-lowering code that determines whether or not the frame pointer (r31) will
be used. When it seemed as through the frame pointer would not be used, the
stack pointer (r1) was used instead. Unfortunately, because the stack size is
not yet known, this does not work. Instead, this change introduces new
always-reserved pseudo-registers (FP and FP8) that are replaced during prologue
insertion with the real frame-pointer register (either r1 or r31).
It is important that this intrinsic always return a valid frame address because
it is used by Clang to store the frame address as part of code generation for
__builtin_setjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a548afc98fd4c61a8dfdd550ba57c37f2cfe3ed9 |
|
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 08a215c2869a89b977754334943681a56f5fc460 |
|
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC unaligned 64-bit loads and stores
PPC64 supports unaligned loads and stores of 64-bit values, but
in order to use the r+i forms, the offset must be a multiple of 4.
Unfortunately, this cannot always be determined by examining the
immediate itself because it might be available only via a TOC entry.
In order to get around this issue, we additionally predicate the
selection of the r+i form on the alignment of the load or store
(forcing it to be at least 4 in order to select the r+i form).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2d37f7b979a24930c444f9783173a90a6e548118 |
|
15-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Enable unaligned memory access on PPC for scalar types
Unaligned access is supported on PPC for non-vector types, and is generally
more efficient than manually expanding the loads and stores.
A few of the existing test cases were using expanded unaligned loads and stores
to test other features (like load/store with update), and for these test cases,
unaligned access remains disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3853f74aba301ef08b699bac2fa8e53230714a58 |
|
07-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
ArrayRefize some code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176648 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 700ed80d3da5e98e05ceb90e9bfb66058581a6db |
|
21-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.
There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.
The refactoring was OK'd by Anton Korobeynikov on llvmdev.
Note: this touches the target interfaces, so out-of-tree targets may
be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3450f800aa65c91f0496816ba6061a422a74c1fe |
|
20-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| abc402886e407e21d845cccc15723cffd6e2dc20 |
|
20-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Additional fixes for bug 15155.
This handles the cases where the 6-bit splat element is odd, converting
to a three-instruction sequence to add or subtract two splats. With this
fix, the XFAIL in test/CodeGen/PowerPC/vec_constants.ll is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 49deebb5ebcde502fa7908362a5c000e7adbb359 |
|
20-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix bug 14779 for passing anonymous aggregates [patch by Kai Nacke].
The PPC backend doesn't handle these correctly. This patch uses logic
similar to that in the X86 and ARM backends to track these arguments
properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b34c79e4bbe5accbb54d0291e8bef5d2bfef32e4 |
|
20-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR15155: lost vadd/vsplat optimization.
During lowering of a BUILD_VECTOR, we look for opportunities to use a
vector splat. When the splatted value fits in 5 signed bits, a single
splat does the job. When it doesn't fit in 5 bits but does fit in 6,
and is an even value, we can splat on half the value and add the result
to itself.
This last optimization hasn't been working recently because of improved
constant folding. To circumvent this, create a pseudo VADD_SPLAT that
can be expanded during instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 212af6af024ca358ed109c7b1c3a6b1fd30fd71b |
|
06-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
PPC calling convention cleanup.
Most of PPCCallingConv.td is used only by the 32-bit SVR4 ABI. Rename
things to clarify this. Also delete some code that's been commented out
for a long time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6ab5061a2c01b68c6e47c55d4cfe29b3e3b29963 |
|
05-Feb-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move MRI liveouts to PowerPC return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0d3731478e6242cceae7c006a071b8b17f7fd298 |
|
04-Feb-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Disable a couple more vector splat optimizations on PPC.
I didn't see those because the test case used "not grep". FileCheck the test and
XFAIL it, preserving the old optimization, so this can be fixed eventually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4969310052f45b1e2e5d21735e38641a20be0e21 |
|
04-Feb-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
SelectionDAG: Teach FoldConstantArithmetic how to deal with vectors.
This required disabling a PowerPC optimization that did the following:
input:
x = BUILD_VECTOR <i32 16, i32 16, i32 16, i32 16>
lowered to:
tmp = BUILD_VECTOR <i32 8, i32 8, i32 8, i32 8>
x = ADD tmp, tmp
The add now gets folded immediately and we're back at the BUILD_VECTOR we
started from. I don't see a way to fix this currently so I left it disabled
for now.
Fix some trivially foldable X86 tests too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
|
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 831737d329a727f53a1fb0572f7b7a8127208881 |
|
30-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the Function::getFnAttributes method in favor of using the AttributeSet
directly.
This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| cd9ea5198660a80c9c28c6471b0983bb450ca8cb |
|
25-Dec-2012 |
Hal Finkel <hfinkel@anl.gov> |
Expand PPC64 atomic load and store
Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 91223a41ef0f5b469b1230919cba9012beb6f321 |
|
19-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
PowerPC: Expand VSELECT nodes.
There's probably a better expansion for those nodes than the default for
altivec, but this is better than crashing. VSELECTs occur in loop vectorizer
output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170551 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 034b94b17006f51722886b0f2283fb6fb19aca1f |
|
19-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b453e16855f347e300f1dc0cd0dfbdd65c27b0d2 |
|
14-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x@got@tprel(2)
add 9,9,x@tls
New sequence:
addis 9,2,x@got@tprel@ha
ld 9,x@got@tprel@l(9)
add 9,9,x@tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1e18b861920ad2fd1a63e006cac61a4e274e5fdf |
|
13-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This is another cleanup patch for 64-bit PowerPC TLS processing. I had
some hackery in place that hid my poor use of TblGen, which I've now sorted
out and cleaned up. No change in observable behavior, so no new test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| dfebc4cc4c267f797e823b781d73586cc6fc49c5 |
|
13-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This is just a clean-up patch that simplifies the initial-exec TLS logic by
avoiding use of machine operand flags. No change in observable behavior, so
no new test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 349c2787cf9e174c8aa955bf8e3b09a405b2aece |
|
12-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements local-dynamic TLS model support for the 64-bit
PowerPC target. This is the last of the four models, so we now have
full TLS support.
This is mostly a straightforward extension of the general dynamic model.
I had to use an additional Chain operand to tie ADDIS_DTPREL_HA to the
register copy following ADDI_TLSLD_L; otherwise everything above the
ADDIS_DTPREL_HA appeared dead and was removed.
As before, there are new test cases to test the assembly generation, and
the relocations output during integrated assembly. The expected code
gen sequence can be read in test/CodeGen/PowerPC/tls-ld.ll.
There are a couple of things I think can be done more efficiently in the
overall TLS code, so there will likely be a clean-up patch forthcoming;
but for now I want to be sure the functionality is in place.
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 946a3a9f22c967d5432eaab5fa464b91343477cd |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?
This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7d34267df63e23be1957f738de783c145febb7af |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 57ac1f458a754f30cf500410b438fb260f9b8fe5 |
|
11-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d7802bf0ddcac16ee910105922492aee86a53e1b |
|
04-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch introduces initial-exec model support for thread-local storage
on 64-bit PowerPC ELF.
The patch includes code to handle external assembly and MC output with the
integrated assembler. It intentionally does not support the "old" JIT.
For the initial-exec TLS model, the ABI requires the following to calculate
the address of external thread-local variable x:
Code sequence Relocation Symbol
ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x
add 9,9,x@tls R_PPC64_TLS x
The register 9 is arbitrary here. The linker will replace x@got@tprel
with the offset relative to the thread pointer to the generated GOT
entry for symbol x. It will replace x@tls with the thread-pointer
register (13).
The two test cases verify correct assembly output and relocation output
as just described.
PowerPC-specific selection node variants are added for the two
instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted
when an initial-exec global variable is encountered by
PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to
machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo
that uses the same LDrs support added for medium code model's LDtocL,
with a different relocation type.
The rest of the processing is straightforward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 34a9d4b3b9b7858b729a1af67afa721c048fe5e7 |
|
27-Nov-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e95ed2b7afbe37f1831cb6d8d46d09ccb5cd6b7f |
|
15-Nov-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Lowering floor intrinsic for Altivec
This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and
llvm.nearbyint to Altivec instruction when using 4 single-precision
float vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 44e394cf618e67b74b0ca566c0acefbc3ca16a58 |
|
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Make a bunch of floating point operations on vectors Expand so that instruction selection won't fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 490104720db9e1e0eb9cc27e88e2d7288ac27ff0 |
|
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1ab489a42d013151b21655a4c011dc15d6d75eab |
|
14-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Set FFLOOR of vectors to expand to keep intruction selection from failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 86aef0a4f093700420c76f313e5668c39db110aa |
|
05-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
On PowerPC64, integer return values (as well as arguments) are supposed
to be extended to a full register. This is modeled in the IR by marking
the return value (or argument) with a signext or zeroext attribute.
However, while these attributes are respected for function arguments,
they are currently ignored for function return values by the PowerPC
back-end. This patch updates PPCCallingConv.td to ask for the promotion
to i64, and fixes LowerReturn and LowerCallResult to implement it.
The new test case verifies that both arguments and return values are
properly extended when passing them; and also that the optimizers
understand incoming argument and return values are in fact guaranteed
by the ABI to be extended.
The patch caused a spurious breakage in CodeGen/PowerPC/coalesce-ext.ll,
since the test case used a "ret" instruction to create a use of an i32
value at the end of the function (to set up data flow as required for
what the test is intended to test). Since there's now an implicit
promotion to i64, that data flow no longer works as expected. To fix
this, this patch now adds an extra "add" to ensure we have an appropriate
use of the i32 value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 827b7a070d349737f1d6ff63115e0cbb0c031f9c |
|
05-Nov-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for the PowerPC-specific inline asm Z constraint and y modifier.
The Z constraint specifies an r+r memory address, and the y modifier expands
to the "r, r" in the asm string. For this initial implementation, the base
register is forced to r0 (which has the special meaning of 0 for r+r addressing
on PowerPC) and the full address is taken in the second register. In the
future, this should be improved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| cfe09ed28d8a65b671e8b7a716a933e98e810e32 |
|
05-Nov-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
[PATCH] PowerPC: Expand load extend vector operations
This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for
vector types when altivec is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167386 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ece6c6bb6329748b92403c06ac87f45c43485911 |
|
01-Nov-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert the series of commits starting with r166578 which introduced the
getIntPtrType support for multiple address spaces via a pointer type,
and also introduced a crasher bug in the constant folder reported in
PR14233.
These commits also contained several problems that should really be
addressed before they are re-committed. I have avoided reverting various
cleanups to the DataLayout APIs that are reasonable to have moving
forward in order to reduce the amount of churn, and minimize the number
of commits that were reverted. I've also manually updated merge
conflicts and manually arranged for the getIntPtrType function to stay
in DataLayout and to be defined in a plausible way after this revert.
Thanks to Duncan for working through this exact strategy with me, and
Nick Lewycky for tracking down the really annoying crasher this
triggered. (Test case to follow in its own commit.)
After discussing with Duncan extensively, and based on a note from
Micah, I'm going to continue to back out some more of the more
problematic patches in this series in order to ensure we go into the
LLVM 3.2 branch with a reasonable story here. I'll send a note to
llvmdev explaining what's going on and why.
Summary of reverted revisions:
r166634: Fix a compiler warning with an unused variable.
r166607: Add some cleanup to the DataLayout changes requested by
Chandler.
r166596: Revert "Back out r166591, not sure why this made it through
since I cancelled the command. Bleh, sorry about this!
r166591: Delete a directory that wasn't supposed to be checked in yet.
r166578: Add in support for getIntPtrType to get the pointer type based
on the address space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 42d43351b274603ed0ac28128498a35b8987ce15 |
|
31-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch addresses an ABI compatibility issue with empty aggregate
parameters. Examples of these are:
struct { } a;
union { } b[256];
int a[0];
An empty aggregate has an address, although dereferencing that address is
pointless. When passed as a parameter, an empty aggregate does not consume
a protocol register, nor does it consume a doubleword in the parameter save
area. Passing an empty aggregate by reference passes an address just as
for any other aggregate. Returning an empty aggregate uses GPR3 as a hidden
address of the return value location, just as for any other aggregate.
The patch modifies PPCTargetLowering::LowerFormalArguments_64SVR4 and
PPCTargetLowering::LowerCall_64SVR4 to properly skip empty aggregate
parameters passed by value. The handling of return values and by-reference
parameters was already correct.
Built on powerpc64-unknown-linux-gnu and tested with no new regressions.
A test case is included to test proper handling of empty aggregate
parameters on both sides of the function call protocol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c83b5dc625bd85276a23c36c1fbad193203d2bc7 |
|
30-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Expand FSRQT for vector types
This patch expands FSQRT for floating point vector types when altivec is
used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5f41fd685b6e82c3194be782566bbc438d697cc9 |
|
30-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: More support for Altivec compare operations
This patch adds more support for vector type comparisons using altivec.
It adds correct support for v16i8, v8i16, v4i32, and v4f32 vector
types for comparison operators ==, !=, >, >=, <, and <=.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e6c56433de56fb89f1d476332134b6b2e22cfa28 |
|
29-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch solves a problem with passing varargs parameters under the PPC64
ELF ABI.
A varargs parameter consisting of a single-precision floating-point value,
or of a single-element aggregate containing a single-precision floating-point
value, must be passed in the low-order (rightmost) four bytes of the
doubleword stack slot reserved for that parameter. If there are GPR protocol
registers remaining, the parameter must also be mirrored in the low-order
four bytes of the reserved GPR.
Prior to this patch, such parameters were being passed in the high-order
four bytes of the stack slot and the mirrored GPR.
The patch adds a new test case to verify the correct code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 78dab643e0d49cc76ca20409d733c23bc17171dd |
|
29-Oct-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Allow i32/i64 for 'f' constraint on PowerPC.
This fixes PR12757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 37900c5dcb254ef50c17c57a302c30626536917c |
|
25-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch addresses a PPC64 ELF issue with passing parameters consisting of
structs having size 3, 5, 6, or 7. Such a struct must be passed and received
as right-justified within its register or memory slot. The problem is only
present for structs that are passed in registers.
Previously, as part of a patch handling all structs of size less than 8, I
added logic to rotate the incoming register so that the struct was left-
justified prior to storing the whole register. This was incorrect because
the address of the parameter had already been adjusted earlier to point to
the right-adjusted value in the storage slot. Essentially I had accidentally
accounted for the right-adjustment twice.
In this patch, I removed the incorrect logic and reorganized the code to make
the flow clearer.
The removal of the rotates changes the expected code generation, so test case
structsinregs.ll has been modified to reflect this. I also added a new test
case, jaggedstructs.ll, to demonstrate that structs of these sizes can now
be properly received and passed.
I've built and tested the code on powerpc64-unknown-linux-gnu with no new
regressions. I also ran the GCC compatibility test suite and verified that
earlier problems with these structs are now resolved, with no new regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| aa76e9e2cf50af190de90bc778b7f7e42ef9ceff |
|
24-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Add in support for getIntPtrType to get the pointer type based on the address space.
This checkin also adds in some tests that utilize these paths and updates some of the
clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 726c23705c056e4d86f0b3d833803f1d43e6eee4 |
|
23-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This is another TLC patch for separating code for the Darwin and ELF ABIs
for the PowerPC target, and factoring the results. This will ease future
maintenance of both subtargets.
PPCTargetLowering::LowerCall_Darwin_Or_64SVR4() has grown a lot of special-case
code for the different ABIs, making maintenance difficult. This is getting
worse as we repair errors in the 64-bit ELF ABI implementation, while avoiding
changes to the Darwin ABI logic. This patch splits the routine into
LowerCall_Darwin() and LowerCall_64SVR4(), allowing both versions to be
significantly simplified. I've factored out chunks of similar code where it
made sense to do so. I also performed similar factoring on
LowerFormalArguments_Darwin() and LowerFormalArguments_64SVR4().
There are no functional changes in this patch, and therefore no new test
cases have been developed.
Built and tested on powerpc64-unknown-linux-gnu with no new regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6c28a7eec8d1794fb5476cd9fe14affb479ed1d9 |
|
18-Oct-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
This patch fixes failures in the SingleSource/Regression/C/uint64_to_float
test case on PowerPC caused by rounding errors when converting from a 64-bit
integer to a single-precision floating point. The reason for this are
double-rounding effects, since on PowerPC we have to convert to an
intermediate double-precision value first, which gets rounded to the
final single-precision result.
The patch fixes the problem by preparing the 64-bit integer so that the
first conversion step to double-precision will always be exact, and the
final rounding step will result in the correctly-rounded single-precision
result. The generated code sequence is equivalent to what GCC would generate.
When -enable-unsafe-fp-math is in effect, that extra effort is omitted
and we accept possible rounding errors (just like GCC does as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7a6cb15a929e76955471ef2a7b6db721198320a0 |
|
16-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch addresses PR13949.
For the PowerPC 64-bit ELF Linux ABI, aggregates of size less than 8
bytes are to be passed in the low-order bits ("right-adjusted") of the
doubleword register or memory slot assigned to them. A previous patch
addressed this for aggregates passed in registers. However, small
aggregates passed in the overflow portion of the parameter save area are
still being passed left-adjusted.
The fix is made in PPCTargetLowering::LowerCall_Darwin_Or_64SVR4 on the
caller side, and in PPCTargetLowering::LowerFormalArguments_64SVR4 on
the callee side. The main fix on the callee side simply extends
existing logic for 1- and 2-byte objects to 1- through 7-byte objects,
and correcting a constant left over from 32-bit code. There is also a
fix to a bogus calculation of the offset to the following argument in
the parameter save area.
On the caller side, again a constant left over from 32-bit code is
fixed. Additionally, some code for 1, 2, and 4-byte objects is
duplicated to handle the 3, 5, 6, and 7-byte objects for SVR4 only. The
LowerCall_Darwin_Or_64SVR4 logic is getting fairly convoluted trying to
handle both ABIs, and I propose to separate this into two functions in a
future patch, at which time the duplication can be removed.
The patch adds a new test (structsinmem.ll) to demonstrate correct
passing of structures of all seven sizes. Eight dummy parameters are
used to force these structures to be in the overflow portion of the
parameter save area.
As a side effect, this corrects the case when aggregates passed in
registers are saved into the first eight doublewords of the parameter
save area: Previously they were stored left-justified, and now are
properly stored right-justified. This requires changing the expected
output of existing test case structsinregs.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a867f378979f26e7d87bb6db5b7665a2ee4c0293 |
|
11-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch addresses PR13947.
For function calls on the 64-bit PowerPC SVR4 target, each parameter
is mapped to as many doublewords in the parameter save area as
necessary to hold the parameter. The first 13 non-varargs
floating-point values are passed in registers; any additional
floating-point parameters are passed in the parameter save area. A
single-precision floating-point parameter (32 bits) must be mapped to
the second (rightmost, low-order) word of its assigned doubleword
slot.
Currently LLVM violates this ABI requirement by mapping such a
parameter to the first (leftmost, high-order) word of its assigned
doubleword slot. This is internally self-consistent but will not
interoperate correctly with libraries compiled with an ABI-compliant
compiler.
This patch corrects the problem by adjusting the parameter addressing
on both sides of the calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6765834754cbb3cb0f15b4b15e98c5e73fa50066 |
|
09-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1c7d69bbe2de22f386ffd9ef4480f8a77be28130 |
|
08-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PR12716: PPC crashes on vector compare
Vector compare using altivec 'vcmpxxx' instructions have as third argument
a vector register instead of CR one, different from integer and float-point
compares. This leads to a failure in code generation, where 'SelectSETCC'
expects a DAG with a CR register and gets vector register instead.
This patch changes the behavior by just returning a DAG with the
vector compare instruction based on the type. The patch also adds a testcase
for all vector types llvm defines.
It also included a fix on signed 5-bits predicates printing, where
signed values were not handled correctly as signed (char are unsigned by
default for PowerPC). This generates 'vspltisw' (vector splat)
instruction with SIM out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 51aaadb7bda93040ebfc8341abed7627c99be8f7 |
|
08-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
Add floating-point to and from integer conversion
This patch add altivec support for v4i32 to v4f32 and for v4f32 to
v4i32 vector rounding conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
|
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b2544ece597192266199ec00ece2ee5bb6273cd9 |
|
05-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch splits apart PPCISelLowering::LowerFormalArguments_Darwin_Or_64SVR4
into separate versions for the Darwin and 64-bit SVR4 ABIs. This will
facilitate doing more major surgery on the 64-bit SVR4 ABI in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2c189061184925c6a8ecbb5a19e648b230a41c0e |
|
26-Sep-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the `hasFnAttr' method from Function.
The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5236ab3fdd4ce9b9990ef58cd8fac695cfbd0eaf |
|
24-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Specify MachinePointerInfo as refering to the argument value and offset of the
store when handling byval arguments. Thus preventing reordering of the store
with load with post-RA scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 419f376564d17eaef7e5b4a77b066668e4272ecc |
|
19-Sep-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Small structs for PPC64 SVR4 must be passed right-justified in registers.
lib/Target/PowerPC/PPCISelLowering.{h,cpp}
Rename LowerFormalArguments_Darwin to LowerFormalArguments_Darwin_Or_64SVR4.
Rename LowerFormalArguments_SVR4 to LowerFormalArguments_32SVR4.
Receive small structs right-justified in LowerFormalArguments_Darwin_Or_64SVR4.
Rename LowerCall_Darwin to LowerCall_Darwin_Or_64SVR4.
Rename LowerCall_SVR4 to LowerCall_32SVR4.
Pass small structs right-justified in LowerCall_Darwin_Or_64SVR4.
test/CodeGen/PowerPC/structsinregs.ll
New test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6fc3ea2f997f30827eaeb5e5c279119c79568333 |
|
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Fix the isLocalCall() by checking for linker weakness as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| eb8b7dc5362b66e45f17ce1c6d1ff1f5b79b9534 |
|
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Optimize local func calls to not emit nop for TOC restoration.
Patch by Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164138 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6c7ccaa3fd1d6e96d0bf922554b09d2b17c3b0e3 |
|
12-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Fix PR11985
- BlockAddress has no support of BA + offset form and there is no way to
propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
support BA + offset addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d2a35f2937af443241fc3d1b0c6104a587170f24 |
|
30-Aug-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCISelLowering.cpp: Fix r162725.
[Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good!
Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 25f6b5a5541e34f8e703f0b5e090e4910dc9d0d7 |
|
30-Aug-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCISelLowering.cpp: Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 621b77ade2ff46d1d8594bddee6931b2f4a14706 |
|
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC Freescale e500mc and e5500 subtargets.
Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 82b3821208286aeb43f603fdac98832bd662dad9 |
|
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Eliminate redundant CR moves on PPC32.
The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and
unset if it doesn't. The solution up to now was to insert a MachineNode to
set/unset the CR bit, which produces a CR vreg. This vreg was then copied
into CR bit 6. When the register allocator saw a bunch of these in the same
function, it allocated the set/unset CR bit in some random CR register (1
extra instruction) and then emitted CR moves before every vararg function
call, rather than just setting and unsetting CR bit 6 directly before every
vararg function call. This patch instead inserts a PPCcrset/PPCcrunset
instruction which are then matched by a dedicated instruction pattern.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1144af3c9b4da48cd581156e05b24261c8de366a |
|
25-Aug-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9fb8b49380e7cf6ce88400ad65051e830563bc81 |
|
24-Aug-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Lower constant pools and jump tables via TOC on PPC64/SVR4.
In collaboration with Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0016f73ae5ebdd8e62ee640d287482fed562b369 |
|
16-Aug-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Fix typo and grammar. By Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8cc3474f72388836fa4ca7d3622289fb9ee08b41 |
|
04-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add readcyclecounter lowering on PPC64.
On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 769951f6cc6323821ce1e9f46a37817a541c884f |
|
03-Jul-2012 |
Evan Cheng <evan.cheng@apple.com> |
Target option DisableJumpTables is a gross hack. Move it to TargetLowering instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 009f7afbeb77d1cc8e962bac7057b73b6d39d62f |
|
23-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for the PPC isel instruction.
The isel (integer select) instruction is supported on the 440 and A2
embedded cores and on the POWER7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 070b8dba809dd75267327cc823118bf7e171d17d |
|
22-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Convert the PPC backend to use the new FMA infrastructure.
The existing contraction patterns are replaced with fma/fneg.
Overall functionality should be the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0fcdd8b2cc2b1bcf0aa64870d5269f9ac6dc76c0 |
|
20-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for generating reg+reg (indexed) pre-inc loads on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ac81cc3282750d724f824547bc519caec0a01bce |
|
19-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for generating reg+reg preinc stores on PPC.
PPC will now generate STWUX and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 71ffcfe9f8602785d4d9133e029c37f2fac78cc3 |
|
10-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Enable ILP scheduling for all nodes by default on PPC.
Over the entire test-suite, this has an insignificantly negative average
performance impact, but reduces some of the worst slowdowns from the
anti-dep. change (r158294).
Largest speedups:
SingleSource/Benchmarks/Stanford/Quicksort - 28%
SingleSource/Benchmarks/Stanford/Towers - 24%
SingleSource/Benchmarks/Shootout-C++/matrix - 23%
MultiSource/Benchmarks/SciMark2-C/scimark2 - 19%
MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - 15%
(matrix and automotive-bitcount were both in the top-5 slowdown list from the
anti-dep. change)
Largest slowdowns:
MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28%
MultiSource/Benchmarks/mediabench/gsm/toast/toast - 26%
MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan - 21%
SingleSource/Benchmarks/CoyoteBench/lpbench - 20%
MultiSource/Applications/d/make_dparser - 16%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3e77af4318f48228f626bb92bdf73a38d851ae4d |
|
05-Jun-2012 |
Roman Divacky <rdivacky@freebsd.org> |
PPC32 uses R2 as the TLS register. Fix the copy and paste.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fd42ed676e37c29364f53f848320b7cb706111e0 |
|
04-Jun-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Implement local-exec TLS on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 77838f9ca974bda956f4a93c20bb4307cf0c470f |
|
04-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Enable generating PPC pre-increment (r+imm) instructions by default.
It seems that this no longer causes test suite failures on PPC64 (after r157159),
and often gives a performance benefit, so it can be enabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d2ea0e10cbd158c93fb870cdd03001b9cd1156b8 |
|
25-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 413ca0d34bfefbe62946a8febc2a4939f837291e |
|
20-Apr-2012 |
Gabor Greif <ggreif@gmail.com> |
effectively back out my last change (r155190)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c77d6781d53d4ebdb5e8dba26f34bd58af1ee7cb |
|
20-Apr-2012 |
Gabor Greif <ggreif@gmail.com> |
fix obviously bogus (IMO) operand index of the load in asserts
(load only has one operand) and smuggle in some whitespace changes too
NB: I am obviously testing the water here, and believe that the unguarded
cast is still wrong, but why is the getZExtValue of the load's operand
tested against zero here? Any review is appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c909950c384e8234a7b3c5a76b7f79e3f7012ceb |
|
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a4b00b2db79bb97d29bf6b6e55322a70150527a6 |
|
19-Apr-2012 |
Gabor Greif <ggreif@gmail.com> |
zap tabs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 26c8dcc692fb2addd475446cfff24d6a4e958bca |
|
04-Apr-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 466958c2a04a74de99efd3d7e0d5bd81cdf1e1fe |
|
02-Apr-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 19aa2b5015205456b42c426ff2559e9b930e285c |
|
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Enable prefetch generation on PPC64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3f31d492a5d0fadf11290e8453f8c519a89b1302 |
|
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Set the default PPC node scheduling preference to ILP (for the embedded cores).
The 440 and A2 cores have detailed itineraries, and this allows them to be
fully used to maximize throughput.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5b00ceaeeabff8c25abb09926343c3fcb06053d8 |
|
31-Mar-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix dynamic linking on PPC64.
Dynamic linking on PPC64 has had problems since we had to move the top-down
hazard-detection logic post-ra. For dynamic linking to work there needs to be
a nop placed after every call. It turns out that it is really hard to guarantee
that nothing will be placed in between the call (bl) and the nop during post-ra
scheduling. Previous attempts at fixing this by placing logic inside the
hazard detector only partially worked.
This is now fixed in a different way: call+nop codegen-only instructions. As far
as CodeGen is concerned the pair is now a single instruction and cannot be split.
This solution works much better than previous attempts.
The scoreboard hazard detector is also renamed to be more generic, there is currently
no cpu-specific logic in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c89c744b69cecac576317a98322fd295e36e9886 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 179a4ddd1fe52a3698a4b87e024250ed508df77a |
|
24-Mar-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix small-integer VAARG on SVR4 ABI PPC64.
The PPC64 SVR4 ABI requires integer stack arguments, and thus the var. args., that
are smaller than 64 bits be zero extended to 64 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c5eaae4e9bc75b203b3a9922b480729bc4f340e2 |
|
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more static tables of registers used by calling convention to uint16_t to reduce space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b78ca423844f19f4a838abb49b4b4fa7ae499707 |
|
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers and opcode in static tables in the target specific backends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e46137f498fa81a088f13d24c79242eed3ff45a7 |
|
06-Mar-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Convert PowerPC to register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
|
28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ec52aaa12f57896fc806e849fa21a61603050ac4 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 44d23825d61d530b8d562329ec8fc2d4f843bb8d |
|
22-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bc2198133a1836598b54b943420748e75d5dea94 |
|
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 263109d822314305822796a2cc05e98304793051 |
|
20-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove a bunch of unused variable assignments.
Found by the clang static analyzer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ed4c8c633c52a40ad1a3e8687f290be4aeb1f0e8 |
|
15-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f321e1075eabae96f62b1f2570d9dee5d10b8200 |
|
07-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove VectorExtras. This unused helper was written for a type of API that is discouraged now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 63974b2144c87c962effdc0508c27643c8ad98b6 |
|
13-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4a4fdf3476473021f62d5b02e8ee8802f5b25e5a |
|
08-Dec-2011 |
Owen Anderson <resistor@mac.com> |
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8a8d479214745c82ef00f08d4e4f1c173b5f9ce2 |
|
02-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 768c65f677af3f05c2e94982043f90a1bfaceda5 |
|
22-Nov-2011 |
Hal Finkel <hfinkel@anl.gov> |
add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d9190c0f148b218ab046deadd0c7ae475414cde5 |
|
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Remove some unnecessary includes of PseudoSourceValue.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d752e0f7e64585839cb3a458ef52456eaebbea3c |
|
08-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added invariant field to the DAG.getLoad method and changed all calls.
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 15701f8969fcb36899a75ca2df6fdcbc52141106 |
|
27-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Rename NonScalarIntSafe to something more appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c61291609d5d2044fa9f9fdcb1fe22cfd7c998e2 |
|
17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Revert change to function alignment b/c existing logic was fine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 98daa9dcc8cf5bf87f06a085793c543c035313d9 |
|
17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Instructions for Book E PPC should be word aligned, set function alignment to reflect this
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d712f935f7e027a733741e6ca67b3237a59f65d1 |
|
14-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Add an implementation of the CanLowerReturn function to the PPC backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 28b77e968d2b01fc9da724762bd8ddcd80650e32 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4a544a79bd735967f1d33fe675ae4566dbd17813 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0aaa9195b53e693eb8618fef305e3799b5b77771 |
|
30-Aug-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Set CR1EQ only when lowering vararg floating arguments (not any vararg
arguments as before), unset CR1EQ otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4db5acaf48c119b2bb7ad93b10dfcfe8b58dcfdb |
|
29-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 26689ac37ebec3b358588089415509285e558de9 |
|
03-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 94b9550a32d189704a8eae55505edf62662c0534 |
|
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d5601cc810486e6ca9b5bfb3634455061eb10f07 |
|
24-Jul-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Set PPCII::MO_DARWIN_STUB only on MacOSX < 10.5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| db125cfaf57cc83e7dd7453de2d509bc8efd0e5e |
|
18-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 33390848a7eca75301d04a59b89b516d83e19ee0 |
|
08-Jul-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| cbb11869c47bdf8f3fa540dc0ee44075c0da8598 |
|
04-Jul-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Remove accidentaly left node from previous iteration of the patch.
Noticed by Benjamin Kramer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bdb226ec83adf2e052f80f31ead21006b240c82f |
|
28-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Implement ISD::VAARG lowering on PPC32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 951cd021c10966f3ae146588b2466deaef730cb6 |
|
17-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Fix a few places where 32bit instructions/registerset were used on PPC64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133260 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4e3adfde653e8216a7f6faa726775f63f16e28d2 |
|
15-Jun-2011 |
Eli Friedman <eli.friedman@gmail.com> |
PR10136: fix PPCTargetLowering::LowerCall_SVR4 so that a necessary CopyToReg doesn't appear to be dead.
Roman, since you're writing tests for other PPC-SVR4 vararg-related stuff, would you mind writing a test for this?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 471e4224809f51652c71f319532697a879a75a0d |
|
09-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Add a parameter to CCState so that it can access the MachineFunction.
No functional change.
Part of PR6965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0c9b559bfd0b476c2dde787285a1195f3142c423 |
|
03-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.
- When lowering an indirect call use CTR8 when targeting 64bit.
- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.
The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 100c83341676d8aae8fc34b5452563ed08b14f3e |
|
03-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d76773a22169fae235be98df7034bc2544492333 |
|
19-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fc5d305597ea6336d75bd7f3b741e8d57d6a5105 |
|
06-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the logic for determining function alignment more explicit. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 558692fd0a31d4d3ae4fd09a3a02f80da2e44e5c |
|
20-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OS
triple component.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 14e2a90b7b0bb4e53e0e66866575d143ce5997b4 |
|
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
Target/PPC: Eliminate a use of getDarwinVers().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
|
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5fcb81dace175106024941b09fa27aecba2d7db7 |
|
04-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Insert code in the right location when lowering PowerPC atomics.
This causes defs to dominate uses, no instructions after terminators, and other
goodness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2684c5db84479456b2ff8264df6f414c9d240fa1 |
|
04-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use X0 instead of R0 for the zero register on ppc64.
The 32-bit R0 cannot be used where a 64-bit register is expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128828 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 95771afbfd604ad003fa3723cac66c9370fed55d |
|
25-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 68e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1 |
|
22-Feb-2011 |
Devang Patel <dpatel@apple.com> |
Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working.
- The debugger needs to be aware of prolog_end attribute attached with line table entries.
- The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a901129169194881a78b7fd8953e09f55b846d10 |
|
16-Feb-2011 |
Stuart Hastings <stuart@apple.com> |
Swap VT and DebugLoc operands of getExtLoad() for consistency with
other getNode() methods. Radar 9002173.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e9a7ea68653689966417443b8ac2528c1d9d3ccf |
|
31-Jan-2011 |
Devang Patel <dpatel@apple.com> |
Keep track of incoming argument's location while emitting LiveIns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 955ed73d12f2b186ef3f80da872b702cd7f2895b |
|
18-Jan-2011 |
Jeffrey Yasskin <jyasskin@google.com> |
Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 16c29b5f285f375be53dabaa73e3e91107485fe4 |
|
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8e68c3873549ca31533e2e3e40dda3a43cb79566 |
|
23-Dec-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Change all self assignments X=X to (void)X, so that we can turn on a
new gcc warning that complains on self-assignments and
self-initializations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
|
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bf17cfa3f904e488e898ac2e3af706fd1a892f08 |
|
23-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6d2ff122af017a24b6e94d4f98f40a3edc0bb62d |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
convert the operand bits into bitfields since they are all combinable in
different ways. Add $non_lazy_ptr support, and proper lowering for
global values.
Now all the ppc regression tests pass with the new instruction printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1e61e69d401045c54b15815f15a0fdb3ca56a9b5 |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add targetoperand flags for jump tables, constant pool and block address
nodes to indicate when ha16/lo16 modifiers should be used. This lets
us pass PowerPC/indirectbr.ll.
The one annoying thing about this patch is that the MCSymbolExpr isn't
expressive enough to represent ha16(label1-label2) which we need on
PowerPC. I have a terrible hack in the meantime, but this will have
to be revisited at some point.
Last major conversion item left is global variable references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b908258d59745ab9f150c66f94541951cf9c9211 |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement support for the MO_DARWIN_STUB TargetOperand flag,
and have isel apply to to call operands as required. This allows
us to get $stub suffixes on label references on ppc/tiger with the
new instprinter, fixing two tests. Only 2 to go.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1e96bab329eb23e4ce8a0dc3cc6b33a3f03d15bf |
|
04-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
In the calling convention logic, ValVT is always a legal type,
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1440e8b918d7116c3587cb95f4f7ac7a0a0b65ad |
|
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Inside the calling convention logic LocVT is always a simple
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 44ab89eb376af838d1123293a79975aede501464 |
|
29-Oct-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6abfa46987e4cb47e2d88ea02574c2c082b0625d |
|
21-Oct-2010 |
Duncan Sands <baldrick@free.fr> |
Remove some variables that are never really used
(gcc-4.6 warns about these).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4f9af2ef65febd20e73ef00d868d3fb94db7afd9 |
|
11-Oct-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
PowerPC varargs functions store live-in registers on the stack. Make sure we use
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.
This fixes PR8357.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 749dc72bdcf214b1a3e2b4eee37e836a39e6bdea |
|
10-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix the expansion of va_arg instruction on PPC to know the arg
alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6229d0acb8f395552131a7015a5d1e7b2bae2111 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
update a bunch of code to use the MachinePointerInfo version of getStore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| da2d8e1032eb4c2fefb1f647d7877910b9483835 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate an old SelectionDAG::getTruncStore method, propagating
MachinePointerInfo around more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3d6ccfba314ed38e4506dae2781a060e9a3e07ac |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
propagate MachinePointerInfo through various uses of the old
SelectionDAG::getExtLoad overload, and eliminate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d1c24ed81c43635d00ff099844a9d0614021a72b |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert the targets off the non-MachinePointerInfo of getLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e72f2027e9116c55a5b39ac72732df8d6c45d37c |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 59db5496f4fc2ef6111569e542f8b65480ef14c1 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert targets to the new MF.getMachineMemOperand interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0e3a1a8f8fbe34d47c83d19c8b11a3bfdcacad00 |
|
04-Aug-2010 |
Torok Edwin <edwintorok@gmail.com> |
Use indirect calls in PowerPC JIT.
See PR5201. There is no way to know if direct calls will be within the allowed
range for BL. Hence emit all calls as indirect when in JIT mode.
Without this long-running applications will fail to JIT on PowerPC with a
relocation failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e3837014d6793cafdeba99c21dd5682f16131fd5 |
|
02-Aug-2010 |
Eli Friedman <eli.friedman@gmail.com> |
PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bcc8017c738e92d9c1af221b11c4916cb524184e |
|
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c9403659a98bf6487ab6fbf40b81628b5695c02e |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0d881dabc1a4e1aefad6dd38de166d8358285638 |
|
07-Jul-2010 |
Devang Patel <dpatel@apple.com> |
Propagate debug loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 14152b480d09c7ca912af7c06d00b0ff3912e4f5 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply r107655 with fixes; insert the pseudo instruction into
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 258c58cc6257cf61c9bdbb9c4cea67ba2691adf0 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert r107655.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b81c771c0d9ab5a980caf3383932b051eafd1a39 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of custom-inserter functions to handle the case where
the pseudo instruction is not at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ed2ae136d29dd36122d2476801e7d7a86e8301e3 |
|
03-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 90c64f4aac95ebfcdeb8ad78a373fdb9e61b002c |
|
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove initialized but otherwise unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1784d160e4efa75782884d451d0788b9457e67dc |
|
25-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e368b460a206fafa0d31d5d059b1779b94f7df8c |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate unnecessary uses of getZExtValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2457f2c66184e978d4ed8fa9e2128effff26cb0b |
|
22-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 08673d295056c93628973c5c54724ac294faef88 |
|
04-May-2010 |
Dale Johannesen <dalej@apple.com> |
Implement builtin_return_address(x) and builtin_frame_address(x)
on PPC for x!=0. 7624113.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e566763b1915c7a4821ce95937b763724d271fec |
|
21-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f0757b0edc1ef3d1998485d3f74cadaa3f7180a0 |
|
21-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers on TargetMachine and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1e93df6f0b5ee6e36d7ec18e6035f0f5a53e5ec6 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 37f32ee7ffe77d7c2bc1b185802e98979612f041 |
|
16-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 46510a73e977273ec67747eb34cbdb43f815e451 |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c3b0c341e731b27b550ee9dcded9c17232b296b8 |
|
08-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 20adc9dc4650313f017b27d9818eb2176238113d |
|
04-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c7f3ace20c325521c68335a1689645b43b06ddf0 |
|
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f28f8bc40eedc6304ab25dd8bed486fa08f51f70 |
|
02-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Correctly lower memset / memcpy of undef. It should be a nop. PR6767.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e754d3fb852abdeaf910c7331eed60f6303597c1 |
|
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Revert r100191 since it breaks objc in clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e33c848fa481b038d5ad0c7c898c33b2b27ec71e |
|
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 42642d06c915a26af1400de6ce6a53c333e5c247 |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add comments about DstAlign and SrcAlign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100132 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 94107ba9ceaa199f8e5c03912511b0619c84226d |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Avoid using floating point stores to implement memset unless the value is zero.
- Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 255f20f7f76e4ca1ac1c73294852cb6fcb18c77d |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix sdisel memcpy, memset, memmove lowering:
1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
ops more effectively.
rdar://7774704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 100f090adde26005b9f1eca96871dff52825b27b |
|
31-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 808bab0169ab7d2e8dfdc72dd2c991cd8ff2396d |
|
30-Mar-2010 |
Mon P Wang <wangmp@apple.com> |
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 505ad8bed3321bc4b99af8fba4844efe2fe9e67a |
|
15-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Now that the default for Darwin platforms is to place the LSDA into the TEXT
section, remove the target-specific code that performs this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 149add0d2855aee8f5821542c98121c11293ee83 |
|
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
tidy indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 53351a175df59c0f8b96011f30842d87046fc9d6 |
|
12-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
The same situation that effected ARM effects PPC with regards to placing the
LSDA into the TEXT section. We need to generate non-lazy pointers to it on
Mach-O. However, the object the NLP points to may be local to the translation
unit. If so, then the NLP needs to have the value of that object specified
instead of "0", which the linker interprets as "external".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f7b730425fc45a28cafddf6e9907cd89acdae2aa |
|
09-Mar-2010 |
Dale Johannesen <dalej@apple.com> |
The address of an indirect call must be in R12 on Darwin.
Make it so. (This patch is in LowerCall_Darwin, which seems
to be used by SVR4 code as well; since that doesn't belong here,
I haven't worried about this case.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98077 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 46ada19645c981a0b7932487d163f7582074a4d9 |
|
02-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove dead parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 362dd0bef5437f85586c046bc53287b6fbe9c099 |
|
15-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move TLOF implementations to libCodegen to resolve layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 534502d1e9579ceb843860d6fa886fb4265fee94 |
|
15-Feb-2010 |
David Greene <greened@obbligato.org> |
Remove an assumption of default arguments. This is in anticipation of a
change to SelectionDAG build APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1797ed50f488f2030f9f9a0ac7426262abf5220a |
|
08-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Rename the PerformTailCallOpt variable to GuaranteedTailCallOpt to reflect
its current purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 022d9e1cef7586a80a96446ae8691a37def9bbf4 |
|
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 942619695f4bd77934c09a1cae0fb39ae59edac3 |
|
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6c2e8a9217ced50da49fb79c569317a50b101f90 |
|
30-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
PPC is not ready for sibcall optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0c439eb2c8397996cbccaf2798e598052d9982c8 |
|
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3ea3c2461932d96d3defa0a9aa93ffaf631bb19d |
|
22-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Add more plumbing. This time in the LowerArguments and "get" functions which
return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3a84dae654630a89a91a73807201b6067c4774ec |
|
18-Dec-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add support for calls through function pointers in the 64-bit PowerPC SVR4 ABI.
Patch contributed by Ken Werner of IBM!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b60d5194f52349b74914593919764fe8f4396bdf |
|
24-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Make capitalization of names starting "is" more consistent.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 735afe14eea8049bf69210ce8a3512e391fc643f |
|
24-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bef8888a9197655512f156e50b10799da7240252 |
|
21-Nov-2009 |
Devang Patel <dpatel@apple.com> |
We are not using DBG_STOPPOINT anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 29cbade25aa094ca9a149a96a8614cf6f3247480 |
|
21-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Target-independent support for TargetFlags on BlockAddress operands,
and support for blockaddresses in x86-32 PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1e608819aa26c06b1552521469f2211339e3bfe0 |
|
13-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Adjust isConstantSplat to allow for big-endian targets.
PPC is such a target; make it work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3f2bf85d14759cc4b28a86805f566ac805a54d00 |
|
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Add a bool flag to StackObjects telling whether they reference spill
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3d90dbee695e723f422dafca3fc75f193268ab9e |
|
04-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add PowerPC codegen for indirect branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ff89dcb06fbd103373436e2d0ae85f252fae2254 |
|
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2.
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 20270c909357e5e501cac1f5393430dfacfc57d8 |
|
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6553155172a2e74feff1253837daa608123de54a |
|
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert 84315 for now. Re-thinking the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bf125583f8bd8196a34921276add7f304b7c1433 |
|
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename getFixedStack to getStackObject. The stack objects represented are not
necessarily fixed. Only those will negative frame indices are "fixed."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ae03af26635b5831d1370b5bc161ced577397200 |
|
28-Sep-2009 |
Dan Gohman <gohman@apple.com> |
LBRX no longer has an explicit SrcValueSDNode operand, so the type
operand is now at index 2, rather than 3. This fixes the
"Invalid child # of SDNode!" failures on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c76909abfec876c6b751d693ebd3df07df686aa0 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 602b0c8c17f458d2c80f2deb3c8e554d516ee316 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6acaaa8f32a52772952c2171ad8ee1f7a896a1c9 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Don't try to use pre-indexed addressing with sthbrx/stwbrx
instructions. This fixes a PowerPC bug exposed by some unrelated
changes I'm working on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ce31910eae5bd4896fa6c27798e7b26885691d3b |
|
19-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
|
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c2d98bc0d682419f09659d94afefd6a6266dd6ee |
|
06-Sep-2009 |
Duncan Sands <baldrick@free.fr> |
Remove some not-really-used variables, as warned
about by icc (#593, partial). Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81115 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 65c3c8f323198b99b88b109654194540cf9b3fa5 |
|
02-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c69d74a5d41a6c5e92f9d947f2fa181f48626ca5 |
|
31-Aug-2009 |
Duncan Sands <baldrick@free.fr> |
Revert commit 80428. It completely broke exception
handling on x86-32 linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9b35a09e7e5b1aa26588e3852fe00a42b4f383ba |
|
29-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
- Add target lowering methods to get the preferred format for the FDE and LSDA
encodings.
- Make some of the values emitted by the FDEs dependent upon the pointer
size. This is in line with how GCC does things. And it has the benefit of
working for Darwin in 64-bit mode now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 45cfe545ec8177262dabc70580ce05feaa1c3880 |
|
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Change Pass::print to take a raw ostream instead of std::ostream,
update all code that this affects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6b16eff207f99bbde3c0f7340452a5287218772c |
|
15-Aug-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add support for the PowerPC 64-bit SVR4 ABI.
The Link Register is volatile when using the 32-bit SVR4 ABI.
Make it possible to use the 64-bit SVR4 ABI.
Add non-volatile registers for the 64-bit SVR4 ABI.
Make sure r2 is a reserved register when using the 64-bit SVR4 ABI.
Update PPCFrameInfo for the 64-bit SVR4 ABI.
Add FIXME for 64-bit Darwin PPC.
Insert NOP instruction after direct function calls.
Emit official procedure descriptors.
Create TOC entries for GlobalAddress references.
Spill 64-bit non-volatile registers to the correct slots.
Only custom lower VAARG when using the 32-bit SVR4 ABI.
Use simple VASTART lowering for the 64-bit SVR4 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fdf229eda95a542fc34d5182e1a91a22789ba122 |
|
14-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove HasCrazyBSS and add a flag in TAI to indicate that '.section'
must be emitted for PowerPC-Linux '.bss' section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78958 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1d0be15f89cb5056e20e2d24faa8d6afb1573bca |
|
13-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Push LLVMContexts through the IntegerType APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 23b9b19b1a5a00faa9fce0788155c7dbfd00bfb1 |
|
12-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 70671845adce8ab36ae596bb06d0375459a7a2af |
|
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Continue the SimpleValueType-ification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 77547befdc430633aaedf4130ddf17d953ed552e |
|
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 892e18239308f8a02a4c83758616be84a459c19d |
|
09-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
1. Make MCSection an abstract class.
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 98ca4f2a325f72374a477f9deba7d09e8999c29b |
|
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3be03406c9c3b2075d5ae416499af2f15f703d6f |
|
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Normalize Subtarget constructors to take a target triple string instead of
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f26e03bc7e30162197641406e37e662a15d80f7e |
|
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
refactor section construction in TLOF to be through an explicit
initialize method, which can be called when an MCContext is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| debcb01b0f0a15f568ca69e8f288fade4bfc7297 |
|
30-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Move types back to the 2.5 API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4bb253c60f895131371aa2ad1bfa5a2bea213f78 |
|
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
the apple "ld_classic" linker doesn't support .literal16 in 32-bit
mode, and "ld64" (the default linker) falls back to it in -static
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f0144127b98425d214e59e4a1a4b342b78e3642b |
|
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e922c0201916e0b980ab3cfe91e1413e68d55647 |
|
22-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Get rid of the Pass+Context magic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d1474d09cbe5fdeec8ba0d6c6b52f316f3422532 |
|
09-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Thread LLVMContext through MVT and related parts of SDISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| dac237e18209b697a8ba122d0ddd9cad4dfba1f8 |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2a9ddfb903ae3baede7282348afae1f750905248 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Refactor ABI code in the PowerPC backend.
Make CalculateParameterAndLinkageAreaSize() Darwin-specific.
Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin().
Rename MachoABI to DarwinABI for consistency.
Rename ELF ABI to SVR4 ABI for consistency.
Factor out common call return lowering between the Darwin and SVR4 ABI.
Factor out common call lowering between the Darwin and SVR4 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ffd0200abfd63177257f949a3674b91dcf87bf23 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Implement the SVR4 ABI for PowerPC.
Implement LowerFORMAL_ARGUMENTS_SVR4().
Implement LowerCALL_SVR4().
Add support for split arguments.
Implement by value parameter passing for aggregates.
Add support for variable argument lists.
Create the spill area for argument registers of variable argument functions no longer at a fixed offset.
Make sure callee saved registers are spilled to the correct stack offsets.
Change allocation order of non-volatile floating-point registers.
Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls.
Add support for variable argument calls with Vector arguments.
Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers.
Stop creating illegal i8 values in LowerVASTART().
Add memory access width hints.
Make sure to reserve space on the stack for the frame pointer.
When using the SVR4 ABI, reserve r13 for the Small Data Area pointer.
Assure that the frame pointer is spilled to the correct location on the stack.
Some FP registers were not marked as volatile.
Make sure the i64 words from a long double are passed either both in registers or both on the stack.
Only put integer arguments in registers which are not marked with the inreg flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6b61cd185eeb90bec93f042535594132ae1f0f41 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 667ee3cb436029e55cc788a3648ddd9f94678744 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Small cleanups in the PowerPC backend.
Small refactoring in LowerFORMAL_ARGUMENTS().
Correct minor formatting issues.
Remove size argument of CreateCopyOfByValArgument().
Remove dead argument from CalculateStackSlotSize().
Remove unused variable ReturnAddrIndex from various targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b4202b84d7e54efe5e144885c7da63e6cc465f80 |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 20c568f366be211323eeaf0e45ef053278ec9ddc |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4c9369df57a52cec5e1fc735e61a979766288074 |
|
04-Jun-2009 |
Dale Johannesen <dalej@apple.com> |
Fix FP_TO_UINT->i32 on ppc32 -mcpu=g5. This was
using Promote which won't work because i64 isn't
a legal type. It's easy enough to use Custom, but
then we have the problem that when the type
legalizer is promoting FP_TO_UINT->i16, it has no
way of telling it should prefer FP_TO_SINT->i32
to FP_TO_UINT->i32. I have uncomfortably hacked
this by making the type legalizer choose FP_TO_SINT
when both are Custom.
This fixes several regressions in the testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c06441e5ea55d1e48a85e99ed2615ff4f459b4c2 |
|
28-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Return the operand rather than a null SDValue when the given SELECT_CC
is actually legal. Part of LegalizeDAG cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ba2352b0663e718855d1898fab6d3308dedd14fc |
|
27-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Ger rid of some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1a8229b1628831da37778e9200824e48c5a38172 |
|
24-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Make the PPC backend use a legal type for the operands to the BUILD_VECTOR
nodes it generates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8d730fbde54b7ac9809fc12852c2a8d30f5bec3d |
|
11-May-2009 |
Jay Foad <jay.foad@gmail.com> |
Don't #include DerivedTypes.h from TargetData.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9008ca6b6b4f638cfafccb593cbc5b1d3f5ab877 |
|
27-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 15684b29552393553524171bff1913e750f390f8 |
|
24-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b706d29f9c5ed3ed9acc82f7ab46205ba56b92dc |
|
24-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f2950b00513e3d3c67c957e664eb3533adc3da22 |
|
03-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use early exit to reduce indentation. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 24e338e8a3dab2923db30fe63d77a5ac95456ff9 |
|
03-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Generalize BuildVectorSDNode::isConstantSplat to use APInts and handle
arbitrary vector sizes. Add an optional MinSplatBits parameter to specify
a minimum for the splat element size. Update the PPC target to use the
revised interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a27ea9e89f38e9bcca4d67defb0bae887a16d72c |
|
01-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Combine PPC's GetConstantBuildVectorBits and isConstantSplat functions to a new
method in a BuildVectorSDNode "pseudo-class".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a87008d90b7d894cfca53d407642acfd7be2af3c |
|
25-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| df38043a46b873acb98e7ce0c700d82c1d888772 |
|
25-Feb-2009 |
Scott Michel <scottm@aero.org> |
Remove all "cached" data from BuildVectorSDNode, preferring to retrieve
results via reference parameters.
This patch also appears to fix Evan's reported problem supplied as a
reduced bugpoint test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4214a5531cdbe538a358033f1847e55c4436be1b |
|
23-Feb-2009 |
Scott Michel <scottm@aero.org> |
Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fdc40a0a696c658d550d894ea03772e5f8af2c94 |
|
17-Feb-2009 |
Scott Michel <scottm@aero.org> |
Remove trailing whitespace to reduce later commit patch noise.
(Note: Eventually, commits like this will be handled via a pre-commit hook that
does this automagically, as well as expand tabs to spaces and look for 80-col
violations.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 536a2f1f8467a17f6d145bd83f25faae1f689839 |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove refs to non-DebugLoc version of BuildMI from PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6f38cb61a94b3abab70f0ee463bdcf55d86d334e |
|
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Use getDebugLoc forwarder instead of getNode()->getDebugLoc.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1fdbc1dd4e9cb42c79a30e8dc308c322e923cc52 |
|
07-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b300d2aa3ef08b5074449e2c05804717f488f4e4 |
|
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of the last non-DebugLoc versions of getNode!
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base. There's no
sensible way to associate debug info with these. I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands.
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e8d7230f480654cdb8ff1c3d0a38e1e9ab0bd55f |
|
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc getNode variants. Use
getCALLSEQ_{END,START} to permit passing no DebugLoc
there. UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| de06470330260f5937e7ca558f5f5b3e171f2ee5 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc versions of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f5f5dce897269885754fc79adeb809194da52942 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Eliminate remaining non-DebugLoc version of getTargetNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ed2eee63a6858312ed17582d8cb85a6856d8eb34 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode. Lots of
caller changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3484c09e0da3c05c8a78946e090c7610208d937b |
|
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove a non-DebugLoc version of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4be0bdf7c1162824927dd3de89e016ae4934d0d6 |
|
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of getMergeValues, ZeroExtendInReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a05dca4f9e051fad19fe9b5f6cce2715c1e5d505 |
|
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 33c960f523f2308482d5b2816af46a7ec90a6d3d |
|
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of getLoad and getStore.
Adjust the many callers of those versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 39355f9fea790c5a1b12ef0fdcfeac3f533232ea |
|
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc forms of the exotic forms
of Lod and Sto; patch uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63716 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f5d9789a7fddc9173cee104c8f25a7564bad3f28 |
|
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove some more non-DebugLoc versions of construction
functions, with callers adjusted to fit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8ad9b43e690e8773cf836b30e8da26bc71e18844 |
|
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove a few non-DebugLoc versions of node creation
functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7d2ad624fa749a6d3edac0d94e9c107989c16304 |
|
31-Jan-2009 |
Dale Johannesen <dalej@apple.com> |
Make LowerCallTo and LowerArguments take a DebugLoc
argument. Adjust all callers and overloaded versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ee5c2b8ba2bd9670931705ca04a46052d534ade9 |
|
16-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 73e0914848662404cf2aa18eb049ff5aae543388 |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Const-qualify getPreIndexedAddressParts and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5480c0469e5c0323ffb12f1ead2abd169d6cc0e7 |
|
01-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType. In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| aaffa05d0a652dd3eae76a941d02d6b0469fa821 |
|
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
There are no longer any places that require a
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1607f05cb7d77d01ce521a30232faa389dbed4e2 |
|
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 25cf2275ff7de3de3bc0e508abaf457413d74725 |
|
24-Nov-2008 |
Duncan Sands <baldrick@free.fr> |
If the type legalizer actually legalized anything
(this doesn't happen that often, since most code
does not use illegal types) then follow it by a
DAG combiner run that is allowed to generate
illegal operations but not illegal types. I didn't
modify the target combiner code to distinguish like
this between illegal operations and illegal types,
so it will not produce illegal operations as well
as not producing illegal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 03228089d5235f8c90477f88809139464e9c6ea5 |
|
23-Nov-2008 |
Duncan Sands <baldrick@free.fr> |
Rename SetCCResultContents to BooleanContents. In
practice these booleans are mostly produced by SetCC,
however the concept is more general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 53e4e4478c69c2c2115db833b54385117c764d14 |
|
07-Nov-2008 |
Dale Johannesen <dalej@apple.com> |
Make FP tests requiring two compares work on PPC (PR 642).
This is Chris' patch from the PR, modified to realize that
SETUGT/SETULT occur legitimately with integers, plus
two fixes in LegalizeDAG to pass a valid result type into
LegalizeSetCC. The argument of TLI.getSetCCResultType is
ignored on PPC, but I think I'm following usage elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2fbfbd2a052fc3935271e441ceb1e401f26d145f |
|
30-Oct-2008 |
Duncan Sands <baldrick@free.fr> |
Shift amounts should have type getShiftAmountTy
(i32 for PPC, not i8). Correct this, and some
formatting while there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 57760d96e2dfb485dc53fe2799df24bd18157abb |
|
28-Oct-2008 |
Duncan Sands <baldrick@free.fr> |
Fix darwin ppc llvm-gcc build breakage: intercept
ppcf128 to i32 conversion and expand it into a code
sequence like in LegalizeDAG. This needs custom
ppc lowering of FP_ROUND_INREG, so turn that on and
make it work with LegalizeTypes. Probably PPC should
simply custom lower the original conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 54aeea39a743effe88eedb43d2f7f4805e806ab5 |
|
21-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Disable constant-offset folding for PowerPC, as the PowerPC target
isn't yet prepared for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0329466b6b4927f4e6f5d144891fef06a027fec5 |
|
14-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename LoadX to LoadExt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e563bbc312f8b11ecfe12b8187176f667df1dff3 |
|
12-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7810bfed5570c192e0714a8fd0e5130a0c38dd2e |
|
26-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode's getSignExtended to getSExtValue, for
consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 86098bd6a63d2cdf0c9be9ef3151bd2728281fd7 |
|
26-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add "inreg" field to CallSDNode (doesn't increase
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| da43bcf624acb56a3d77bb5ae9a02728af032613 |
|
24-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| eaf42abab6d465c38891345d999255871cf03943 |
|
24-Sep-2008 |
Devang Patel <dpatel@apple.com> |
s/ParameterAttributes/Attributes/g
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0bb41608e94adfe9884bc188457c4f6ae47ea43c |
|
22-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Make log, log2, log10, exp, exp2 use Expand by
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7795932d41a84c921a5d348b7fa70f5d32e146d0 |
|
17-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Add trampoline support to PPC. GCC simply calls the "__trampoline_setup"
function with appropriate parameters. This allows us to support blocks on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 056292fd738924f3f7703725d8f630983794b5a5 |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9468a9b6beed640eca64274c8dcc5aed3b94450b |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 095cc29f321382e1f7d295e262a28197f92c5491 |
|
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f5aeb1a8e4cf272c7348376d185ef8d8267653e0 |
|
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 209a4099f96f0dfd340fab4ffaf2c2d8fc15aad6 |
|
11-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Succumb utterly to compatibility and implement
__sync_fetch_and_nand as ANDC, even though that's
not what nand means.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56087 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7794f2a3a7778bdbc9bdd861db1fe914450e0470 |
|
04-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a619d012c13bee0572b96b045723dff5a117a5c2 |
|
02-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Fix some bugs in the code sequences for atomics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 93c53e5583427ee567293a9a21c6c76fccf218ca |
|
31-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
fix a bunch of 80-col violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3156b62855667566bf48641252526b57a8c46a49 |
|
31-Aug-2008 |
Bill Wendling <isanbard@gmail.com> |
Expand for ROTR with MVT::i64.
Dale, Could you please review this?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ea9eedb7877008082b314b7ab322843fe2d402b5 |
|
30-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Add ppc partial-word ATOMIC_CMP_SWAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0e55f0678cf3b40aa6e6d6139419254e568d7227 |
|
29-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Add partial word version of ATOMIC_SWAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
|
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5ad0bf658aa1e3df4b15b64647a6f91e0641c294 |
|
28-Aug-2008 |
Mon P Wang <wangmp@apple.com> |
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 97efa365869d3b7b62836434585360a232836f0e |
|
28-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Implement partial-word binary atomics on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 99a6cb92d173c142073416c81efe6d3daeb80b49 |
|
27-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
disallow direct access to SDValue::ResNo, provide a getter instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bdab93a2ef5d9574bb4e322e020849f9bc9c90d7 |
|
26-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Implement 32 & 64 bit versions of PPC atomic
binary primitives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 140a8bb00640a5af4ae29516ac7c18c22f75c2be |
|
25-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Remove PPC-specific lowering for atomics; the
generic stuff works fine.
Mark rewritten cmp-and-swap as not using CR1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 65e3973dff46a54ff764d09f57ebe59fbff6bbdf |
|
25-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
It's important for the cmp-and-swap to balance
loads and stores but it's even more important for
it to store the right value.:(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f87d6c02f5ef43c2ed54d14e4cd137758401a947 |
|
22-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Implement __sync_synchronize on ppc32. Patch by Gary Benson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5f0cfa299d16e6d43577317176cab1a463c912da |
|
22-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Rewrite ppc code generated for __sync_{bool|val}_compare_and_swap
so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1db3c92306f551a81440dffd88ce07b9fbea97f4 |
|
11-Aug-2008 |
Nate Begeman <natebegeman@mac.com> |
Implement ISD::TRAP support on PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7232464bdaae5e6e48986a1e3b9a95fac7aa7bdf |
|
31-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Add a flag to disable jump table generation (all
switches use the binary search algorithm) for
environments that don't support it. PPC64 JIT
is such an environment; turn the flag on for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54248 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8968450305c28444edc3c272d8752a8db0c2f34a |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Tidy SDNode::use_iterator, and complete the transition to have it
parallel its analogue, Value::value_use_iterator. The operator* method
now returns the user, rather than the use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 982a05955ae9cfa71b8c6f3e80fed8ce5b778a1e |
|
24-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a catastrophic PPC64 ABI bug: i32 operands which are passed in memory (all of the parameter registers are used) are loaded from sp offsets that were off by 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d038e04188047eca4749d025ef1f05f7ae660bca |
|
21-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Add VerifyNode, a place to put sanity checks on
generic SDNode's (nodes with their own constructors
should do sanity checking in the constructor). Add
sanity checks for BUILD_VECTOR and fix all the places
that were producing bogus BUILD_VECTORs, as found by
"make check". My favorite is the BUILD_VECTOR with
only two operands that was being used to build a
vector with four elements!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a7360f0178327e1ef4b1789612dbded46a704156 |
|
19-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Make sure custom lowering for LegalizeTypes
returns a node with the right number of
return values. This fixes codegen of
Generic/cast-fp.ll, Generic/fp_to_int.ll
and PowerPC/multiple-return-values.ll
when using -march=ppc32 -mattr=+64bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5330192ab59d65f285799ff5a9acd67d27417a56 |
|
12-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement llvm.atomic.cmp.swap.i32 on PPC. Patch by Gary Benson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a54cf176613f9ae8301519a61b8935652c0fb8ae |
|
12-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Include a frame index in the "fixed stack" pseudo source value
instead of using the frame index for the SVOffset, which was
inconsistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6291d69c4cf6cfff1d23c4363dc627872b825da0 |
|
10-Jul-2008 |
Chris Lattner <sabre@nondot.org> |
Remove extraneous vertical whitespace before Eric gets the wrong idea ;-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 85e7ac0353d6be357e6cab49f40304793ee601a1 |
|
10-Jul-2008 |
Chris Lattner <sabre@nondot.org> |
Fix an altivec constant miscompilation that Duncan found through
his work on legalizetypes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
|
08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 126d90770bdb17e6925b2fe26de99aa079b7b9b3 |
|
04-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Rather than having a different custom legalization
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes. No change if the
new LegalizeTypes infrastructure is not turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4bdcb61af33399d4e01fdf3c47ca1f1f5356e370 |
|
02-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Add a new getMergeValues method that does not need
to be passed the list of value types, and use this
where appropriate. Inappropriate places are where
the value type list is already known and may be
long, in which case the existing method is more
efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7f460203b0c5350e9b2c592f438e40f7a7de6e45 |
|
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect its
purpose, and give it a custom SDNode subclass so that it doesn't
need to have line number, column number, filename string, and
directory string, all existing as individual SDNodes to be the
operands.
This was the only user of ISD::STRING, StringSDNode, etc., so
remove those and some associated code.
This makes stop-points considerably easier to read in
-view-legalize-dags output, and reduces overhead (creating new
nodes and copying std::strings into them) on code containing
debugging information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f9516208e57364ab1e7d8748af1f59a2ea5fb572 |
|
30-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Revert the SelectionDAG optimization that makes
it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT. On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable. So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 28873106309db515d58889a4c4fa3e0a92d1b60e |
|
25-Jun-2008 |
Mon P Wang <wangmp@apple.com> |
Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 09d3fdc254c0b922c38f7c2bcad27c02fa0904f3 |
|
22-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Remove unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52613 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0011dc4738fbe624d44197ef9496517fd093eaa4 |
|
21-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Use MachineBasicBlock::transferSuccessors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8e4eb09b1e3571965f49edcdfb56b1375b1b7551 |
|
08-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Remove comparison methods for MVT. The main cause
of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits. Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a8a8f427d6aecfde48fa34367925423170bab41e |
|
08-Jun-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily reverting r52056. It's causing PPC to fail to bootstrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 929b39f0a03bb6ae7c7b4ba0fac3e3aa4216b822 |
|
06-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6b4a65f4e7a668815593eb9dea2b994eaad70a86 |
|
06-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
PPC preferred loop alignment is 16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 844731a7f1909f55935e3514c9e713a62d67662e |
|
13-May-2008 |
Dan Gohman <gohman@apple.com> |
Clean up the use of static and anonymous namespaces. This turned up
several things that were neither in an anonymous namespace nor static
but not intended to be global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 30e62c098b5841259f8026df1c5c45c7c1182a38 |
|
30-Apr-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5e764233f398b6929b67701672a5e78fec20ce2e |
|
27-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
A few inline asm cleanups:
- Make targetlowering.h fit in 80 cols.
- Make LowerAsmOperandForConstraint const.
- Make lowerXConstraint -> LowerXConstraint
- Make LowerXConstraint return a const char* instead of taking a string byref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8608f2eff2dab5345243c40d0bca9138f2dce6f1 |
|
19-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
64-bit atomic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 54fc97dcdc0ab747f49bd09c5a877bfd2a00e364 |
|
19-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
PPC32 atomic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6ccbbd89906157187ac04b2b3237c4aee7acd095 |
|
15-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Change Divided flag to Split, as suggested by Evan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c0cb28fd3abee9a8b40856990e04f1af2f9bd7b8 |
|
13-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Add a divided flag for the first piece of an argument divided into mulitple parts. Fixes PR1643
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 707e0184233f27e0e9f9aee0309f2daab8cfe7f8 |
|
12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 36b5c1338a03453ba1c110b120269ca972fb65a3 |
|
07-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Rename MemOperand to MachineMemOperand. This was suggested by
review feedback from Chris quite a while ago. No functionality
change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| dc1adac582fa120861f18ae7221bfe1421fea59f |
|
07-Apr-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Re-commit of the r48822, where the infinite looping problem discovered
by Dan Gohman is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6397c64441ddce3822ab0e712f224a11bd75811c |
|
03-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Backing out 48222 temporarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d27c991cebe48fdf82b5d9eec6c2a1a244f82622 |
|
30-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Fix "Control reaches the end of non-void function" warnings,
patch by David Chisnall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e326332acd5fefb9854118603b4d07d4e44b64c5 |
|
26-Mar-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Use a linked data structure for the uses lists of an SDNode, just like
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.
The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.
On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3e98c30cf5dd450879c0b9d6404353b02e2429c3 |
|
25-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Use the bit size of the operand instead of the hard-coded 32 to generate the
mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 276dcbdc8db6614cfd5004dc7dc35e437ddf9c58 |
|
21-Mar-2008 |
Duncan Sands <baldrick@free.fr> |
Introduce a new node for holding call argument
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7925ed05d0245aca0b0b2ea8d8a0b35b77c5ebd4 |
|
19-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add support for multiple return values for the PPC target by
converting call result lowering to use the CallingConvLowering
infastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 257f75d0b88a7d3d5ba5b7b7908a97f6dd56e27d |
|
17-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Make Complex long long/double/long double work
in ppc64 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fdd3ade005c7bd60f3dc74a49db82f91654e99ae |
|
17-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Next round of PPC32 ABI changes. Allow for gcc
behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be. Handle complex long long
and complex double (4 and 8 return regs).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8f5422c24b318d2680eafc177f199a180d5054da |
|
14-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Implement the real calling convention for ppc32 Altivec:
vectors go at the end of the memory area, after all
non-vector parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d75686a471ee6ed5260e29d22d54f15152bbc9b4 |
|
13-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Do not promote float params to double in varargs
calls here. This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 404d99010d2d31398a16aa1ecfa9fb198b9e0afd |
|
12-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
One more bit of Altivec parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48269 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 75092de483561e3dcfa09cfc4420577272f7ac2d |
|
12-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Implement Altivec passing to varargs functions on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 034f60ed24c53c1e37f7695965f782faec2dff2b |
|
11-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Generalize ExpandIntToFP to handle the case where the operand is legal
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d2cde68855125b6815b1575f29cd96927614b0cd |
|
10-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Default ISD::PREFETCH to expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5b8f82e35b51bf007de07a7ca9347d804084ddf8 |
|
10-Mar-2008 |
Scott Michel <scottm@aero.org> |
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0404cd97e4f6ebfe4f8057d4e21119d77654dff2 |
|
10-Mar-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Add description of individual bits in CR. This fix PR1765.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b8cafe3427a168414400e5dfcbea78996792d2c3 |
|
10-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| dc9971a2e322ddeff9eb97a6b03909094f1b8357 |
|
09-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48120 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7f96f3912e20b94627fde28edc0a292f660b9197 |
|
08-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
More ppc32 byval handling (bug fixes). Things
are looking pretty good now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 27b7db549e4c5bff4579d209304de5628513edeb |
|
08-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a2fcff4d97c8fecd58cd977c45f1a883bc6ae1c3 |
|
08-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add support for calls with i128 return values on ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5f5bf3a3fd06704e5752c91561a711fbaa856d58 |
|
07-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9ed06db5c800c347b3ceac70df420f66c62e11c1 |
|
07-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add support for lowering 128-bit shifts on ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8419dd6aa6e8a26307222bdda473ac4bdccbb693 |
|
07-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Next bits of PPC byval handling. Basically functional
but there are bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1f797a32fdc5e3841e9975756ff8c8e62cb41414 |
|
06-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Next bit of PPC ByVal handling; call-site code seems
correct now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5b3b695c2f1e11b6f5e0c89e1644211a92edab49 |
|
05-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Move PPC lowering functions into PPCTargetLowering
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 28d08fdb9f6572cafd5aae95c7caffa3cd136d8e |
|
28-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Interface of getByValTypeAlignment differed between
generic & x86 versions; change generic to follow x86
and improve comments. Add PPC version (not right
for non-Darwin.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ec59b95a19f59c075c74f01016a57218775b5d55 |
|
27-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Don't hard-code the mask size to be 32, which is incorrect on ppc64
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b3564aa8367fc38efdab0a812868f6f93b9d883e |
|
27-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert the last remaining users of the non-APInt form of
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d497d9fab6e90499c703f3e672ec001dbfa074f9 |
|
16-Feb-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e179584f9b740cf3a36bde70f8cab40de59b8081 |
|
14-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Change how FP immediates are handled.
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
if it is legal.
This allows ConstantFP to be handled like Constant, allowing for
targets that can encode FP immediates as MachineOperands.
As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants! Hooray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3 |
|
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9f72d1a73029ed3bfb1f8ced755a1aeeb36fb4f1 |
|
13-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
DAGCombine is now quite good at zapifying them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fd29e0eb060ea8b4d490860329234d2ae5f5952e |
|
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3069b8743769527ce7af6cfb6591a2f0fc2faee4 |
|
07-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Follow Chris' suggestion; change the PseudoSourceValue accessors
to return pointers instead of references, since this is always what
is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 69de1932b350d7cdfc0ed1f4198d6f78c7822a02 |
|
06-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Re-apply the memory operand changes, with a fix for the static
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fcf5d4f456e5bb2547164c150797a023d22780a4 |
|
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak ppc debug support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 334dc1f58d617dcff969a2e107febaae42bbc883 |
|
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1a0248690aaa9f7baaf1247e5f65a1c0c9e3783c |
|
31-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting
with the real FLT_ROUNDS (defined in <float.h>).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c6c391daddbafa722d9ca87d18f204e9a6e617a3 |
|
31-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Create a new class, MemOperand, for describing memory references
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.
Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.
Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ff9b373e8f5006c629af81e2619778b4c4f5249e |
|
30-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b625f2f8960de32bc973092aaee8ac62863006fe |
|
30-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f9c98e650d2795b8edfae8e1560c221029df218b |
|
23-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
The last pieces needed for loading arbitrary
precision integers. This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on. While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5c5eb80255293ece142b59e170256be0880b6bfb |
|
18-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Implement flt_rounds for PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ef97c676f97d33312eb5009522a9d51f2c25ccb1 |
|
18-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
get symbolic information for ppc ldbl nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a7a02fb828382afffd51596ee63822aa141a7147 |
|
18-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a latent bug exposed by my truncstore patch. We compiled stfiwx-2.ll to:
_test:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of:
_test:
fctiwz f0, f1
stfd f0, -8(r1)
nop
nop
lwz r2, -4(r1)
stb r2, 0(r4)
blr
The former is not correct (stores 4 bytes, not 1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ddf89566a93081cb230bb9406a72ab2d3eada4a7 |
|
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
This commit changes:
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0bd4893a0726889b942405262e53d06cf3fe3be8 |
|
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
* Introduce a new SelectionDAG::getIntPtrConstant method
and switch various codegen pieces and the X86 backend over
to using it.
* Add some comments to SelectionDAGNodes.h
* Introduce a second argument to FP_ROUND, which indicates
whether the FP_ROUND changes the value of its input. If
not it is safe to xform things like fp_extend(fp_round(x)) -> x.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 007f9847c44ddbe7fd04cba362b4ec0f0f40964b |
|
10-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
Output sinl for a long double FSIN node, not sin.
Likewise fix up a bunch of other libcalls. While
there I remove NEG_F32 and NEG_F64 since they are
not used anywhere. This fixes 9 Ada ACATS failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5a6c91a3eceb701396c30dd126079903006c5e0b |
|
21-Dec-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Fix unintented change from last commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 616585bbff926d806f154a0ae45f327c63abe54f |
|
21-Dec-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Enable EH for linux/ppc32 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3fc027df4fca0355717515abb4d6e3753e6dee2a |
|
08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
implement __builtin_return_addr(0) on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1f873003266fbdec7c2c48a965c60f4e2e35a158 |
|
28-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Implement ExpandOperationResult for ppc i64 fp->int, which fixes
CodeGen/Generic/fp_to_int.ll among others. Its unclear why this
just started failing...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0f8d9c04d9feef86cee35cf5fecfb348a6b3de50 |
|
13-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 79217064c618afecd4979aec6d2e8fe784565931 |
|
24-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Disable a couple more things for ppcf128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3311876c3c3147688b08f64c441e5bfaaa3412b3 |
|
22-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use ptr type in the immediate field of a BxA instruction so we don't end up selecting 32-bit call instruction for ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 26cb2862e982e5527ffb904568e204907ca9be17 |
|
19-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
comment fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fabd32deb025ebd47c5eb47259d2424fd789b05c |
|
19-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
More ppcf128 issues (maybe the last)?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1de7c1dd6fdedc8ab2e450ba74e4b81d13e49af2 |
|
15-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
Change LowerFP_TO_SINT to create the specific code it needs instead of
unconditionally creating an i64 bitcast. With the future legalizer
design, operation legalization can't introduce new nodes with illegal
types.
This fixes the rest of olden on ppc32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 296c1761416df3eb706dbcf5319f1f2267e1b4f7 |
|
14-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Fix type mismatch error in PPC Altivec (only causes
a problem when asserts are on). From vecLib.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a3f269f7f6211958774f151833870935c91feaee |
|
12-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Mark vector pow, ctpop, cttz, and ctlz as Expand on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f96e4de403453e57aea75bcac1ed99af686d33c4 |
|
12-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Set ISD::FPOW to Expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6eaeff29b8a6990107735f7e5f5e49da38f56223 |
|
10-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Next PPC long double bits: ppcf128->i32 conversion.
Surprisingly complicated.
Adds getTargetNode for 2 outputs, no inputs (missing).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3ce990dc051622755afc22b55f95954c5a19e779 |
|
08-Oct-2007 |
Dan Gohman <gohman@apple.com> |
When we start enabling SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM in
target-indepenent lowering, don't use them on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 638ccd52b9fa2d1d03a1e85992c09e2bf6800fc6 |
|
06-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Next powerpc long double bits. Comparisons work,
although not well, and shortening FP converts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 161e897b0fb35d156b2fe720fadabd975b0d6723 |
|
05-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
First round of ppc long double. call/return and
basic arithmetic works.
Rename RTLIB long double functions to distinguish
different flavors of long double; the lib functions
have different names, alas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f7331b3dd72409e644833ecaf62a0f6db03c97ee |
|
11-Sep-2007 |
Duncan Sands <baldrick@free.fr> |
Fold the adjust_trampoline intrinsic into
init_trampoline. There is now only one
trampoline intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 718cb665ca6ce2bc4d8e8479f46a45db91b49f86 |
|
07-Sep-2007 |
Owen Anderson <resistor@mac.com> |
Add lengthof and endof templates that hide a lot of sizeof computations.
Patch by Sterling Stein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| eaf089430e7681fcddc3465c3b33b9645273ab02 |
|
31-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Enhance APFloat to retain bits of NaNs (fixes oggenc).
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b8a80f03bf573a36b6f63b834aae2e91b82f96c6 |
|
30-Aug-2007 |
Bill Wendling <isanbard@gmail.com> |
Use i64 on a PPC64 machine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 48884cd80b52be1528618f2e9b3425ac24e7b5ca |
|
25-Aug-2007 |
Chris Lattner <sabre@nondot.org> |
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
changing the interface to allow for future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 66ffe6be0c7b50100a00cb0cc87a5d4983818572 |
|
30-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Vector fneg must be expanded into fsub -0.0, X.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 36397f50343639ce9a25996f2d790c656791ab92 |
|
27-Jul-2007 |
Duncan Sands <baldrick@free.fr> |
Support for trampolines, except for X86 codegen which is
still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 75ce010f7b6a47d9656e546b5db4a9cd77ba1dee |
|
11-Jul-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Assert when TLS is not implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 532dc2e1f2473b16b48566c1cbc9eefe94a4e58e |
|
09-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Change getCopyToParts and getCopyFromParts to always use target-endian
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ea859be53ca13a1547c4675549946b74dc3c6f41 |
|
22-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3ee774091ba6d25c7db4b0481b963454bd6d9903 |
|
19-Jun-2007 |
Chris Lattner <sabre@nondot.org> |
describe an argument, hide it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 52387be1e00291a88edc4c2b8a0b5c22478bcd83 |
|
19-Jun-2007 |
Chris Lattner <sabre@nondot.org> |
If a function is vararg, never pass inreg arguments in registers. Thanks to
Anton for half of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37641 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 51eaa86758338d5935c0eff0469c418b1256aba7 |
|
15-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f5135be3fc20534ccaee52cbfa80a8408af5672b |
|
19-May-2007 |
Dan Gohman <gohman@apple.com> |
Apply this patch:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9f5d5783ecdb02ebf2000fcf50ee67628bc2e07d |
|
15-May-2007 |
Chris Lattner <sabre@nondot.org> |
fix some subtle inline asm selection issues
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7c7ba9d2d587303a486f29c68416bd8391499f77 |
|
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in PPCTargetLowering::isLegalAddressingMode, scales other than 0/1/2
are always unsupported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0111999a88077f237c49d03c5e7891ec874b33a9 |
|
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Starting implementation of the ELF32 ABI specification of varargs handling.
LowerVASTART emits the right code if the subtarget is ELF32, the other intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ec58d9f9ddfbfe16ea40822164f340b256c89191 |
|
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ef3c030e0e08b7d9446445823f4972fcf18c1ce1 |
|
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c9addb74883fef318140272768422656a694341f |
|
31-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
implement the new addressing mode description hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1baa1971a66d6a250d07b7bee249653bd91453a0 |
|
27-Mar-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
"The C standards do say that "char" may either be a "signed char" or "unsigned
char" and it is up to the compilers implementation or the platform which is
followed."
http://www.arm.linux.org.uk/docs/faqs/signedchar.php
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4234f57fa02b1f04a9f52a7b3c2aa22d32ac521c |
|
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b2ec1cc6cb1c34d3e43559ab59619b29f010684b |
|
13-Mar-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Stack and register alignment of call arguments in the ELF ABI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 861939152debbaa15a55a196a4321837c7bc379d |
|
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b9a7bea99c8aac6eb3509df93a25fe9cc3858bde |
|
06-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
Switch PPC return lower to use an autogenerated CC description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 43c6e7cd9b0d9a3b0006650ddfac256848f10d51 |
|
01-Mar-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Implemented the frameaddress intrinsic for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 63f8fb1993bf2b4286c5a6763e2eee414a751699 |
|
27-Feb-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Differentiate between the MachO and the ELF ABI the CALL instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| caddd44be776e0dc97baf40ca8afdd405cb705a1 |
|
26-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
always lower to RETFLAG, never leave it as just ret.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34639 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4ddf7a4ca69c3f5872b568bcb523d491b29a2592 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
no really, this is the right patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34605 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 640c0ac01d17ce907a601b9fea4c29c87c37edee |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
always promote float varargs to double.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9f0bc659c8d2f1e401a9690e4900b0fd2a70bdfe |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
implement support for the linux/ppc function call ABI. Patch by
Nicolas Geoffray!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2ad9f17fee5d6395cd8db81668853e6dbf94060b |
|
22-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Simplify lowering and selection of exception ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 62819f31440fe1b1415473a89b8683b5b690d5fa |
|
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support to provide exception and selector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| dee5a5a52c45d04aa9f64a7b6e2adae37878a304 |
|
17-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Fix ixaddrs as well, allowing ppc64 to compile to:
_test2:
li r2, 0
lis r3, 1
std r2, 9024(r3)
blr
instead of:
_test2:
lis r2, 1
li r3, 0
ori r2, r2, 9024
std r3, 0(r2)
blr
This implements CodeGen/PowerPC/LargeAbsoluteAddr.ll:test2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bc681d6af490a7e67bcc8c4a4b17d18cb38ca455 |
|
17-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to:
_test:
lis r2, 743
li r3, 0
stw r3, 32751(r2)
blr
instead of:
_test:
li r2, 0
stw r2, 32751(48693248)
blr
Implement support for ppc64 as well, allowing it to produce better code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bcc5f36765e8111c13873a0c0dc874c92385d808 |
|
29-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
Finish off bug 680, allowing targets to custom lower frame and return
address nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b10308e440c80dd6ffb4b478f741ff7e5f30cb48 |
|
28-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1ee29257428960fede862fcfdbe80d5d007927e9 |
|
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Make LABEL a builtin opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d08d23315d20c568fe35b8732d4a49d298b228c2 |
|
06-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
setSetCCIsExpensive is gone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ca367b4e259efdd9366d358addbb983cce7c4360 |
|
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Provide support for FP_TO_UINT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 57fc62c8d2bf056b0d2a0e3d1b82b3b787b899f8 |
|
12-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Another step forward in PPC64 JIT support: we now no-longer need stubs
emitted for external globals in PPC64-JIT-PIC mode (which is good because
we didn't handle them before!).
This also fixes a bug handling the picbase delta, which we would get wrong
in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2060a822fee8a500017e3afc1d91cf3644553d44 |
|
11-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Missing opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d27a258d2d7691db3731135a448b7654d260cc07 |
|
11-Dec-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 85c671b90870705ba7e10baf99aa306c843f1325 |
|
07-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Fix i64 uint_to_fp on ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| efc7e52183a384917ff4deac06e829433602150a |
|
04-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Restoration of the stack pointer after a deallocation of a alloca was not
updating the SP link.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fbb74e6941ebf6c108a4e385902e5e2cd35b739d |
|
01-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
1. In ppc64 mode we need only use one GPR.
2. Float values need to be promoted to double when they are vararg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 70fa493613142f2ad99003de91b46e701f9bd605 |
|
01-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the CodeGen/PowerPC/vec_constants.ll regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 15eb329dae1dea7a5a38cf0c1074aaa3e0f78ab6 |
|
29-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Fix bug codegen'ing FP constant vectors with integer splats. Make sure the
created intrinsics have the right integer types. This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 619965d32e2cb961cc315aaece2e32f53f236784 |
|
29-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Offset for load of 32-bit arg in 64-bit world was incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7fc4a94bdd5fb2933fecf27ca0cf377e1dc70cb0 |
|
28-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Remove debug code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31970 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e9bd7b2e03252391dce5cacd4fcf68df4d4eef7a |
|
28-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
32-bit int space was not accounted for properly in lowerCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31966 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c0f64ffab93d11fb27a3b8a0707b77400918a20e |
|
28-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b1eb987ccd86e58d81dde75424d37369785910d7 |
|
18-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots.
Also, valist should create a pointer RC reg class value, not a GPRC value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 18258c640466274c26e89016e361ec411ff78520 |
|
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
convert PPC::BCC to use the 'pred' operand instead of separate predicate
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 289c2d5f4566d8d7722e3934f4763d3df92886f3 |
|
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
rename PPC::COND_BRANCH to PPC::BCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| df4ed6350b2a51f71c0980e86c9078f4046ea706 |
|
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
start using PPC predicates more consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173 |
|
16-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
This is a general clean up of the PowerPC ABI. Address several problems and
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0851b4f3eda110cc21c8d4b59f0d55bc84d9d088 |
|
15-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri
addrmodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31757 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ac011bce9e8a69f99f92d46133adbf883a91cb6f |
|
14-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of
'(shr (ctlz (sub Y, Z)), 5)'.
The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner. For example, this:
typedef struct {
unsigned prefix : 4;
unsigned code : 4;
unsigned unsigned_p : 4;
} tree_common;
int foo(tree_common *a, tree_common *b) {
return a->code == b->code;
}
Now compiles to:
_foo:
lwz r2, 0(r4)
lwz r3, 0(r3)
xor r2, r3, r2
rlwinm r2, r2, 28, 28, 31
cntlzw r2, r2
srwi r3, r2, 5
blr
instead of:
_foo:
lbz r2, 3(r4)
lbz r3, 3(r3)
srwi r2, r2, 4
srwi r3, r3, 4
subf r2, r2, r3
cntlzw r2, r2
srwi r3, r2, 5
blr
saving a cycle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2fe4bf453b433cfe7113e282a59bf0f1e7fb0195 |
|
14-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
minor tweaks, reject vector preinc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f6edf4dcf0907427f5e07012b0fe51e43fb09c45 |
|
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
ppc64 doesn't have lwau, don't attempt to form it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 94e509caeab08edb27849ea9be5dc80e74d95f38 |
|
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
implement preinc support for r+i loads on ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4eab71497d10622bd209c53f8e56152877ac5638 |
|
10-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add an initial cut at preinc loads for ppc32. This is broken for ppc64
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)
This is disabled unless -enable-ppc-preinc is passed to llc for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| cd633192272c9c433af6f40621b2bf5a38a68f30 |
|
09-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
PPC supports i32 / i64 pre-inc load / store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 144d8f09e139f691cafadbc17873943ba4c465f3 |
|
09-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31595 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| fc5b1ab94959879a91c34aee8859e652a50270d0 |
|
08-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Refactor all the addressing mode selection stuff into the isel lowering
class, where it can be used for preinc formation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3ed469ccd7b028a030b550d84b7336d146f5d8fa |
|
02-Nov-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR786:
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 331d1bc5dfe1be9090e29f9af9579888a63a9a79 |
|
02-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Implement the getRegForInlineAsmConstraint method for PPC. With recent
sdisel changes, this eliminates a ton of copies around common inline asms.
For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| dba1aeedd8179114a45be655b985455218d20806 |
|
31-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Change the prototype for TargetLowering::isOperandValidForConstraint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c35497fc2a8b984dbacede5b75b7be74c6756948 |
|
30-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
All targets expand BR_JT for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 10da9575740d9515c70a171a7c40405302d62f4a |
|
18-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
set the ppc64 stack pointer right, dynamic alloca now works for ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 56a752e00ff6fb078fd0466d9be438f7b8a1dd79 |
|
18-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Expand alloca for ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8b2794aeff151be8cdbd44786c1d0f94f8f2e427 |
|
13-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 466685d41a9ea4905b9486fea38e83802e46f196 |
|
09-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 786225adf09e606c795ef68a1f789c12f37869f2 |
|
06-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Make use of getStore().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c548428c5d7328592f4db6f6cd815af18b3152a3 |
|
04-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3fe6c1d38901929d65d6d8a61bd9b1594af0ffdd |
|
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| cf9d0acfef1503439c231f2717b3d4b3afce67e1 |
|
19-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Fold the PPCISD shifts when presented with 0 inputs. This occurs for code
like:
long long test(long long X, int Y) {
return 1ULL << Y;
}
long long test2(long long X, int Y) {
return -1LL << Y;
}
which we used to compile to:
_test:
li r2, 1
subfic r3, r5, 32
li r4, 0
addi r6, r5, -32
srw r3, r2, r3
slw r4, r4, r5
slw r6, r2, r6
or r3, r4, r3
slw r4, r2, r5
or r3, r3, r6
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
Now we produce:
_test:
li r2, 1
addi r3, r5, -32
subfic r4, r5, 32
slw r3, r2, r3
srw r4, r2, r4
or r3, r4, r3
slw r4, r2, r5
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c356a572e34131bf767f35e3fecefae36fab744a |
|
12-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects MachineConstantPoolEntry changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3a9ec2463ddeba0820f284e2952bd6919cd5e080 |
|
28-Aug-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR387:
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f6e190fae02174d465ae1f9000192269a5978c73 |
|
12-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in a recent refactoring that broke a bunch of stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e219945348207453a2d5e21021ba3211f8f94e25 |
|
11-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Eliminate use of getNode that takes a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29614 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 79e490aa23d29c20471163b28faf916af610b921 |
|
11-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Convert vectors to fixed sized arrays and smallvectors. Eliminate use of getNode that takes a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29609 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 325f0a129e57ff5d1842edd0b4b7473a4d6b47f6 |
|
11-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Fix miscompilation of float vector returns. Compile code to this:
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
blr
instead of:
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
*** vor f1, v2, v2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29607 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0d72a20630ebde26c302518077a28c9faffbd747 |
|
28-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Fix some ppc64 issues with vector code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 35d86fef1f1fc5845366c7c36803a6a3334d8a2e |
|
26-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d9989384592a3bd9dd374470a723ca8303071a2d |
|
10-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps
into i16/i32 load/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f89437d049b4a3dff2b04e2635b45068db0a6b34 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement 64-bit select, bswap, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5f9faeaa78a79e03df6bb32e9b3c779e554fe8a2 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
PPC doesn't have bit converts to/from i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 563ecfbf8207ce941ddc0ee60c65378c6b9c572f |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement 64-bit undef, sub, shl/shr, srem/urem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7b0c58cd257d2197bc178818bc081c72aae57e46 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Use i32 for shift amounts instead of i64. This gets bisort working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c08f902bb7bfcc8a97a4c7c9eb9187882dc2d6d7 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but
doesn't work right).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c91a4757b60094ade6fc82afde7f94bbe1988a7d |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Improve PPC64 calling convention support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ef957105833fad1baadabbeb48632eb0d51f9262 |
|
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Correct returns of 64-bit values, though they seemed to work before...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 059ca0f5b712e5460dcbccfa802b7adb3bccbac9 |
|
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
fix some assumptions that pointers can only be 32-bits. With this, we can
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28839 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a7a5854f1c3710f4bedf069be4771b81e449f2a3 |
|
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a7dc4a59cbb19cfb5dbc0f9ca500f26dddfbb7f6 |
|
15-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Type of extract_element index operand should be iPTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28797 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4a45abf66ee33ce3b8404ace90c4bfefda7105f8 |
|
10-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a problem exposed by the local allocator. CALL instructions are not marked
as using incoming argument registers, so the local allocator would clobber them
between their set and use. To fix this, we give the call instructions a variable
number of uses in the CALL MachineInstr itself, so live variables understands
the live ranges of these register arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7b053509063f21aa0bf6ffc82b274e8cf6b0e182 |
|
30-May-2006 |
Chris Lattner <sabre@nondot.org> |
Always reserve space for 8 spilled GPRs. GCC apparently assumes that this
space will be available, even if the callee isn't varargs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6848be1a27e08a89dcd4dd69f746471a608012cd |
|
27-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4360bdcf1fc92a0bd29cc1a8ec1d2338def29cfc |
|
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
CALL node change (arg / sign pairs instead of just arguments).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28462 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d74ea2bbd8bb630331f35ead42d385249bd42af8 |
|
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2ef5e89dc964ffb6a84d1e1a2a29c429dc4aa715 |
|
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/Generic/vector.ll:test_div with altivec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 573401237578297310a6be764805b8dfad702938 |
|
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Handle SETO* like we handle SET*, restoring behavior after Evan's setcc
change. This fixes PowerPC/fnegsel.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c703a8fbf8653ac8302ae368391a4954c307ca2c |
|
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
Make PPC call lowering more aggressive, making the isel matching code simple
enough to be autogenerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9a2a497284e2233345c4bb9cdc1044d8395fddde |
|
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
Switch PPC over to a call-selection model where the lowering code creates
the copyto/fromregs instead of making the PPCISD::CALL selection code create
them. This vastly simplifies the selection code, and moves the ABI handling
parts into one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c8b682ca196c90bfae1ea4a411a97cccc2f4bd62 |
|
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
3 changes, 2 of which are cleanup one of which changes codegen:
1. Rearrange code a bit so that the special case doesn't require indenting lots
of code.
2. Add comments describing PPC calling convention.
3. Only round up to 56-bytes of stack space for an outgoing call if the callee
is varargs. This saves a bit of stack space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c04ba7a97d5ad599d92a1817de2d7c5fbb145810 |
|
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
implement passing/returning vector regs to calls, at least non-varargs calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| abde460d4f4e2fb6a4493b2a938055e48abaf239 |
|
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
Instead of implementing LowerCallTo directly, let the default impl produce an
ISD::CALL node, then custom lower that. This means that we only have to handle
LEGAL call operands/results, not every possible type. This allows us to
simplify the call code, shrinking it by about 1/3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| af4ec0c56d2162a369fcdeba740ddda21be359b9 |
|
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Simplify the argument counting logic by only incrementing the index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b375b5e629d12db6ec2b2b816af9784c0709656e |
|
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Simplify the dead argument handling code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| be4849aabe957019bd73dd465859c7c081c9fddd |
|
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Vector args passed in registers don't reserve stack space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8ab5fe574a388598b7ca945b4cd12e2485268027 |
|
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Switch the PPC backend over to using FORMAL_ARGUMENTS for formal argument
handling. This makes the lower argument code significantly simpler (we
only need to handle legal argument types).
Incidentally, this also implements support for vector argument registers,
so long as they are not on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28331 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 00402c7ec3aaf4d6a22c1eb97b9e1c1bb3136f46 |
|
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fit in 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b65e7256ed711aa473973744403efc86e1cb2c6d |
|
12-May-2006 |
Chris Lattner <sabre@nondot.org> |
Remove dead var, fix bad override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 25b8b8cb2cd8653712b0a567edf8573a067f8ff1 |
|
28-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 37efe6764568a3829fee26aba532283131d1a104 |
|
22-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
JumpTable support! What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0090120c2b8ac3fea5427f6fae6f36fc3dc50dca |
|
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a crash on:
void foo2(vector float *A, vector float *B) {
vector float C = (vector float)vec_cmpeq(*A, *B);
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
*A = C;
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f70f8d91a79a3474345ad51c1899276eac7825c1 |
|
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
pretty print node name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 90564f26d17701e11effa2f4e0fb9a18d8a91274 |
|
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| cea2aa77eb815d41ad59ecdd110ec42bc5b567c8 |
|
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Use vmladduhm to do v8i16 multiplies which is faster and simpler than doing
even/odd halves. Thanks to Nate telling me what's what.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27793 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 19a815238e55458e95f99b4dad31ed053c9f635c |
|
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement v16i8 multiply with this code:
vmuloub v5, v3, v2
vmuleub v2, v3, v2
vperm v2, v2, v5, v4
This implements CodeGen/PowerPC/vec_mul.ll. With this, v16i8 multiplies are
6.79x faster than before.
Overall, UnitTests/Vector/multiplies.c is now 2.45x faster with LLVM than with
GCC.
Remove the 'integer multiplies' todo from the README file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 72dd9bdcc57a71d7e9a6f3e68ca1a35ad437a980 |
|
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Lower v8i16 multiply into this code:
li r5, lo16(LCPI1_0)
lis r6, ha16(LCPI1_0)
lvx v4, r6, r5
vmulouh v5, v3, v2
vmuleuh v2, v3, v2
vperm v2, v2, v5, v4
where v4 is:
LCPI1_0: ; <16 x ubyte>
.byte 2
.byte 3
.byte 18
.byte 19
.byte 6
.byte 7
.byte 22
.byte 23
.byte 10
.byte 11
.byte 26
.byte 27
.byte 14
.byte 15
.byte 30
.byte 31
This is 5.07x faster on the G5 (measured) than lowering to scalar code +
loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e7c768ea24027938b52abd6ee94755b6d17f3da3 |
|
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Custom lower v4i32 multiplies into a cute sequence, instead of having legalize
scalarize the sequence into 4 mullw's and a bunch of load/store traffic.
This speeds up v4i32 multiplies 4.1x (measured) on a G5. This implements
PowerPC/vec_mul.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| dbce85dedf5d37794cf5237a78f609dda6b6608d |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make sure to check splats of every constant we can, handle splat(31) by
being a bit more clever, add support for odd splats from -31 to -17.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bdd558cd94a816df83526ab5e5d309f3fc0e210a |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Teach the ppc backend to use rol and vsldoi to generate splatted constants.
This implements vec_constants.ll:test_vsldoi and test_rol
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6876e66e5dbab2847f10ca89a75964fabda4489c |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make some code more general, adding support for constant formation of several
new patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c408382ecade09f66343b084fa0ab437781de593 |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Learn how to make odd splatted constants in range [17,29]. This implements
PowerPC/vec_constants.ll:test_29.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27752 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4a998b9ca8372038ac92ea6057290c2cad73f988 |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Pull some code out into a helper function.
Effeciently codegen even splats in the range [-32,30].
This allows us to codegen <30,30,30,30> as:
vspltisw v0, 15
vadduwm v2, v0, v0
instead of as a cp load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5913810b8286191053853b7495f324e091ab208f |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement a TODO: for any shuffle that can be viewed as a v4[if]32 shuffle,
if it can be implemented in 3 or fewer discrete altivec instructions, codegen
it as such. This implements Regression/CodeGen/PowerPC/vec_perf_shuffle.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f3f69decca93d2465957e5ebf1f64b20e2845967 |
|
16-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement a TODO: have the legalizer canonicalize a bunch of operations to
one type (v4i32) so that we don't have to write patterns for each type, and
so that more CSE opportunities are exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b17f1679e3ce2b40fc2141fc50ef3def4bbd00bc |
|
16-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make the BUILD_VECTOR lowering code much more aggressive w.r.t constant vectors.
Remove some done items from the todo list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 730b45694bd910efe0c5c38897854222f74c92bb |
|
16-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a crash when faced with a shuffle vector that has an undef in its mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b097aa9353121cf6713408402022b8843a0f6acc |
|
15-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Allow undef in a shuffle mask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1a635d617aae63a759bc9d8abc6ee4315b9277ea |
|
14-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Move the rest of the PPCTargetLowering::LowerOperation cases out into
separate functions, for simplicity and code clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f1b4708950cb0dc2a0cafb572d5a56d99b8140c0 |
|
14-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Pull the VECTOR_SHUFFLE and BUILD_VECTOR lowering code out into separate
functions, which makes the code much cleaner :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a39d798e0af289956848b8583b2f80d4801656ec |
|
13-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Force non-darwin targets to use a static relo model. This fixes PR734,
tested by CodeGen/Generic/vector.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ac225ca0514b75e29347933d75e86d03ab8a28e1 |
|
12-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add a new way to match vector constants, which make it easier to bang bits of
different types.
Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1. This compiles:
typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
*P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
*P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
*P3 = vec_abs((vector float)*P3);
}
to:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
vspltisw v0, -1
vslw v0, v0, v0
lvx v1, 0, r3
vand v1, v1, v0
stvx v1, 0, r3
lvx v1, 0, r4
vandc v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vandc v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
instead of (with two constant pool entries):
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
li r6, lo16(LCPI1_0)
lis r7, ha16(LCPI1_0)
li r8, lo16(LCPI1_1)
lis r9, ha16(LCPI1_1)
lvx v0, r7, r6
lvx v1, 0, r3
vand v0, v1, v0
stvx v0, 0, r3
lvx v0, r9, r8
lvx v1, 0, r4
vand v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vand v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
GCC produces (with 2 cp entries):
_test:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc00c
mtspr 256,r0
lis r2,ha16(LC0)
lis r9,ha16(LC1)
la r2,lo16(LC0)(r2)
lvx v0,0,r3
lvx v1,0,r5
la r9,lo16(LC1)(r9)
lwz r12,-4(r1)
lvx v12,0,r2
lvx v13,0,r9
vand v0,v0,v12
stvx v0,0,r3
vspltisw v0,-1
vslw v12,v0,v0
vandc v1,v1,v12
stvx v1,0,r5
lvx v0,0,r4
vand v0,v0,v13
stvx v0,0,r4
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e87192a854ff0f2f1904dd9ea282eb36059bb5af |
|
12-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Rename get_VSPLI_elt -> get_VSPLTI_elt
Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively. This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27614 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2b1c3258d68271098172e52d4e1f8424d855025f |
|
12-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Ensure that zero vectors are always v4i32, which forces them to CSE with
each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27609 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bee9836c0f21be0bd5034f60caa9594c3949910d |
|
11-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Vector function results go into V2 according to GCC. The darwin ABI doc
doesn't say where they go :-/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 06c24350a92dff027cf1b4ddb91704cb82d976ae |
|
11-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Move some return-handling code from lowerarguments to the ISD::RET handling stuff.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a1d95e16df0949fcd33b1ee938a4791dac6f6cad |
|
09-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
properly mark vector selects as expanded to select_cc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27544 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 710ff32983ca919fa0da14e077450b6a7654274f |
|
09-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add VRRC select support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27543 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 79d9a881651689a3814e2d471ba4ab0ff37a4ca8 |
|
08-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a
constant pool load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 140a58f9dfda30dbb80edd3da1b5632c178f7efc |
|
08-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Change the interface to the predicate that determines if vsplti* can be used.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 90217999bdb00fdb1e6d7ee98f75fca8930b2ba5 |
|
07-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make sure to return the result in the right type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f24380e78ecc8a2db1b2116867d878b1e7c6f6ed |
|
07-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Match vpku[hw]um(x,x).
Convert vsldoi(x,x) to work the same way other (x,x) cases work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| caad163496a3ad207a75009f4ad16bae1b1527ae |
|
07-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for matching vmrg(x,x) patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27463 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 116cc48e30b9c307bf3eec29c890b4ba25cd18db |
|
06-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Pattern match vmrg* instructions, which are now lowered by the CFE into shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d0608e191ff9c00af68985f246410c219d1bec57 |
|
06-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to
lower it and LLVM to have one fewer intrinsic. This implements
CodeGen/PowerPC/vec_shuffle.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ddb739e5ea6ccf6fa4f4e2a23e3da550868efaa1 |
|
06-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into
vperm with a perm mask lvx'd from the constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9b42bdd7bced1d31d309dca2932d0a063ea6c863 |
|
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/PowerPC/2006-04-05-splat-ish.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 278158b4877c64b741fd37b2eb9ca1bdbc2eb3d7 |
|
05-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27433 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 098e699f21a532d37b1ad44bb1bc24a87b3f9962 |
|
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7ff7e674580adad7a5bccdbd74cf9c9f05e46d0f |
|
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Ask legalize to promote all vector shuffles to be v16i8 instead of having to
handle all 4 PPC vector types. This simplifies the matching code and allows
us to eliminate a bunch of patterns. This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b68314480d693f2d431c9d1748f4c8c084f3e5f5 |
|
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Revert accidentally committed hunks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27386 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 01cae0799dd4a43c02edc3b5e08e9010ac4ae459 |
|
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bbe77de450ef36b4f83cc3b57705a9758adbd925 |
|
02-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Inform the dag combiner that the predicate compares only return a low bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 541f91b17c33712e2c92f02916082832e6d73c46 |
|
02-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into
"vspltisb v0, 8" instead of a constant pool load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e3fea5a1c12c668ae659a9f68c2d9c711607d8fd |
|
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Rearrange code a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 32a988a095ac93f54ca058bbeb7561f694c66b07 |
|
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add, sub and shuffle are legal for all vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 33497cc99210b45eede30b35909929eebe06d734 |
|
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
note to self: *save* file, then check it in
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4468c224586ba0f75e17ed7520a39a30e8caf636 |
|
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Implement an item from the readme, folding vcmp/vcmp. instructions with
identical instructions into a single instruction. For example, for:
void test(vector float *x, vector float *y, int *P) {
int v = vec_any_out(*x, *y);
*x = (vector float)vec_cmpb(*x, *y);
*P = v;
}
we now generate:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v0, v1, v0
mfcr r4, 2
stvx v0, 0, r3
rlwinm r3, r4, 27, 31, 31
xori r3, r3, 1
stw r3, 0(r5)
mtspr 256, r2
blr
instead of:
_test:
mfspr r2, 256
oris r6, r2, 57344
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v2, v1, v0
mfcr r4, 2
*** vcmpbfp v0, v1, v0
rlwinm r4, r4, 27, 31, 31
stvx v0, 0, r3
xori r3, r4, 1
stw r3, 0(r5)
mtspr 256, r2
blr
Testcase here: CodeGen/PowerPC/vcmp-fold.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a17b1557ad705c56c41624e6841e19093ed31f21 |
|
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Lower vector compares to VCMP nodes, just like we lower vector comparison
predicates to VCMPo nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 36f4b0da9d71b06fce6277be2d9594fafdcb26e0 |
|
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Mark INSERT_VECTOR_ELT as expand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 98e70cc124a1b522611dfc61e085bc755b5616c1 |
|
28-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Add a few more altivec intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7f20b13518b3e45b1c594d3faac3b649571d48d8 |
|
28-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Use normal lvx for scalar_to_vector instead of lve*x. They do the exact
same thing and we have a dag node for the former.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 48b61a729df6576c8833a83893d4086bddff69a5 |
|
28-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f15485a8d0dff5f720b7ad27346129ac5c3ec503 |
|
27-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
SelectionDAGISel can now natively handle Switch instructions, in the same
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6d92caddc4aa5fc946b294259e00cc35536e61e8 |
|
26-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Codegen vector predicate compares.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5b6a01b59c570a32baeab52f7080e6bf1739926a |
|
26-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8d052bc711f1f451e79a2923829d2590d2951601 |
|
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add some basic patterns for other datatypes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9c61dcf1aaf275a1733b6785c54d34eda5426ae1 |
|
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Codegen things like:
<int -1, int -1, int -1, int -1>
and
<int 65537, int 65537, int 65537, int 65537>
Using things like:
vspltisb v0, -1
and:
vspltish v0, 1
instead of using constant pool loads.
This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7fbcef7102732769e2dab1d37f68166b2868c963 |
|
24-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Disable the i32->float G5 optimization. It is unsafe, as documented in the
comment.
This fixes 177.mesa, and McCat/09-vor with the td scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 64b3a08bc696b2ef8733d72ce81e49be175cbbff |
|
24-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add support for using vxor to build zero vectors. This implements
Regression/CodeGen/PowerPC/vec_zero.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ecfe55e65b6a72fddd543c42f2e2df4c96c647ba |
|
22-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9b3bd467d02e73a02afed6d50aaaa149a6a69701 |
|
21-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 23baa1b3106993bc9e8a5807d8b1f9e486bdf845 |
|
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
remove dead variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bd83afd3cdaa89b8a378e92518a5aec7dc7f46c5 |
|
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
figuring these out! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| dd4d2d0e4086905d85bc3011c2de78822d873d83 |
|
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for generating vspltw, instead of a vperm instruction with a
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 88a99ef7cc69febf4e9feb89a087fd40d74c47a4 |
|
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ef819f8fbb68793cc21396fcc1563ec481dacb2f |
|
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
fix duplicate definition errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f1d0b2bedaa065972a5ba17259055c1176cd1497 |
|
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26887 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b2177b9405e43a66bd5e76dfeed1b40aaedd9271 |
|
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Custom lower SCALAR_TO_VECTOR into lve*x.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ab515b09bfba19c671aa2f8635d595552876189d |
|
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
PPC doesn't have SCALAR_TO_VECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a064d28843b425905ed981e693b7730a183ee31b |
|
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
rename these nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 81e8097377529dc3b666f33bb525c49cfbac3f51 |
|
17-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c4c6257c1a154279bf10e9498d46d6c1793dbaa7 |
|
14-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9601a86a644fa036168ff173d3539550b2e9206e |
|
05-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
implement copysign as a native op if they have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5126984b1da4bda0e93961da07e883699f1f2d57 |
|
01-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Compile this:
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8c13d0a5734a2f9d2b1c3870732cafffb20e3a55 |
|
01-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d30bf01e9064a668eaa896a3e9c79d8f0290b6a7 |
|
01-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Vector op lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4c1aa866578f7a358407a22fe55b454f52a24325 |
|
22-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Added option -relocation-model to set relocation model. Valid values include static, pic,
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1efa40f6a4b561cf8f80fe018684236010645cd0 |
|
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
split register class handling from explicit physreg handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4217ca8dc175f7268a4335c8406dedd901e8e631 |
|
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Updates to match change of getRegForInlineAsmConstraint prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d2ee218b499fcd364aae7da031819b738f009cd1 |
|
18-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Moved PICEnabled to include/llvm/Target/TargetOptions.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 45b3976db7f20abe99035962596698008a60033f |
|
13-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Switch to using getCALLSEQ_START instead of using our own creation calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ad3bc8d8add8204195aeb5106036eb7992541bdb |
|
07-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Implement getConstraintType for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 763317de1bda41581b12915b31ba06c2e16450fe |
|
07-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Add the simple PPC integer constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 750ac1bdfa6f09bddfd9efce1d6360dde8fa74c0 |
|
01-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix some of the stuff in the PPC README file, and clean up legalization
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b8973bd8f50d7321635e1e07b81a880a0828d185 |
|
31-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Allow the specification of explicit alignments for constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ddc787dfdc75fb2d78eb3e5793ca0f417ad74fd3 |
|
31-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
add info about the inline asm register constraints for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4477590ef64796e4716f7322d8b2d1cffbaadfa1 |
|
31-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Codegen
bool %test(int %X) {
%Y = seteq int %X, 13
ret bool %Y
}
as
_test:
addi r2, r3, -13
cntlzw r2, r2
srwi r3, r2, 5
blr
rather than
_test:
cmpwi cr7, r3, 13
mfcr r2
rlwinm r3, r2, 31, 31, 31
blr
This has very little effect on most code, but speeds up analyzer 23% and
mason 11%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 37dd6f1b79bd888cb88ced7e5ce5a8ebc7aa44e2 |
|
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Functions that are lazily streamed in from the .bc file are *not* external.
This fixes llvm-test/SingleSource/UnitTests/2006-01-29-SimpleIndirectCall.c
and PR704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25793 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d9b55dd21ae4168d131b344d53eb19ac4468b23c |
|
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Now that OpActions is big enough, we can specify actions for vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25784 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3fd327fe7fdcc9cfdf0ecc2e069120672c37c0c9 |
|
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
disable this for now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ec4a0c7c6bd689572d8f432950867e6ee9d777f4 |
|
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Request expansion of ConstantVec nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a54aa94197d5af9a72c0de422a58e938da80b2a4 |
|
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Targets all now request ConstantFP to be legalized into TargetConstantFP.
'fpimm' in .td files is now TargetConstantFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e00ebf0acaa47a9aa8bfeba025f281432c4e9957 |
|
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in my elimination of ISD::CALL this morning. PPC now has to
provide the expansion for i64 calls itself
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 281b55ebeccd3f0d723888c1bb9ec6e476f708f1 |
|
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Use PPCISD::CALL instead of ISD::CALL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bba534dc6676fa6a91dfb4492b30faf67bd22abe |
|
27-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Make llvm.frame/returnaddr not crash on ppc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ee625573b5b39b91441fc6ea23f3ba415abdc71f |
|
27-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0577a22c678bd5e31047e6b8038c6917202271ee |
|
25-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Set SchedulingForLatency to be the default scheduling preference for all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25607 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| acc398c195a697795bff3245943d104eb19192b9 |
|
25-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
First part of bug 680:
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7558b0e80c058c148ef9f45220bbbe6bc8a146dd |
|
25-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Default scheduling preference is SchedulingForLatency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bc38dbfd9b88c021378c647f6c169f4f76a775da |
|
18-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Don't assert on 'select_cc SETUO'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b22c08b8082cdf0026a8d429f37e8c16a1ca8caf |
|
15-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d88fc03602947b5baa35c8b09fe8bcfa2b4a03c1 |
|
14-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
bswap implementation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| cadd7420f9e705735b794e61cd24aab16ce2fa18 |
|
13-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
implement stacksave/stackrestore on PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| b99329e8a0ec3b5a0004dd649e3546939f5c31e7 |
|
13-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
expand unsupported stacksave/stackrestore nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 35ef913ec21de0f4f1b39c811b4335438717a9b8 |
|
11-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Add bswap, rotl, and rotr nodes
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a243db8c41bd8ace6e002c9e1fdcdc7256ebf677 |
|
11-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix calls that need to store values in stack slots, to not copy the stack
pointer. This allows us to emit stuff like this:
li r10, 0
stw r10, 56(r1)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
instead of this:
or r2, r1, r1 ;; Extraneous copy.
li r10, 0
stw r10, 56(r2)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
wowness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 413b979fe4b3482f347fc7b613d7dcda81e34874 |
|
11-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Dead FP arguments still use an incoming FP reg. This fixes
Regression/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll, which was
distilled from a miscompilation in 252.eon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25217 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| da6d20f0c15205923cb2c3ef4bf9b5d77de88881 |
|
10-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Give PPCISD:: nodes legible names in dumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a35ef6350defdc09eb912c52603cffa6afbd78e2 |
|
06-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
linkonce symbols have an extra indirection, just like weak ones do. This fixes
Prolangs-C++/family and Prolangs-C++/primes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e0bce71c42a021d897b51425dab16841a0ebc5bd |
|
05-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Had expand logic backward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| abf6d1784b2d4bbcb7d20ab64881f77d755059f6 |
|
05-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Added initial support for DEBUG_LABEL allowing debug specific labels to be
inserted in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1166bf3f4ca4d2bf9509ec2f243eb9c41360364b |
|
30-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove a fixme
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 50fb3c498601a84e0d82d7bab3e28c820dd64598 |
|
24-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix one of the things in the todo file, and get a bit closer to folding
constant offsets from statics into the address arithmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 53e884587bd4b56c14dc39600eb655e77ae7b905 |
|
23-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
make sure bit_converts are expanded
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1b95e0ba92a08dd90c9f06fe175d7a62b055b5f3 |
|
23-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Simplify some code by using BIT_CONVERT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9e4dd9dfc97f3930f58ca6e47bebbd8eb5cdd8a1 |
|
20-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Pattern-match return. Includes gross hack!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7fd1edd32e9a6782dbcd00818bbdaf82f14284a1 |
|
20-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Convert load/store over to being pattern matched
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 28a6b02626c29b1fe9bb16c14c193549fab4cab8 |
|
10-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for TargetConstantPool nodes to the dag isel emitter, and use
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4172b10ca1adfc1026428e5f522aaab98bd939ad |
|
06-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Use new PPC-specific nodes to represent shifts which require the 6-bit
amount handling that PPC provides. These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits. This fixes a miscompilation of crafty with
the new front-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24615 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 80720a921987e36c83236d375919172afd20d79c |
|
30-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24547 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 425a96971f0b0298222a51b5692aacaa9229dce3 |
|
29-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Hook up one type, v4f32, to the VR RegisterClass for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f73bae1b73211c77238f64029ee2bec7ce90bba2 |
|
29-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
No targets support line number info yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1d05cb47a94bb5639b690519c6027447791e06f7 |
|
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
add an option to generate completely non-pic code, corresponding to what
gcc -static produces on PPC. This is used for building kexts and other things.
With this, materializing the address of a global looks like:
lis r2, ha16(L_H$non_lazy_ptr)
la r3, lo16(L_H$non_lazy_ptr)(r2)
we're still emitting stubs for functions, which is wrong. That is next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1df747867cc1e7d37447bc3072e55e380c6720e8 |
|
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug that resistor on IRC hit where we tried to create token factor
nodes of load results, not of their chain results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 3eef4e377cad01d5fbef2d67a12fe96171e0d860 |
|
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Enable global address legalization, fixing a todo and allowing the removal
of some code. This exposes the implicit load from the stubs to the DAG, allowing
them to be optimized by the dag combiner. It also moves darwin specific stuff
out of the isel into the legalizer, and allows more to be moved to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1566613ca4aecaf0143b41c97ae3b3be80660c56 |
|
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Use the right accessor to create this node
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 860e8862c1fbd3b261da4a64a8c0096f9f373681 |
|
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Add an initial hack at legalizing GlobalAddress into the appropriate nodes
on Darwin to remove smarts from the isel. This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file. However, we can currently emit stuff like
this: :)
li r2, lo16(L_x$non_lazy_ptr)
lis r3, ha16(L_x$non_lazy_ptr)
lwzx r2, r3, r2
The obvious improvements will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2823b3e70ee7a5ed7482c45c503659a16a879a61 |
|
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
When lowering direct calls, lower them to use a targetglobaladress directly
instead of a globaladdress. This has no effect on the generated code at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24386 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 85fd97dc8810ac16197594304f9f985a13466d19 |
|
26-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Fix an assert compiling MallocBench/gs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ae749a9bb5aa4e350041e275ea26f4cc52197392 |
|
26-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Correctly Expand or Promote FP_TO_UINT based on the capabilities of the
machine. This allows us to generate great code for i32 FP_TO_UINT now on
targets with 64 bit extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23993 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| eb255f2b83cd87902309df1ce590f02178aabc65 |
|
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Expose the fextend on the DAG instead of doing it in the matcher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 405e3ecb563f21e7b4ee30f0de57821f3eb91219 |
|
21-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Invert the TargetLowering flag that controls divide by consant expansion.
Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6957523b9ddc6e85aede47a107502043fd1a3b2d |
|
20-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Move the target constant divide optimization up into the dag combiner, so
that the nodes can be folded with other nodes, and we can not duplicate
code in every backend. Alpha will probably want this too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 4a95945fa5aa431110f50092f4a45d24772a553b |
|
19-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the ability to lower return instructions to TargetLowering. This
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 9d2b817fcbad2ee615be323c38f1ed66d81964dc |
|
18-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Do the right thing and enable 64 bit regs under the control of a subtarget
option. Currently the only way to enable this is to specify the
64bitregs mattr flag. It is never enabled by default on any config yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1d9d7427c4a4e3c7bdcfd1f725447f355e509c20 |
|
18-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
purely mechanical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 21e463b2bf864671a87ebe386cb100ef9349a540 |
|
16-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
More PPC32 -> PPC changes, as well as merging some classes that were
redundant after the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 16e71f2f70811c69c56052dd146324fe20e31db5 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PPC32*.h to PPC*.h
This completes the grand PPC file renaming
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7c0d664c2118d1c5da50b137856d4a6b1c962ec3 |
|
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
fix an f32/f64 type mismatch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 919c032fa4511468aadc6f50d6ed9c50890710b3 |
|
01-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 615c2d0920862ae7d4d766ee3da660ecf2197308 |
|
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| d145a61f8f581cfe7dc7abb023a3b1ab534606c7 |
|
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Darwin, like many BSD systems, has a setjmp/longjmp which saves the signal mask
on setjmp calls and restores it on longjmp calls (both of which require syscalls).
This makes the calls REALLY slow. Use _setjmp/_longjmp instead. This speeds up
hexxagon from 120.31s to 15.68s: from 5.53x slower than GCC to 28% faster than GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7b738342f0b27b9f7fdcf93f08ebb99fa510ae09 |
|
13-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Change the arg lowering code to use copyfromreg from vregs associated
with incoming arguments instead of the pregs themselves. This fixes
the scheduler from causing problems by moving a copyfromreg for an argument
to after a select_cc node (now it can, and bad things won't happen).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 31262ce53d8ce1558fb03b41d0a1afab840e5130 |
|
13-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Remove some dead vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e6ec9f20c9df6387b68874e4c49035d3c9c5527f |
|
10-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
PowerPC cannot truncstore i1 natively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c09eeec0ebc378644bafd04916e5efafa7d98152 |
|
07-Sep-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when we
are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.
This speeds up 189.lucas from 81.99 to 32.64 seconds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23250 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 1e9de3ed2db440fac99e5cc85b7d98b0a23a2727 |
|
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Decouple fsqrt from gpul optimizations, implementing fsqrt.ll.
Remove the -enable-gpopt option which is subsumed by feature flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f505949580e1a4af3d49cb5dcff9fd78f31a00fb |
|
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Restore this patch now that the latent bug has been fixed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23209 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 5b3224fe7ecafd486b75ebfa113a95783112ec3d |
|
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Revert the previous patch which causes a mysterious regression in toast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 2a00daac5895879afdf14adf936cd93deaadbb99 |
|
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Implement small-arguments.ll:test3 by teaching the DAG optimizer that
the results of calls to functions returning small values are properly
sign/zero extended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23198 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| f76053269ecc6c7bd3d0b1e90ebdd0cef1bb2bdc |
|
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Move FCTIWZ handling out of the instruction selectors and into legalization,
getting them out of the business of making stack slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| bc11c3482c2d38af514031c38c417f106b8f3c91 |
|
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Move SHL,SHR i64 -> legalizer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| eb9b62e35e16f90ab1f641e9ba8d077bd591ff0b |
|
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
lower sra_parts on the dag, implementing it for the dag isel, and exposing
the ops to dag optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 49296f1f48251945635fcebf562331b5ca5eb9c5 |
|
31-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Enable generation of AssertSext and AssertZext in the PPC backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 6de08f4377302cb73ca6a378410889be423af20f |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in my patch for legalizing to fsel. It cannot handle seteq/setne,
which I failed to include when I moved the code over. This fixes
MallocBench/gs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 915fb302b103cc53b14693a8dad7e2a83d3037d3 |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix some really strange indentation that xcode likes to use.
no xcode, this is not right:
if (!foo) break;
X;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23138 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8a2d3ca7dff8f37ee0f1fc0042f47c194045183d |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement SELECT_CC fully for the DAG->DAG isel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0bbea954331b8f08afa5b094dfb0841829c70eaa |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Make fsel emission work with both the pattern and dag-dag selectors, by
giving it a non-instruction opcode. The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 0b1e4e508b1fb76408a2c6a434b0f4df3cad3578 |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement the other half of the select_cc -> fsel lowering, which handles
when the RHS of the comparison is 0.0. Turn this on by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| e4bc9ea0a560d8a0ba42f5a2da617e1f1f834710 |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add initial support for converting select_cc -> fsel in the legalizer
instead of in the backend. This currently handles fsel cases with registers,
but doesn't have the 0.0 and -0.0 optimization enabled yet.
Once this is finished, special hack for fp immediates can go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| c8e27db5c58abc2c2aa1b60d6a58aef251766ee7 |
|
25-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove option to make SetCC illegal on PowerPC after long discussion with
Chris. This will be accomplished through correctly modeling CR's and
subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 8ca5693c517054c89a557391267fe305baa3407e |
|
23-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Ack, typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a50d53e5ef9f2ef9866937511075f873e31d7c1d |
|
23-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add an option to make SetCC illegal as a beta option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| ad23c9d4f256469881e4e6ca9e6fd4605e12ec36 |
|
17-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
Make UINT_TO_FP and SINT_TO_FP use generic expansion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22815 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| a8cd01524f08d5e7aef84b6aed8745b3f618a2a3 |
|
16-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
updates for changes in nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7cbd525ba85ebe440d15fa359ec940e404d14906 |
|
16-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty
fixme from the PowerPC backend. Emit slightly better code for legalizing
select_cc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|
| 7c5a3d390a463fb50a6eee7ae3174817925e6d28 |
|
16-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Pull the LLVM -> DAG lowering code out of the pattern selector so that it
can be shared with the DAG->DAG selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22799 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
|