PPCISelLowering.cpp revision 3ce990dc051622755afc22b55f95954c5a19e779
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/Analysis/ScalarEvolutionExpressions.h" 22#include "llvm/CodeGen/CallingConvLower.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Constants.h" 29#include "llvm/Function.h" 30#include "llvm/Intrinsics.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/Target/TargetOptions.h" 33#include "llvm/Support/CommandLine.h" 34using namespace llvm; 35 36static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 37cl::desc("enable preincrement load/store generation on PPC (experimental)"), 38 cl::Hidden); 39 40PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 41 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 42 43 setPow2DivIsCheap(); 44 45 // Use _setjmp/_longjmp instead of setjmp/longjmp. 46 setUseUnderscoreSetJmp(true); 47 setUseUnderscoreLongJmp(true); 48 49 // Set up the register classes. 50 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 51 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 52 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 53 54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 55 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 56 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 57 58 // PowerPC does not have truncstore for i1. 59 setStoreXAction(MVT::i1, Promote); 60 61 // PowerPC has pre-inc load and store's. 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 72 73 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 74 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 75 76 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) 77 setConvertAction(MVT::ppcf128, MVT::f64, Expand); 78 setConvertAction(MVT::ppcf128, MVT::f32, Expand); 79 80 // PowerPC has no intrinsics for these particular operations 81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 82 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 84 85 // PowerPC has no SREM/UREM instructions 86 setOperationAction(ISD::SREM, MVT::i32, Expand); 87 setOperationAction(ISD::UREM, MVT::i32, Expand); 88 setOperationAction(ISD::SREM, MVT::i64, Expand); 89 setOperationAction(ISD::UREM, MVT::i64, Expand); 90 91 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 92 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 93 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 94 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 95 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 96 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 97 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 98 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 99 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 100 101 // We don't support sin/cos/sqrt/fmod 102 setOperationAction(ISD::FSIN , MVT::f64, Expand); 103 setOperationAction(ISD::FCOS , MVT::f64, Expand); 104 setOperationAction(ISD::FREM , MVT::f64, Expand); 105 setOperationAction(ISD::FSIN , MVT::f32, Expand); 106 setOperationAction(ISD::FCOS , MVT::f32, Expand); 107 setOperationAction(ISD::FREM , MVT::f32, Expand); 108 109 // If we're enabling GP optimizations, use hardware square root 110 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 111 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 112 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 113 } 114 115 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 116 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 117 118 // PowerPC does not have BSWAP, CTPOP or CTTZ 119 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 120 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 121 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 122 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 123 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 124 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 125 126 // PowerPC does not have ROTR 127 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 128 129 // PowerPC does not have Select 130 setOperationAction(ISD::SELECT, MVT::i32, Expand); 131 setOperationAction(ISD::SELECT, MVT::i64, Expand); 132 setOperationAction(ISD::SELECT, MVT::f32, Expand); 133 setOperationAction(ISD::SELECT, MVT::f64, Expand); 134 135 // PowerPC wants to turn select_cc of FP into fsel when possible. 136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 138 139 // PowerPC wants to optimize integer setcc a bit 140 setOperationAction(ISD::SETCC, MVT::i32, Custom); 141 142 // PowerPC does not have BRCOND which requires SetCC 143 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 144 145 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 146 147 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 148 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 149 150 // PowerPC does not have [U|S]INT_TO_FP 151 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 152 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 153 154 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 155 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 156 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 157 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 158 159 // We cannot sextinreg(i1). Expand to shifts. 160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 161 162 // Support label based line numbers. 163 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 164 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 165 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) { 166 setOperationAction(ISD::LABEL, MVT::Other, Expand); 167 } else { 168 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 169 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 170 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 171 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 172 } 173 174 // We want to legalize GlobalAddress and ConstantPool nodes into the 175 // appropriate instructions to materialize the address. 176 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 177 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 178 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 179 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 180 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 181 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 182 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 183 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 184 185 // RET must be custom lowered, to meet ABI requirements 186 setOperationAction(ISD::RET , MVT::Other, Custom); 187 188 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 189 setOperationAction(ISD::VASTART , MVT::Other, Custom); 190 191 // VAARG is custom lowered with ELF 32 ABI 192 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) 193 setOperationAction(ISD::VAARG, MVT::Other, Custom); 194 else 195 setOperationAction(ISD::VAARG, MVT::Other, Expand); 196 197 // Use the default implementation. 198 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 199 setOperationAction(ISD::VAEND , MVT::Other, Expand); 200 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 201 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 202 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 203 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 204 205 // We want to custom lower some of our intrinsics. 206 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 207 208 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 209 // They also have instructions for converting between i64 and fp. 210 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 211 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 212 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 213 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 214 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 215 216 // FIXME: disable this lowered code. This generates 64-bit register values, 217 // and we don't model the fact that the top part is clobbered by calls. We 218 // need to flag these together so that the value isn't live across a call. 219 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 220 221 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 222 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 223 } else { 224 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 226 } 227 228 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 229 // 64 bit PowerPC implementations can support i64 types directly 230 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 231 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 232 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 233 } else { 234 // 32 bit PowerPC wants to expand i64 shifts itself. 235 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 236 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 237 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 238 } 239 240 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 241 // First set operation action for all vector types to expand. Then we 242 // will selectively turn on ones that can be effectively codegen'd. 243 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 244 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 245 // add/sub are legal for all supported vector VT's. 246 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 247 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 248 249 // We promote all shuffles to v16i8. 250 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 251 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 252 253 // We promote all non-typed operations to v4i32. 254 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 255 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 256 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 257 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 258 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 259 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 260 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 261 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 262 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 263 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 264 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 265 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 266 267 // No other operations are legal. 268 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 269 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 270 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 271 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 272 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 273 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 274 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); 275 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 276 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 277 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 278 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); 279 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); 280 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); 281 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); 282 283 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 284 } 285 286 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 287 // with merges, splats, etc. 288 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 289 290 setOperationAction(ISD::AND , MVT::v4i32, Legal); 291 setOperationAction(ISD::OR , MVT::v4i32, Legal); 292 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 293 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 294 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 295 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 296 297 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 298 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 299 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 300 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 301 302 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 303 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 304 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 305 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 306 307 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 308 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 309 310 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 311 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 312 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 313 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 314 } 315 316 setSetCCResultType(MVT::i32); 317 setShiftAmountType(MVT::i32); 318 setSetCCResultContents(ZeroOrOneSetCCResult); 319 320 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 321 setStackPointerRegisterToSaveRestore(PPC::X1); 322 setExceptionPointerRegister(PPC::X3); 323 setExceptionSelectorRegister(PPC::X4); 324 } else { 325 setStackPointerRegisterToSaveRestore(PPC::R1); 326 setExceptionPointerRegister(PPC::R3); 327 setExceptionSelectorRegister(PPC::R4); 328 } 329 330 // We have target-specific dag combine patterns for the following nodes: 331 setTargetDAGCombine(ISD::SINT_TO_FP); 332 setTargetDAGCombine(ISD::STORE); 333 setTargetDAGCombine(ISD::BR_CC); 334 setTargetDAGCombine(ISD::BSWAP); 335 336 computeRegisterProperties(); 337} 338 339const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 340 switch (Opcode) { 341 default: return 0; 342 case PPCISD::FSEL: return "PPCISD::FSEL"; 343 case PPCISD::FCFID: return "PPCISD::FCFID"; 344 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 345 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 346 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 347 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 348 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 349 case PPCISD::VPERM: return "PPCISD::VPERM"; 350 case PPCISD::Hi: return "PPCISD::Hi"; 351 case PPCISD::Lo: return "PPCISD::Lo"; 352 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 353 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 354 case PPCISD::SRL: return "PPCISD::SRL"; 355 case PPCISD::SRA: return "PPCISD::SRA"; 356 case PPCISD::SHL: return "PPCISD::SHL"; 357 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 358 case PPCISD::STD_32: return "PPCISD::STD_32"; 359 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 360 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 361 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 362 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 363 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 364 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 365 case PPCISD::MFCR: return "PPCISD::MFCR"; 366 case PPCISD::VCMP: return "PPCISD::VCMP"; 367 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 368 case PPCISD::LBRX: return "PPCISD::LBRX"; 369 case PPCISD::STBRX: return "PPCISD::STBRX"; 370 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 371 } 372} 373 374//===----------------------------------------------------------------------===// 375// Node matching predicates, for use by the tblgen matching code. 376//===----------------------------------------------------------------------===// 377 378/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 379static bool isFloatingPointZero(SDOperand Op) { 380 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 381 return CFP->getValueAPF().isZero(); 382 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 383 // Maybe this has already been legalized into the constant pool? 384 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 385 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 386 return CFP->getValueAPF().isZero(); 387 } 388 return false; 389} 390 391/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 392/// true if Op is undef or if it matches the specified value. 393static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 394 return Op.getOpcode() == ISD::UNDEF || 395 cast<ConstantSDNode>(Op)->getValue() == Val; 396} 397 398/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 399/// VPKUHUM instruction. 400bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 401 if (!isUnary) { 402 for (unsigned i = 0; i != 16; ++i) 403 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 404 return false; 405 } else { 406 for (unsigned i = 0; i != 8; ++i) 407 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 408 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 409 return false; 410 } 411 return true; 412} 413 414/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 415/// VPKUWUM instruction. 416bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 417 if (!isUnary) { 418 for (unsigned i = 0; i != 16; i += 2) 419 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 420 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 421 return false; 422 } else { 423 for (unsigned i = 0; i != 8; i += 2) 424 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 425 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 426 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 427 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 428 return false; 429 } 430 return true; 431} 432 433/// isVMerge - Common function, used to match vmrg* shuffles. 434/// 435static bool isVMerge(SDNode *N, unsigned UnitSize, 436 unsigned LHSStart, unsigned RHSStart) { 437 assert(N->getOpcode() == ISD::BUILD_VECTOR && 438 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 439 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 440 "Unsupported merge size!"); 441 442 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 443 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 444 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 445 LHSStart+j+i*UnitSize) || 446 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 447 RHSStart+j+i*UnitSize)) 448 return false; 449 } 450 return true; 451} 452 453/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 454/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 455bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 456 if (!isUnary) 457 return isVMerge(N, UnitSize, 8, 24); 458 return isVMerge(N, UnitSize, 8, 8); 459} 460 461/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 462/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 463bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 464 if (!isUnary) 465 return isVMerge(N, UnitSize, 0, 16); 466 return isVMerge(N, UnitSize, 0, 0); 467} 468 469 470/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 471/// amount, otherwise return -1. 472int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 473 assert(N->getOpcode() == ISD::BUILD_VECTOR && 474 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 475 // Find the first non-undef value in the shuffle mask. 476 unsigned i; 477 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 478 /*search*/; 479 480 if (i == 16) return -1; // all undef. 481 482 // Otherwise, check to see if the rest of the elements are consequtively 483 // numbered from this value. 484 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 485 if (ShiftAmt < i) return -1; 486 ShiftAmt -= i; 487 488 if (!isUnary) { 489 // Check the rest of the elements to see if they are consequtive. 490 for (++i; i != 16; ++i) 491 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 492 return -1; 493 } else { 494 // Check the rest of the elements to see if they are consequtive. 495 for (++i; i != 16; ++i) 496 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 497 return -1; 498 } 499 500 return ShiftAmt; 501} 502 503/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 504/// specifies a splat of a single element that is suitable for input to 505/// VSPLTB/VSPLTH/VSPLTW. 506bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 507 assert(N->getOpcode() == ISD::BUILD_VECTOR && 508 N->getNumOperands() == 16 && 509 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 510 511 // This is a splat operation if each element of the permute is the same, and 512 // if the value doesn't reference the second vector. 513 unsigned ElementBase = 0; 514 SDOperand Elt = N->getOperand(0); 515 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 516 ElementBase = EltV->getValue(); 517 else 518 return false; // FIXME: Handle UNDEF elements too! 519 520 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 521 return false; 522 523 // Check that they are consequtive. 524 for (unsigned i = 1; i != EltSize; ++i) { 525 if (!isa<ConstantSDNode>(N->getOperand(i)) || 526 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 527 return false; 528 } 529 530 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 531 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 532 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 533 assert(isa<ConstantSDNode>(N->getOperand(i)) && 534 "Invalid VECTOR_SHUFFLE mask!"); 535 for (unsigned j = 0; j != EltSize; ++j) 536 if (N->getOperand(i+j) != N->getOperand(j)) 537 return false; 538 } 539 540 return true; 541} 542 543/// isAllNegativeZeroVector - Returns true if all elements of build_vector 544/// are -0.0. 545bool PPC::isAllNegativeZeroVector(SDNode *N) { 546 assert(N->getOpcode() == ISD::BUILD_VECTOR); 547 if (PPC::isSplatShuffleMask(N, N->getNumOperands())) 548 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) 549 return CFP->getValueAPF().isNegZero(); 550 return false; 551} 552 553/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 554/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 555unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 556 assert(isSplatShuffleMask(N, EltSize)); 557 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 558} 559 560/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 561/// by using a vspltis[bhw] instruction of the specified element size, return 562/// the constant being splatted. The ByteSize field indicates the number of 563/// bytes of each element [124] -> [bhw]. 564SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 565 SDOperand OpVal(0, 0); 566 567 // If ByteSize of the splat is bigger than the element size of the 568 // build_vector, then we have a case where we are checking for a splat where 569 // multiple elements of the buildvector are folded together into a single 570 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 571 unsigned EltSize = 16/N->getNumOperands(); 572 if (EltSize < ByteSize) { 573 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 574 SDOperand UniquedVals[4]; 575 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 576 577 // See if all of the elements in the buildvector agree across. 578 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 579 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 580 // If the element isn't a constant, bail fully out. 581 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 582 583 584 if (UniquedVals[i&(Multiple-1)].Val == 0) 585 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 586 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 587 return SDOperand(); // no match. 588 } 589 590 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 591 // either constant or undef values that are identical for each chunk. See 592 // if these chunks can form into a larger vspltis*. 593 594 // Check to see if all of the leading entries are either 0 or -1. If 595 // neither, then this won't fit into the immediate field. 596 bool LeadingZero = true; 597 bool LeadingOnes = true; 598 for (unsigned i = 0; i != Multiple-1; ++i) { 599 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 600 601 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 602 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 603 } 604 // Finally, check the least significant entry. 605 if (LeadingZero) { 606 if (UniquedVals[Multiple-1].Val == 0) 607 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 608 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 609 if (Val < 16) 610 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 611 } 612 if (LeadingOnes) { 613 if (UniquedVals[Multiple-1].Val == 0) 614 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 615 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 616 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 617 return DAG.getTargetConstant(Val, MVT::i32); 618 } 619 620 return SDOperand(); 621 } 622 623 // Check to see if this buildvec has a single non-undef value in its elements. 624 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 625 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 626 if (OpVal.Val == 0) 627 OpVal = N->getOperand(i); 628 else if (OpVal != N->getOperand(i)) 629 return SDOperand(); 630 } 631 632 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 633 634 unsigned ValSizeInBytes = 0; 635 uint64_t Value = 0; 636 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 637 Value = CN->getValue(); 638 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 639 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 640 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 641 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 642 ValSizeInBytes = 4; 643 } 644 645 // If the splat value is larger than the element value, then we can never do 646 // this splat. The only case that we could fit the replicated bits into our 647 // immediate field for would be zero, and we prefer to use vxor for it. 648 if (ValSizeInBytes < ByteSize) return SDOperand(); 649 650 // If the element value is larger than the splat value, cut it in half and 651 // check to see if the two halves are equal. Continue doing this until we 652 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 653 while (ValSizeInBytes > ByteSize) { 654 ValSizeInBytes >>= 1; 655 656 // If the top half equals the bottom half, we're still ok. 657 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 658 (Value & ((1 << (8*ValSizeInBytes))-1))) 659 return SDOperand(); 660 } 661 662 // Properly sign extend the value. 663 int ShAmt = (4-ByteSize)*8; 664 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 665 666 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 667 if (MaskVal == 0) return SDOperand(); 668 669 // Finally, if this value fits in a 5 bit sext field, return it 670 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 671 return DAG.getTargetConstant(MaskVal, MVT::i32); 672 return SDOperand(); 673} 674 675//===----------------------------------------------------------------------===// 676// Addressing Mode Selection 677//===----------------------------------------------------------------------===// 678 679/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 680/// or 64-bit immediate, and if the value can be accurately represented as a 681/// sign extension from a 16-bit value. If so, this returns true and the 682/// immediate. 683static bool isIntS16Immediate(SDNode *N, short &Imm) { 684 if (N->getOpcode() != ISD::Constant) 685 return false; 686 687 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 688 if (N->getValueType(0) == MVT::i32) 689 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 690 else 691 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 692} 693static bool isIntS16Immediate(SDOperand Op, short &Imm) { 694 return isIntS16Immediate(Op.Val, Imm); 695} 696 697 698/// SelectAddressRegReg - Given the specified addressed, check to see if it 699/// can be represented as an indexed [r+r] operation. Returns false if it 700/// can be more efficiently represented with [r+imm]. 701bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, 702 SDOperand &Index, 703 SelectionDAG &DAG) { 704 short imm = 0; 705 if (N.getOpcode() == ISD::ADD) { 706 if (isIntS16Immediate(N.getOperand(1), imm)) 707 return false; // r+i 708 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 709 return false; // r+i 710 711 Base = N.getOperand(0); 712 Index = N.getOperand(1); 713 return true; 714 } else if (N.getOpcode() == ISD::OR) { 715 if (isIntS16Immediate(N.getOperand(1), imm)) 716 return false; // r+i can fold it if we can. 717 718 // If this is an or of disjoint bitfields, we can codegen this as an add 719 // (for better address arithmetic) if the LHS and RHS of the OR are provably 720 // disjoint. 721 uint64_t LHSKnownZero, LHSKnownOne; 722 uint64_t RHSKnownZero, RHSKnownOne; 723 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 724 725 if (LHSKnownZero) { 726 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); 727 // If all of the bits are known zero on the LHS or RHS, the add won't 728 // carry. 729 if ((LHSKnownZero | RHSKnownZero) == ~0U) { 730 Base = N.getOperand(0); 731 Index = N.getOperand(1); 732 return true; 733 } 734 } 735 } 736 737 return false; 738} 739 740/// Returns true if the address N can be represented by a base register plus 741/// a signed 16-bit displacement [r+imm], and if it is not better 742/// represented as reg+reg. 743bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, 744 SDOperand &Base, SelectionDAG &DAG){ 745 // If this can be more profitably realized as r+r, fail. 746 if (SelectAddressRegReg(N, Disp, Base, DAG)) 747 return false; 748 749 if (N.getOpcode() == ISD::ADD) { 750 short imm = 0; 751 if (isIntS16Immediate(N.getOperand(1), imm)) { 752 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 753 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 754 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 755 } else { 756 Base = N.getOperand(0); 757 } 758 return true; // [r+i] 759 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 760 // Match LOAD (ADD (X, Lo(G))). 761 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 762 && "Cannot handle constant offsets yet!"); 763 Disp = N.getOperand(1).getOperand(0); // The global address. 764 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 765 Disp.getOpcode() == ISD::TargetConstantPool || 766 Disp.getOpcode() == ISD::TargetJumpTable); 767 Base = N.getOperand(0); 768 return true; // [&g+r] 769 } 770 } else if (N.getOpcode() == ISD::OR) { 771 short imm = 0; 772 if (isIntS16Immediate(N.getOperand(1), imm)) { 773 // If this is an or of disjoint bitfields, we can codegen this as an add 774 // (for better address arithmetic) if the LHS and RHS of the OR are 775 // provably disjoint. 776 uint64_t LHSKnownZero, LHSKnownOne; 777 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 778 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 779 // If all of the bits are known zero on the LHS or RHS, the add won't 780 // carry. 781 Base = N.getOperand(0); 782 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 783 return true; 784 } 785 } 786 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 787 // Loading from a constant address. 788 789 // If this address fits entirely in a 16-bit sext immediate field, codegen 790 // this as "d, 0" 791 short Imm; 792 if (isIntS16Immediate(CN, Imm)) { 793 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 794 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 795 return true; 796 } 797 798 // Handle 32-bit sext immediates with LIS + addr mode. 799 if (CN->getValueType(0) == MVT::i32 || 800 (int64_t)CN->getValue() == (int)CN->getValue()) { 801 int Addr = (int)CN->getValue(); 802 803 // Otherwise, break this down into an LIS + disp. 804 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 805 806 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 807 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 808 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 809 return true; 810 } 811 } 812 813 Disp = DAG.getTargetConstant(0, getPointerTy()); 814 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 815 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 816 else 817 Base = N; 818 return true; // [r+0] 819} 820 821/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 822/// represented as an indexed [r+r] operation. 823bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, 824 SDOperand &Index, 825 SelectionDAG &DAG) { 826 // Check to see if we can easily represent this as an [r+r] address. This 827 // will fail if it thinks that the address is more profitably represented as 828 // reg+imm, e.g. where imm = 0. 829 if (SelectAddressRegReg(N, Base, Index, DAG)) 830 return true; 831 832 // If the operand is an addition, always emit this as [r+r], since this is 833 // better (for code size, and execution, as the memop does the add for free) 834 // than emitting an explicit add. 835 if (N.getOpcode() == ISD::ADD) { 836 Base = N.getOperand(0); 837 Index = N.getOperand(1); 838 return true; 839 } 840 841 // Otherwise, do it the hard way, using R0 as the base register. 842 Base = DAG.getRegister(PPC::R0, N.getValueType()); 843 Index = N; 844 return true; 845} 846 847/// SelectAddressRegImmShift - Returns true if the address N can be 848/// represented by a base register plus a signed 14-bit displacement 849/// [r+imm*4]. Suitable for use by STD and friends. 850bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, 851 SDOperand &Base, 852 SelectionDAG &DAG) { 853 // If this can be more profitably realized as r+r, fail. 854 if (SelectAddressRegReg(N, Disp, Base, DAG)) 855 return false; 856 857 if (N.getOpcode() == ISD::ADD) { 858 short imm = 0; 859 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 860 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 861 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 862 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 863 } else { 864 Base = N.getOperand(0); 865 } 866 return true; // [r+i] 867 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 868 // Match LOAD (ADD (X, Lo(G))). 869 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 870 && "Cannot handle constant offsets yet!"); 871 Disp = N.getOperand(1).getOperand(0); // The global address. 872 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 873 Disp.getOpcode() == ISD::TargetConstantPool || 874 Disp.getOpcode() == ISD::TargetJumpTable); 875 Base = N.getOperand(0); 876 return true; // [&g+r] 877 } 878 } else if (N.getOpcode() == ISD::OR) { 879 short imm = 0; 880 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 881 // If this is an or of disjoint bitfields, we can codegen this as an add 882 // (for better address arithmetic) if the LHS and RHS of the OR are 883 // provably disjoint. 884 uint64_t LHSKnownZero, LHSKnownOne; 885 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 886 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 887 // If all of the bits are known zero on the LHS or RHS, the add won't 888 // carry. 889 Base = N.getOperand(0); 890 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 891 return true; 892 } 893 } 894 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 895 // Loading from a constant address. Verify low two bits are clear. 896 if ((CN->getValue() & 3) == 0) { 897 // If this address fits entirely in a 14-bit sext immediate field, codegen 898 // this as "d, 0" 899 short Imm; 900 if (isIntS16Immediate(CN, Imm)) { 901 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 902 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 903 return true; 904 } 905 906 // Fold the low-part of 32-bit absolute addresses into addr mode. 907 if (CN->getValueType(0) == MVT::i32 || 908 (int64_t)CN->getValue() == (int)CN->getValue()) { 909 int Addr = (int)CN->getValue(); 910 911 // Otherwise, break this down into an LIS + disp. 912 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 913 914 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 915 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 916 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 917 return true; 918 } 919 } 920 } 921 922 Disp = DAG.getTargetConstant(0, getPointerTy()); 923 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 924 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 925 else 926 Base = N; 927 return true; // [r+0] 928} 929 930 931/// getPreIndexedAddressParts - returns true by value, base pointer and 932/// offset pointer and addressing mode by reference if the node's address 933/// can be legally represented as pre-indexed load / store address. 934bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 935 SDOperand &Offset, 936 ISD::MemIndexedMode &AM, 937 SelectionDAG &DAG) { 938 // Disabled by default for now. 939 if (!EnablePPCPreinc) return false; 940 941 SDOperand Ptr; 942 MVT::ValueType VT; 943 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 944 Ptr = LD->getBasePtr(); 945 VT = LD->getLoadedVT(); 946 947 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 948 ST = ST; 949 Ptr = ST->getBasePtr(); 950 VT = ST->getStoredVT(); 951 } else 952 return false; 953 954 // PowerPC doesn't have preinc load/store instructions for vectors. 955 if (MVT::isVector(VT)) 956 return false; 957 958 // TODO: Check reg+reg first. 959 960 // LDU/STU use reg+imm*4, others use reg+imm. 961 if (VT != MVT::i64) { 962 // reg + imm 963 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 964 return false; 965 } else { 966 // reg + imm * 4. 967 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 968 return false; 969 } 970 971 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 972 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 973 // sext i32 to i64 when addr mode is r+i. 974 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 && 975 LD->getExtensionType() == ISD::SEXTLOAD && 976 isa<ConstantSDNode>(Offset)) 977 return false; 978 } 979 980 AM = ISD::PRE_INC; 981 return true; 982} 983 984//===----------------------------------------------------------------------===// 985// LowerOperation implementation 986//===----------------------------------------------------------------------===// 987 988static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 989 MVT::ValueType PtrVT = Op.getValueType(); 990 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 991 Constant *C = CP->getConstVal(); 992 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 993 SDOperand Zero = DAG.getConstant(0, PtrVT); 994 995 const TargetMachine &TM = DAG.getTarget(); 996 997 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 998 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 999 1000 // If this is a non-darwin platform, we don't support non-static relo models 1001 // yet. 1002 if (TM.getRelocationModel() == Reloc::Static || 1003 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1004 // Generate non-pic code that has direct accesses to the constant pool. 1005 // The address of the global is just (hi(&g)+lo(&g)). 1006 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1007 } 1008 1009 if (TM.getRelocationModel() == Reloc::PIC_) { 1010 // With PIC, the first instruction is actually "GR+hi(&G)". 1011 Hi = DAG.getNode(ISD::ADD, PtrVT, 1012 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1013 } 1014 1015 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1016 return Lo; 1017} 1018 1019static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 1020 MVT::ValueType PtrVT = Op.getValueType(); 1021 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1022 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1023 SDOperand Zero = DAG.getConstant(0, PtrVT); 1024 1025 const TargetMachine &TM = DAG.getTarget(); 1026 1027 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 1028 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 1029 1030 // If this is a non-darwin platform, we don't support non-static relo models 1031 // yet. 1032 if (TM.getRelocationModel() == Reloc::Static || 1033 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1034 // Generate non-pic code that has direct accesses to the constant pool. 1035 // The address of the global is just (hi(&g)+lo(&g)). 1036 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1037 } 1038 1039 if (TM.getRelocationModel() == Reloc::PIC_) { 1040 // With PIC, the first instruction is actually "GR+hi(&G)". 1041 Hi = DAG.getNode(ISD::ADD, PtrVT, 1042 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1043 } 1044 1045 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1046 return Lo; 1047} 1048 1049static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 1050 assert(0 && "TLS not implemented for PPC."); 1051} 1052 1053static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 1054 MVT::ValueType PtrVT = Op.getValueType(); 1055 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1056 GlobalValue *GV = GSDN->getGlobal(); 1057 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1058 SDOperand Zero = DAG.getConstant(0, PtrVT); 1059 1060 const TargetMachine &TM = DAG.getTarget(); 1061 1062 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 1063 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1064 1065 // If this is a non-darwin platform, we don't support non-static relo models 1066 // yet. 1067 if (TM.getRelocationModel() == Reloc::Static || 1068 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1069 // Generate non-pic code that has direct accesses to globals. 1070 // The address of the global is just (hi(&g)+lo(&g)). 1071 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1072 } 1073 1074 if (TM.getRelocationModel() == Reloc::PIC_) { 1075 // With PIC, the first instruction is actually "GR+hi(&G)". 1076 Hi = DAG.getNode(ISD::ADD, PtrVT, 1077 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1078 } 1079 1080 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1081 1082 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1083 return Lo; 1084 1085 // If the global is weak or external, we have to go through the lazy 1086 // resolution stub. 1087 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1088} 1089 1090static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 1091 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1092 1093 // If we're comparing for equality to zero, expose the fact that this is 1094 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1095 // fold the new nodes. 1096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1097 if (C->isNullValue() && CC == ISD::SETEQ) { 1098 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1099 SDOperand Zext = Op.getOperand(0); 1100 if (VT < MVT::i32) { 1101 VT = MVT::i32; 1102 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1103 } 1104 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1105 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1106 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1107 DAG.getConstant(Log2b, MVT::i32)); 1108 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1109 } 1110 // Leave comparisons against 0 and -1 alone for now, since they're usually 1111 // optimized. FIXME: revisit this when we can custom lower all setcc 1112 // optimizations. 1113 if (C->isAllOnesValue() || C->isNullValue()) 1114 return SDOperand(); 1115 } 1116 1117 // If we have an integer seteq/setne, turn it into a compare against zero 1118 // by xor'ing the rhs with the lhs, which is faster than setting a 1119 // condition register, reading it back out, and masking the correct bit. The 1120 // normal approach here uses sub to do this instead of xor. Using xor exposes 1121 // the result to other bit-twiddling opportunities. 1122 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1123 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1124 MVT::ValueType VT = Op.getValueType(); 1125 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1126 Op.getOperand(1)); 1127 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1128 } 1129 return SDOperand(); 1130} 1131 1132static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, 1133 int VarArgsFrameIndex, 1134 int VarArgsStackOffset, 1135 unsigned VarArgsNumGPR, 1136 unsigned VarArgsNumFPR, 1137 const PPCSubtarget &Subtarget) { 1138 1139 assert(0 && "VAARG in ELF32 ABI not implemented yet!"); 1140} 1141 1142static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 1143 int VarArgsFrameIndex, 1144 int VarArgsStackOffset, 1145 unsigned VarArgsNumGPR, 1146 unsigned VarArgsNumFPR, 1147 const PPCSubtarget &Subtarget) { 1148 1149 if (Subtarget.isMachoABI()) { 1150 // vastart just stores the address of the VarArgsFrameIndex slot into the 1151 // memory location argument. 1152 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1153 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1154 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1155 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 1156 SV->getOffset()); 1157 } 1158 1159 // For ELF 32 ABI we follow the layout of the va_list struct. 1160 // We suppose the given va_list is already allocated. 1161 // 1162 // typedef struct { 1163 // char gpr; /* index into the array of 8 GPRs 1164 // * stored in the register save area 1165 // * gpr=0 corresponds to r3, 1166 // * gpr=1 to r4, etc. 1167 // */ 1168 // char fpr; /* index into the array of 8 FPRs 1169 // * stored in the register save area 1170 // * fpr=0 corresponds to f1, 1171 // * fpr=1 to f2, etc. 1172 // */ 1173 // char *overflow_arg_area; 1174 // /* location on stack that holds 1175 // * the next overflow argument 1176 // */ 1177 // char *reg_save_area; 1178 // /* where r3:r10 and f1:f8 (if saved) 1179 // * are stored 1180 // */ 1181 // } va_list[1]; 1182 1183 1184 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); 1185 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); 1186 1187 1188 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1189 1190 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1191 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1192 1193 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, 1194 PtrVT); 1195 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1, 1196 PtrVT); 1197 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT); 1198 1199 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1200 1201 // Store first byte : number of int regs 1202 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, 1203 Op.getOperand(1), SV->getValue(), 1204 SV->getOffset()); 1205 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), 1206 ConstFPROffset); 1207 1208 // Store second byte : number of float regs 1209 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, 1210 SV->getValue(), SV->getOffset()); 1211 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); 1212 1213 // Store second word : arguments given on stack 1214 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr, 1215 SV->getValue(), SV->getOffset()); 1216 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); 1217 1218 // Store third word : arguments given in registers 1219 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(), 1220 SV->getOffset()); 1221 1222} 1223 1224#include "PPCGenCallingConv.inc" 1225 1226/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1227/// depending on which subtarget is selected. 1228static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1229 if (Subtarget.isMachoABI()) { 1230 static const unsigned FPR[] = { 1231 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1232 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1233 }; 1234 return FPR; 1235 } 1236 1237 1238 static const unsigned FPR[] = { 1239 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1240 PPC::F8 1241 }; 1242 return FPR; 1243} 1244 1245static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 1246 int &VarArgsFrameIndex, 1247 int &VarArgsStackOffset, 1248 unsigned &VarArgsNumGPR, 1249 unsigned &VarArgsNumFPR, 1250 const PPCSubtarget &Subtarget) { 1251 // TODO: add description of PPC stack frame format, or at least some docs. 1252 // 1253 MachineFunction &MF = DAG.getMachineFunction(); 1254 MachineFrameInfo *MFI = MF.getFrameInfo(); 1255 SSARegMap *RegMap = MF.getSSARegMap(); 1256 SmallVector<SDOperand, 8> ArgValues; 1257 SDOperand Root = Op.getOperand(0); 1258 1259 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1260 bool isPPC64 = PtrVT == MVT::i64; 1261 bool isMachoABI = Subtarget.isMachoABI(); 1262 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1263 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1264 1265 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1266 1267 static const unsigned GPR_32[] = { // 32-bit registers. 1268 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1269 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1270 }; 1271 static const unsigned GPR_64[] = { // 64-bit registers. 1272 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1273 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1274 }; 1275 1276 static const unsigned *FPR = GetFPR(Subtarget); 1277 1278 static const unsigned VR[] = { 1279 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1280 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1281 }; 1282 1283 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1284 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; 1285 const unsigned Num_VR_Regs = array_lengthof( VR); 1286 1287 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1288 1289 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1290 1291 // Add DAG nodes to load the arguments or copy them out of registers. On 1292 // entry to a function on PPC, the arguments start after the linkage area, 1293 // although the first ones are often in registers. 1294 // 1295 // In the ELF 32 ABI, GPRs and stack are double word align: an argument 1296 // represented with two words (long long or double) must be copied to an 1297 // even GPR_idx value or to an even ArgOffset value. 1298 1299 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1300 SDOperand ArgVal; 1301 bool needsLoad = false; 1302 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 1303 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 1304 unsigned ArgSize = ObjSize; 1305 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue(); 1306 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1307 // See if next argument requires stack alignment in ELF 1308 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) && 1309 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) && 1310 (!(Flags & AlignFlag))); 1311 1312 unsigned CurArgOffset = ArgOffset; 1313 switch (ObjectVT) { 1314 default: assert(0 && "Unhandled argument type!"); 1315 case MVT::i32: 1316 // Double word align in ELF 1317 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1318 if (GPR_idx != Num_GPR_Regs) { 1319 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1320 MF.addLiveIn(GPR[GPR_idx], VReg); 1321 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1322 ++GPR_idx; 1323 } else { 1324 needsLoad = true; 1325 ArgSize = PtrByteSize; 1326 } 1327 // Stack align in ELF 1328 if (needsLoad && Expand && isELF32_ABI) 1329 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1330 // All int arguments reserve stack space in Macho ABI. 1331 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1332 break; 1333 1334 case MVT::i64: // PPC64 1335 if (GPR_idx != Num_GPR_Regs) { 1336 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1337 MF.addLiveIn(GPR[GPR_idx], VReg); 1338 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1339 ++GPR_idx; 1340 } else { 1341 needsLoad = true; 1342 } 1343 // All int arguments reserve stack space in Macho ABI. 1344 if (isMachoABI || needsLoad) ArgOffset += 8; 1345 break; 1346 1347 case MVT::f32: 1348 case MVT::f64: 1349 // Every 4 bytes of argument space consumes one of the GPRs available for 1350 // argument passing. 1351 if (GPR_idx != Num_GPR_Regs && isMachoABI) { 1352 ++GPR_idx; 1353 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1354 ++GPR_idx; 1355 } 1356 if (FPR_idx != Num_FPR_Regs) { 1357 unsigned VReg; 1358 if (ObjectVT == MVT::f32) 1359 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 1360 else 1361 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1362 MF.addLiveIn(FPR[FPR_idx], VReg); 1363 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1364 ++FPR_idx; 1365 } else { 1366 needsLoad = true; 1367 } 1368 1369 // Stack align in ELF 1370 if (needsLoad && Expand && isELF32_ABI) 1371 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1372 // All FP arguments reserve stack space in Macho ABI. 1373 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1374 break; 1375 case MVT::v4f32: 1376 case MVT::v4i32: 1377 case MVT::v8i16: 1378 case MVT::v16i8: 1379 // Note that vector arguments in registers don't reserve stack space. 1380 if (VR_idx != Num_VR_Regs) { 1381 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); 1382 MF.addLiveIn(VR[VR_idx], VReg); 1383 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1384 ++VR_idx; 1385 } else { 1386 // This should be simple, but requires getting 16-byte aligned stack 1387 // values. 1388 assert(0 && "Loading VR argument not implemented yet!"); 1389 needsLoad = true; 1390 } 1391 break; 1392 } 1393 1394 // We need to load the argument to a virtual register if we determined above 1395 // that we ran out of physical registers of the appropriate type 1396 if (needsLoad) { 1397 // If the argument is actually used, emit a load from the right stack 1398 // slot. 1399 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 1400 int FI = MFI->CreateFixedObject(ObjSize, 1401 CurArgOffset + (ArgSize - ObjSize)); 1402 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1403 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1404 } else { 1405 // Don't emit a dead load. 1406 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); 1407 } 1408 } 1409 1410 ArgValues.push_back(ArgVal); 1411 } 1412 1413 // If the function takes variable number of arguments, make a frame index for 1414 // the start of the first vararg value... for expansion of llvm.va_start. 1415 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1416 if (isVarArg) { 1417 1418 int depth; 1419 if (isELF32_ABI) { 1420 VarArgsNumGPR = GPR_idx; 1421 VarArgsNumFPR = FPR_idx; 1422 1423 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame 1424 // pointer. 1425 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 + 1426 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 + 1427 MVT::getSizeInBits(PtrVT)/8); 1428 1429 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1430 ArgOffset); 1431 1432 } 1433 else 1434 depth = ArgOffset; 1435 1436 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1437 depth); 1438 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1439 1440 SmallVector<SDOperand, 8> MemOps; 1441 1442 // In ELF 32 ABI, the fixed integer arguments of a variadic function are 1443 // stored to the VarArgsFrameIndex on the stack. 1444 if (isELF32_ABI) { 1445 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { 1446 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT); 1447 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1448 MemOps.push_back(Store); 1449 // Increment the address by four for the next argument to store 1450 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1451 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1452 } 1453 } 1454 1455 // If this function is vararg, store any remaining integer argument regs 1456 // to their spots on the stack so that they may be loaded by deferencing the 1457 // result of va_next. 1458 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1459 unsigned VReg; 1460 if (isPPC64) 1461 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1462 else 1463 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1464 1465 MF.addLiveIn(GPR[GPR_idx], VReg); 1466 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1467 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1468 MemOps.push_back(Store); 1469 // Increment the address by four for the next argument to store 1470 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1471 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1472 } 1473 1474 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex 1475 // on the stack. 1476 if (isELF32_ABI) { 1477 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { 1478 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); 1479 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1480 MemOps.push_back(Store); 1481 // Increment the address by eight for the next argument to store 1482 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1483 PtrVT); 1484 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1485 } 1486 1487 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { 1488 unsigned VReg; 1489 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1490 1491 MF.addLiveIn(FPR[FPR_idx], VReg); 1492 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); 1493 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1494 MemOps.push_back(Store); 1495 // Increment the address by eight for the next argument to store 1496 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1497 PtrVT); 1498 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1499 } 1500 } 1501 1502 if (!MemOps.empty()) 1503 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1504 } 1505 1506 ArgValues.push_back(Root); 1507 1508 // Return the new list of results. 1509 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1510 Op.Val->value_end()); 1511 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1512} 1513 1514/// isCallCompatibleAddress - Return the immediate to use if the specified 1515/// 32-bit value is representable in the immediate field of a BxA instruction. 1516static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 1517 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1518 if (!C) return 0; 1519 1520 int Addr = C->getValue(); 1521 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1522 (Addr << 6 >> 6) != Addr) 1523 return 0; // Top 6 bits have to be sext of immediate. 1524 1525 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val; 1526} 1527 1528 1529static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, 1530 const PPCSubtarget &Subtarget) { 1531 SDOperand Chain = Op.getOperand(0); 1532 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1533 SDOperand Callee = Op.getOperand(4); 1534 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1535 1536 bool isMachoABI = Subtarget.isMachoABI(); 1537 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1538 1539 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1540 bool isPPC64 = PtrVT == MVT::i64; 1541 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1542 1543 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1544 // SelectExpr to use to put the arguments in the appropriate registers. 1545 std::vector<SDOperand> args_to_use; 1546 1547 // Count how many bytes are to be pushed on the stack, including the linkage 1548 // area, and parameter passing area. We start with 24/48 bytes, which is 1549 // prereserved space for [SP][CR][LR][3 x unused]. 1550 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1551 1552 // Add up all the space actually used. 1553 for (unsigned i = 0; i != NumOps; ++i) { 1554 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 1555 ArgSize = std::max(ArgSize, PtrByteSize); 1556 NumBytes += ArgSize; 1557 } 1558 1559 // The prolog code of the callee may store up to 8 GPR argument registers to 1560 // the stack, allowing va_start to index over them in memory if its varargs. 1561 // Because we cannot tell if this is needed on the caller side, we have to 1562 // conservatively assume that it is needed. As such, make sure we have at 1563 // least enough stack space for the caller to store the 8 GPRs. 1564 NumBytes = std::max(NumBytes, 1565 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1566 1567 // Adjust the stack pointer for the new arguments... 1568 // These operations are automatically eliminated by the prolog/epilog pass 1569 Chain = DAG.getCALLSEQ_START(Chain, 1570 DAG.getConstant(NumBytes, PtrVT)); 1571 1572 // Set up a copy of the stack pointer for use loading and storing any 1573 // arguments that may not fit in the registers available for argument 1574 // passing. 1575 SDOperand StackPtr; 1576 if (isPPC64) 1577 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 1578 else 1579 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1580 1581 // Figure out which arguments are going to go in registers, and which in 1582 // memory. Also, if this is a vararg function, floating point operations 1583 // must be stored to our stack, and loaded into integer regs as well, if 1584 // any integer regs are available for argument passing. 1585 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1586 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1587 1588 static const unsigned GPR_32[] = { // 32-bit registers. 1589 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1590 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1591 }; 1592 static const unsigned GPR_64[] = { // 64-bit registers. 1593 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1594 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1595 }; 1596 static const unsigned *FPR = GetFPR(Subtarget); 1597 1598 static const unsigned VR[] = { 1599 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1600 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1601 }; 1602 const unsigned NumGPRs = array_lengthof(GPR_32); 1603 const unsigned NumFPRs = isMachoABI ? 13 : 8; 1604 const unsigned NumVRs = array_lengthof( VR); 1605 1606 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1607 1608 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1609 SmallVector<SDOperand, 8> MemOpChains; 1610 for (unsigned i = 0; i != NumOps; ++i) { 1611 bool inMem = false; 1612 SDOperand Arg = Op.getOperand(5+2*i); 1613 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1614 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1615 // See if next argument requires stack alignment in ELF 1616 unsigned next = 5+2*(i+1)+1; 1617 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) && 1618 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) && 1619 (!(Flags & AlignFlag))); 1620 1621 // PtrOff will be used to store the current argument to the stack if a 1622 // register cannot be found for it. 1623 SDOperand PtrOff; 1624 1625 // Stack align in ELF 32 1626 if (isELF32_ABI && Expand) 1627 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, 1628 StackPtr.getValueType()); 1629 else 1630 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1631 1632 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1633 1634 // On PPC64, promote integers to 64-bit values. 1635 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1636 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1637 1638 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1639 } 1640 1641 switch (Arg.getValueType()) { 1642 default: assert(0 && "Unexpected ValueType for argument!"); 1643 case MVT::i32: 1644 case MVT::i64: 1645 // Double word align in ELF 1646 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2); 1647 if (GPR_idx != NumGPRs) { 1648 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1649 } else { 1650 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1651 inMem = true; 1652 } 1653 if (inMem || isMachoABI) { 1654 // Stack align in ELF 1655 if (isELF32_ABI && Expand) 1656 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1657 1658 ArgOffset += PtrByteSize; 1659 } 1660 break; 1661 case MVT::f32: 1662 case MVT::f64: 1663 if (isVarArg) { 1664 // Float varargs need to be promoted to double. 1665 if (Arg.getValueType() == MVT::f32) 1666 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); 1667 } 1668 1669 if (FPR_idx != NumFPRs) { 1670 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1671 1672 if (isVarArg) { 1673 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1674 MemOpChains.push_back(Store); 1675 1676 // Float varargs are always shadowed in available integer registers 1677 if (GPR_idx != NumGPRs) { 1678 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1679 MemOpChains.push_back(Load.getValue(1)); 1680 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1681 Load)); 1682 } 1683 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 1684 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1685 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1686 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1687 MemOpChains.push_back(Load.getValue(1)); 1688 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1689 Load)); 1690 } 1691 } else { 1692 // If we have any FPRs remaining, we may also have GPRs remaining. 1693 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1694 // GPRs. 1695 if (isMachoABI) { 1696 if (GPR_idx != NumGPRs) 1697 ++GPR_idx; 1698 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 1699 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 1700 ++GPR_idx; 1701 } 1702 } 1703 } else { 1704 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1705 inMem = true; 1706 } 1707 if (inMem || isMachoABI) { 1708 // Stack align in ELF 1709 if (isELF32_ABI && Expand) 1710 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1711 if (isPPC64) 1712 ArgOffset += 8; 1713 else 1714 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1715 } 1716 break; 1717 case MVT::v4f32: 1718 case MVT::v4i32: 1719 case MVT::v8i16: 1720 case MVT::v16i8: 1721 assert(!isVarArg && "Don't support passing vectors to varargs yet!"); 1722 assert(VR_idx != NumVRs && 1723 "Don't support passing more than 12 vector args yet!"); 1724 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 1725 break; 1726 } 1727 } 1728 if (!MemOpChains.empty()) 1729 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1730 &MemOpChains[0], MemOpChains.size()); 1731 1732 // Build a sequence of copy-to-reg nodes chained together with token chain 1733 // and flag operands which copy the outgoing args into the appropriate regs. 1734 SDOperand InFlag; 1735 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1736 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1737 InFlag); 1738 InFlag = Chain.getValue(1); 1739 } 1740 1741 // With the ELF 32 ABI, set CR6 to true if this is a vararg call. 1742 if (isVarArg && isELF32_ABI) { 1743 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0); 1744 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag); 1745 InFlag = Chain.getValue(1); 1746 } 1747 1748 std::vector<MVT::ValueType> NodeTys; 1749 NodeTys.push_back(MVT::Other); // Returns a chain 1750 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1751 1752 SmallVector<SDOperand, 8> Ops; 1753 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 1754 1755 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1756 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1757 // node so that legalize doesn't hack it. 1758 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1759 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 1760 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1761 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 1762 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 1763 // If this is an absolute destination address, use the munged value. 1764 Callee = SDOperand(Dest, 0); 1765 else { 1766 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 1767 // to do the call, we can't use PPCISD::CALL. 1768 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 1769 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 1770 InFlag = Chain.getValue(1); 1771 1772 // Copy the callee address into R12 on darwin. 1773 if (isMachoABI) { 1774 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); 1775 InFlag = Chain.getValue(1); 1776 } 1777 1778 NodeTys.clear(); 1779 NodeTys.push_back(MVT::Other); 1780 NodeTys.push_back(MVT::Flag); 1781 Ops.push_back(Chain); 1782 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 1783 Callee.Val = 0; 1784 } 1785 1786 // If this is a direct call, pass the chain and the callee. 1787 if (Callee.Val) { 1788 Ops.push_back(Chain); 1789 Ops.push_back(Callee); 1790 } 1791 1792 // Add argument registers to the end of the list so that they are known live 1793 // into the call. 1794 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1795 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1796 RegsToPass[i].second.getValueType())); 1797 1798 if (InFlag.Val) 1799 Ops.push_back(InFlag); 1800 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 1801 InFlag = Chain.getValue(1); 1802 1803 SDOperand ResultVals[3]; 1804 unsigned NumResults = 0; 1805 NodeTys.clear(); 1806 1807 // If the call has results, copy the values out of the ret val registers. 1808 switch (Op.Val->getValueType(0)) { 1809 default: assert(0 && "Unexpected ret value!"); 1810 case MVT::Other: break; 1811 case MVT::i32: 1812 if (Op.Val->getValueType(1) == MVT::i32) { 1813 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1814 ResultVals[0] = Chain.getValue(0); 1815 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, 1816 Chain.getValue(2)).getValue(1); 1817 ResultVals[1] = Chain.getValue(0); 1818 NumResults = 2; 1819 NodeTys.push_back(MVT::i32); 1820 } else { 1821 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1822 ResultVals[0] = Chain.getValue(0); 1823 NumResults = 1; 1824 } 1825 NodeTys.push_back(MVT::i32); 1826 break; 1827 case MVT::i64: 1828 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 1829 ResultVals[0] = Chain.getValue(0); 1830 NumResults = 1; 1831 NodeTys.push_back(MVT::i64); 1832 break; 1833 case MVT::f64: 1834 if (Op.Val->getValueType(1) == MVT::f64) { 1835 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1); 1836 ResultVals[0] = Chain.getValue(0); 1837 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64, 1838 Chain.getValue(2)).getValue(1); 1839 ResultVals[1] = Chain.getValue(0); 1840 NumResults = 2; 1841 NodeTys.push_back(MVT::f64); 1842 NodeTys.push_back(MVT::f64); 1843 break; 1844 } 1845 // else fall through 1846 case MVT::f32: 1847 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 1848 InFlag).getValue(1); 1849 ResultVals[0] = Chain.getValue(0); 1850 NumResults = 1; 1851 NodeTys.push_back(Op.Val->getValueType(0)); 1852 break; 1853 case MVT::v4f32: 1854 case MVT::v4i32: 1855 case MVT::v8i16: 1856 case MVT::v16i8: 1857 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 1858 InFlag).getValue(1); 1859 ResultVals[0] = Chain.getValue(0); 1860 NumResults = 1; 1861 NodeTys.push_back(Op.Val->getValueType(0)); 1862 break; 1863 } 1864 1865 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 1866 DAG.getConstant(NumBytes, PtrVT)); 1867 NodeTys.push_back(MVT::Other); 1868 1869 // If the function returns void, just return the chain. 1870 if (NumResults == 0) 1871 return Chain; 1872 1873 // Otherwise, merge everything together with a MERGE_VALUES node. 1874 ResultVals[NumResults++] = Chain; 1875 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1876 ResultVals, NumResults); 1877 return Res.getValue(Op.ResNo); 1878} 1879 1880static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { 1881 SmallVector<CCValAssign, 16> RVLocs; 1882 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 1883 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1884 CCState CCInfo(CC, isVarArg, TM, RVLocs); 1885 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC); 1886 1887 // If this is the first return lowered for this function, add the regs to the 1888 // liveout set for the function. 1889 if (DAG.getMachineFunction().liveout_empty()) { 1890 for (unsigned i = 0; i != RVLocs.size(); ++i) 1891 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); 1892 } 1893 1894 SDOperand Chain = Op.getOperand(0); 1895 SDOperand Flag; 1896 1897 // Copy the result values into the output registers. 1898 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1899 CCValAssign &VA = RVLocs[i]; 1900 assert(VA.isRegLoc() && "Can only return in registers!"); 1901 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 1902 Flag = Chain.getValue(1); 1903 } 1904 1905 if (Flag.Val) 1906 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); 1907 else 1908 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); 1909} 1910 1911static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, 1912 const PPCSubtarget &Subtarget) { 1913 // When we pop the dynamic allocation we need to restore the SP link. 1914 1915 // Get the corect type for pointers. 1916 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1917 1918 // Construct the stack pointer operand. 1919 bool IsPPC64 = Subtarget.isPPC64(); 1920 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 1921 SDOperand StackPtr = DAG.getRegister(SP, PtrVT); 1922 1923 // Get the operands for the STACKRESTORE. 1924 SDOperand Chain = Op.getOperand(0); 1925 SDOperand SaveSP = Op.getOperand(1); 1926 1927 // Load the old link SP. 1928 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 1929 1930 // Restore the stack pointer. 1931 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 1932 1933 // Store the old link SP. 1934 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 1935} 1936 1937static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, 1938 const PPCSubtarget &Subtarget) { 1939 MachineFunction &MF = DAG.getMachineFunction(); 1940 bool IsPPC64 = Subtarget.isPPC64(); 1941 bool isMachoABI = Subtarget.isMachoABI(); 1942 1943 // Get current frame pointer save index. The users of this index will be 1944 // primarily DYNALLOC instructions. 1945 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1946 int FPSI = FI->getFramePointerSaveIndex(); 1947 1948 // If the frame pointer save index hasn't been defined yet. 1949 if (!FPSI) { 1950 // Find out what the fix offset of the frame pointer save area. 1951 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 1952 1953 // Allocate the frame index for frame pointer save area. 1954 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 1955 // Save the result. 1956 FI->setFramePointerSaveIndex(FPSI); 1957 } 1958 1959 // Get the inputs. 1960 SDOperand Chain = Op.getOperand(0); 1961 SDOperand Size = Op.getOperand(1); 1962 1963 // Get the corect type for pointers. 1964 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1965 // Negate the size. 1966 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, 1967 DAG.getConstant(0, PtrVT), Size); 1968 // Construct a node for the frame pointer save index. 1969 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); 1970 // Build a DYNALLOC node. 1971 SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; 1972 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 1973 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 1974} 1975 1976 1977/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 1978/// possible. 1979static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 1980 // Not FP? Not a fsel. 1981 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 1982 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 1983 return SDOperand(); 1984 1985 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1986 1987 // Cannot handle SETEQ/SETNE. 1988 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 1989 1990 MVT::ValueType ResVT = Op.getValueType(); 1991 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 1992 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 1993 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 1994 1995 // If the RHS of the comparison is a 0.0, we don't need to do the 1996 // subtraction at all. 1997 if (isFloatingPointZero(RHS)) 1998 switch (CC) { 1999 default: break; // SETUO etc aren't handled by fsel. 2000 case ISD::SETULT: 2001 case ISD::SETOLT: 2002 case ISD::SETLT: 2003 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2004 case ISD::SETUGE: 2005 case ISD::SETOGE: 2006 case ISD::SETGE: 2007 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2008 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2009 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 2010 case ISD::SETUGT: 2011 case ISD::SETOGT: 2012 case ISD::SETGT: 2013 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2014 case ISD::SETULE: 2015 case ISD::SETOLE: 2016 case ISD::SETLE: 2017 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2018 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2019 return DAG.getNode(PPCISD::FSEL, ResVT, 2020 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 2021 } 2022 2023 SDOperand Cmp; 2024 switch (CC) { 2025 default: break; // SETUO etc aren't handled by fsel. 2026 case ISD::SETULT: 2027 case ISD::SETOLT: 2028 case ISD::SETLT: 2029 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2030 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2031 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2032 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2033 case ISD::SETUGE: 2034 case ISD::SETOGE: 2035 case ISD::SETGE: 2036 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2037 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2038 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2039 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2040 case ISD::SETUGT: 2041 case ISD::SETOGT: 2042 case ISD::SETGT: 2043 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2044 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2045 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2046 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2047 case ISD::SETULE: 2048 case ISD::SETOLE: 2049 case ISD::SETLE: 2050 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2051 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2052 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2053 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2054 } 2055 return SDOperand(); 2056} 2057 2058static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 2059 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 2060 SDOperand Src = Op.getOperand(0); 2061 if (Src.getValueType() == MVT::f32) 2062 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 2063 2064 SDOperand Tmp; 2065 switch (Op.getValueType()) { 2066 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 2067 case MVT::i32: 2068 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 2069 break; 2070 case MVT::i64: 2071 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 2072 break; 2073 } 2074 2075 // Convert the FP value to an int value through memory. 2076 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 2077 if (Op.getValueType() == MVT::i32) 2078 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 2079 return Bits; 2080} 2081 2082static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 2083 if (Op.getOperand(0).getValueType() == MVT::i64) { 2084 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 2085 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 2086 if (Op.getValueType() == MVT::f32) 2087 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 2088 return FP; 2089 } 2090 2091 assert(Op.getOperand(0).getValueType() == MVT::i32 && 2092 "Unhandled SINT_TO_FP type in custom expander!"); 2093 // Since we only generate this in 64-bit mode, we can take advantage of 2094 // 64-bit registers. In particular, sign extend the input value into the 2095 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 2096 // then lfd it and fcfid it. 2097 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2098 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 2099 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2100 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2101 2102 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 2103 Op.getOperand(0)); 2104 2105 // STD the extended value into the stack slot. 2106 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 2107 DAG.getEntryNode(), Ext64, FIdx, 2108 DAG.getSrcValue(NULL)); 2109 // Load the value as a double. 2110 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 2111 2112 // FCFID it and return it. 2113 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 2114 if (Op.getValueType() == MVT::f32) 2115 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 2116 return FP; 2117} 2118 2119static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2120 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2121 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 2122 2123 // Expand into a bunch of logical ops. Note that these ops 2124 // depend on the PPC behavior for oversized shift amounts. 2125 SDOperand Lo = Op.getOperand(0); 2126 SDOperand Hi = Op.getOperand(1); 2127 SDOperand Amt = Op.getOperand(2); 2128 2129 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2130 DAG.getConstant(32, MVT::i32), Amt); 2131 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 2132 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 2133 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2134 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2135 DAG.getConstant(-32U, MVT::i32)); 2136 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 2137 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2138 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 2139 SDOperand OutOps[] = { OutLo, OutHi }; 2140 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2141 OutOps, 2); 2142} 2143 2144static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2145 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2146 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); 2147 2148 // Otherwise, expand into a bunch of logical ops. Note that these ops 2149 // depend on the PPC behavior for oversized shift amounts. 2150 SDOperand Lo = Op.getOperand(0); 2151 SDOperand Hi = Op.getOperand(1); 2152 SDOperand Amt = Op.getOperand(2); 2153 2154 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2155 DAG.getConstant(32, MVT::i32), Amt); 2156 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2157 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2158 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2159 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2160 DAG.getConstant(-32U, MVT::i32)); 2161 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 2162 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2163 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 2164 SDOperand OutOps[] = { OutLo, OutHi }; 2165 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2166 OutOps, 2); 2167} 2168 2169static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 2170 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2171 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 2172 2173 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 2174 SDOperand Lo = Op.getOperand(0); 2175 SDOperand Hi = Op.getOperand(1); 2176 SDOperand Amt = Op.getOperand(2); 2177 2178 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2179 DAG.getConstant(32, MVT::i32), Amt); 2180 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2181 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2182 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2183 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2184 DAG.getConstant(-32U, MVT::i32)); 2185 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 2186 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 2187 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 2188 Tmp4, Tmp6, ISD::SETLE); 2189 SDOperand OutOps[] = { OutLo, OutHi }; 2190 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2191 OutOps, 2); 2192} 2193 2194//===----------------------------------------------------------------------===// 2195// Vector related lowering. 2196// 2197 2198// If this is a vector of constants or undefs, get the bits. A bit in 2199// UndefBits is set if the corresponding element of the vector is an 2200// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2201// zero. Return true if this is not an array of constants, false if it is. 2202// 2203static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 2204 uint64_t UndefBits[2]) { 2205 // Start with zero'd results. 2206 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 2207 2208 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 2209 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 2210 SDOperand OpVal = BV->getOperand(i); 2211 2212 unsigned PartNo = i >= e/2; // In the upper 128 bits? 2213 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 2214 2215 uint64_t EltBits = 0; 2216 if (OpVal.getOpcode() == ISD::UNDEF) { 2217 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 2218 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 2219 continue; 2220 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 2221 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 2222 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 2223 assert(CN->getValueType(0) == MVT::f32 && 2224 "Only one legal FP vector type!"); 2225 EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); 2226 } else { 2227 // Nonconstant element. 2228 return true; 2229 } 2230 2231 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 2232 } 2233 2234 //printf("%llx %llx %llx %llx\n", 2235 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 2236 return false; 2237} 2238 2239// If this is a splat (repetition) of a value across the whole vector, return 2240// the smallest size that splats it. For example, "0x01010101010101..." is a 2241// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2242// SplatSize = 1 byte. 2243static bool isConstantSplat(const uint64_t Bits128[2], 2244 const uint64_t Undef128[2], 2245 unsigned &SplatBits, unsigned &SplatUndef, 2246 unsigned &SplatSize) { 2247 2248 // Don't let undefs prevent splats from matching. See if the top 64-bits are 2249 // the same as the lower 64-bits, ignoring undefs. 2250 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 2251 return false; // Can't be a splat if two pieces don't match. 2252 2253 uint64_t Bits64 = Bits128[0] | Bits128[1]; 2254 uint64_t Undef64 = Undef128[0] & Undef128[1]; 2255 2256 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 2257 // undefs. 2258 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 2259 return false; // Can't be a splat if two pieces don't match. 2260 2261 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 2262 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 2263 2264 // If the top 16-bits are different than the lower 16-bits, ignoring 2265 // undefs, we have an i32 splat. 2266 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 2267 SplatBits = Bits32; 2268 SplatUndef = Undef32; 2269 SplatSize = 4; 2270 return true; 2271 } 2272 2273 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 2274 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 2275 2276 // If the top 8-bits are different than the lower 8-bits, ignoring 2277 // undefs, we have an i16 splat. 2278 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 2279 SplatBits = Bits16; 2280 SplatUndef = Undef16; 2281 SplatSize = 2; 2282 return true; 2283 } 2284 2285 // Otherwise, we have an 8-bit splat. 2286 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 2287 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 2288 SplatSize = 1; 2289 return true; 2290} 2291 2292/// BuildSplatI - Build a canonical splati of Val with an element size of 2293/// SplatSize. Cast the result to VT. 2294static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 2295 SelectionDAG &DAG) { 2296 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 2297 2298 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 2299 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 2300 }; 2301 2302 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 2303 2304 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 2305 if (Val == -1) 2306 SplatSize = 1; 2307 2308 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 2309 2310 // Build a canonical splat for this value. 2311 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT)); 2312 SmallVector<SDOperand, 8> Ops; 2313 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 2314 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 2315 &Ops[0], Ops.size()); 2316 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 2317} 2318 2319/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 2320/// specified intrinsic ID. 2321static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 2322 SelectionDAG &DAG, 2323 MVT::ValueType DestVT = MVT::Other) { 2324 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 2325 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2326 DAG.getConstant(IID, MVT::i32), LHS, RHS); 2327} 2328 2329/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 2330/// specified intrinsic ID. 2331static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 2332 SDOperand Op2, SelectionDAG &DAG, 2333 MVT::ValueType DestVT = MVT::Other) { 2334 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 2335 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2336 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 2337} 2338 2339 2340/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 2341/// amount. The result has the specified value type. 2342static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 2343 MVT::ValueType VT, SelectionDAG &DAG) { 2344 // Force LHS/RHS to be the right type. 2345 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 2346 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 2347 2348 SDOperand Ops[16]; 2349 for (unsigned i = 0; i != 16; ++i) 2350 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 2351 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 2352 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 2353 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 2354} 2355 2356// If this is a case we can't handle, return null and let the default 2357// expansion code take care of it. If we CAN select this case, and if it 2358// selects to a single instruction, return Op. Otherwise, if we can codegen 2359// this case more efficiently than a constant pool load, lower it to the 2360// sequence of ops that should be used. 2361static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2362 // If this is a vector of constants or undefs, get the bits. A bit in 2363 // UndefBits is set if the corresponding element of the vector is an 2364 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2365 // zero. 2366 uint64_t VectorBits[2]; 2367 uint64_t UndefBits[2]; 2368 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 2369 return SDOperand(); // Not a constant vector. 2370 2371 // If this is a splat (repetition) of a value across the whole vector, return 2372 // the smallest size that splats it. For example, "0x01010101010101..." is a 2373 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2374 // SplatSize = 1 byte. 2375 unsigned SplatBits, SplatUndef, SplatSize; 2376 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 2377 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 2378 2379 // First, handle single instruction cases. 2380 2381 // All zeros? 2382 if (SplatBits == 0) { 2383 // Canonicalize all zero vectors to be v4i32. 2384 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 2385 SDOperand Z = DAG.getConstant(0, MVT::i32); 2386 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 2387 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 2388 } 2389 return Op; 2390 } 2391 2392 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 2393 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 2394 if (SextVal >= -16 && SextVal <= 15) 2395 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 2396 2397 2398 // Two instruction sequences. 2399 2400 // If this value is in the range [-32,30] and is even, use: 2401 // tmp = VSPLTI[bhw], result = add tmp, tmp 2402 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 2403 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 2404 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 2405 } 2406 2407 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 2408 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 2409 // for fneg/fabs. 2410 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 2411 // Make -1 and vspltisw -1: 2412 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 2413 2414 // Make the VSLW intrinsic, computing 0x8000_0000. 2415 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 2416 OnesV, DAG); 2417 2418 // xor by OnesV to invert it. 2419 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 2420 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2421 } 2422 2423 // Check to see if this is a wide variety of vsplti*, binop self cases. 2424 unsigned SplatBitSize = SplatSize*8; 2425 static const signed char SplatCsts[] = { 2426 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 2427 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 2428 }; 2429 2430 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 2431 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 2432 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 2433 int i = SplatCsts[idx]; 2434 2435 // Figure out what shift amount will be used by altivec if shifted by i in 2436 // this splat size. 2437 unsigned TypeShiftAmt = i & (SplatBitSize-1); 2438 2439 // vsplti + shl self. 2440 if (SextVal == (i << (int)TypeShiftAmt)) { 2441 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2442 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2443 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 2444 Intrinsic::ppc_altivec_vslw 2445 }; 2446 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2447 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2448 } 2449 2450 // vsplti + srl self. 2451 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2452 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2453 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2454 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 2455 Intrinsic::ppc_altivec_vsrw 2456 }; 2457 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2458 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2459 } 2460 2461 // vsplti + sra self. 2462 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2463 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2464 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2465 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 2466 Intrinsic::ppc_altivec_vsraw 2467 }; 2468 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2469 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2470 } 2471 2472 // vsplti + rol self. 2473 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 2474 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 2475 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2476 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2477 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 2478 Intrinsic::ppc_altivec_vrlw 2479 }; 2480 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2481 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2482 } 2483 2484 // t = vsplti c, result = vsldoi t, t, 1 2485 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 2486 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2487 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 2488 } 2489 // t = vsplti c, result = vsldoi t, t, 2 2490 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 2491 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2492 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 2493 } 2494 // t = vsplti c, result = vsldoi t, t, 3 2495 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 2496 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2497 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 2498 } 2499 } 2500 2501 // Three instruction sequences. 2502 2503 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 2504 if (SextVal >= 0 && SextVal <= 31) { 2505 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 2506 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2507 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS); 2508 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2509 } 2510 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 2511 if (SextVal >= -31 && SextVal <= 0) { 2512 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 2513 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2514 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS); 2515 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2516 } 2517 } 2518 2519 return SDOperand(); 2520} 2521 2522/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2523/// the specified operations to build the shuffle. 2524static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 2525 SDOperand RHS, SelectionDAG &DAG) { 2526 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2527 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2528 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2529 2530 enum { 2531 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2532 OP_VMRGHW, 2533 OP_VMRGLW, 2534 OP_VSPLTISW0, 2535 OP_VSPLTISW1, 2536 OP_VSPLTISW2, 2537 OP_VSPLTISW3, 2538 OP_VSLDOI4, 2539 OP_VSLDOI8, 2540 OP_VSLDOI12 2541 }; 2542 2543 if (OpNum == OP_COPY) { 2544 if (LHSID == (1*9+2)*9+3) return LHS; 2545 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2546 return RHS; 2547 } 2548 2549 SDOperand OpLHS, OpRHS; 2550 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 2551 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 2552 2553 unsigned ShufIdxs[16]; 2554 switch (OpNum) { 2555 default: assert(0 && "Unknown i32 permute!"); 2556 case OP_VMRGHW: 2557 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 2558 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 2559 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 2560 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 2561 break; 2562 case OP_VMRGLW: 2563 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 2564 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 2565 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 2566 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 2567 break; 2568 case OP_VSPLTISW0: 2569 for (unsigned i = 0; i != 16; ++i) 2570 ShufIdxs[i] = (i&3)+0; 2571 break; 2572 case OP_VSPLTISW1: 2573 for (unsigned i = 0; i != 16; ++i) 2574 ShufIdxs[i] = (i&3)+4; 2575 break; 2576 case OP_VSPLTISW2: 2577 for (unsigned i = 0; i != 16; ++i) 2578 ShufIdxs[i] = (i&3)+8; 2579 break; 2580 case OP_VSPLTISW3: 2581 for (unsigned i = 0; i != 16; ++i) 2582 ShufIdxs[i] = (i&3)+12; 2583 break; 2584 case OP_VSLDOI4: 2585 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 2586 case OP_VSLDOI8: 2587 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 2588 case OP_VSLDOI12: 2589 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 2590 } 2591 SDOperand Ops[16]; 2592 for (unsigned i = 0; i != 16; ++i) 2593 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 2594 2595 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 2596 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2597} 2598 2599/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 2600/// is a shuffle we can handle in a single instruction, return it. Otherwise, 2601/// return the code it can be lowered into. Worst case, it can always be 2602/// lowered into a vperm. 2603static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 2604 SDOperand V1 = Op.getOperand(0); 2605 SDOperand V2 = Op.getOperand(1); 2606 SDOperand PermMask = Op.getOperand(2); 2607 2608 // Cases that are handled by instructions that take permute immediates 2609 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 2610 // selected by the instruction selector. 2611 if (V2.getOpcode() == ISD::UNDEF) { 2612 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 2613 PPC::isSplatShuffleMask(PermMask.Val, 2) || 2614 PPC::isSplatShuffleMask(PermMask.Val, 4) || 2615 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 2616 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 2617 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 2618 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 2619 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 2620 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 2621 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 2622 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 2623 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 2624 return Op; 2625 } 2626 } 2627 2628 // Altivec has a variety of "shuffle immediates" that take two vector inputs 2629 // and produce a fixed permutation. If any of these match, do not lower to 2630 // VPERM. 2631 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 2632 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 2633 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 2634 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 2635 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 2636 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 2637 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 2638 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 2639 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 2640 return Op; 2641 2642 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 2643 // perfect shuffle table to emit an optimal matching sequence. 2644 unsigned PFIndexes[4]; 2645 bool isFourElementShuffle = true; 2646 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 2647 unsigned EltNo = 8; // Start out undef. 2648 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 2649 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 2650 continue; // Undef, ignore it. 2651 2652 unsigned ByteSource = 2653 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 2654 if ((ByteSource & 3) != j) { 2655 isFourElementShuffle = false; 2656 break; 2657 } 2658 2659 if (EltNo == 8) { 2660 EltNo = ByteSource/4; 2661 } else if (EltNo != ByteSource/4) { 2662 isFourElementShuffle = false; 2663 break; 2664 } 2665 } 2666 PFIndexes[i] = EltNo; 2667 } 2668 2669 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 2670 // perfect shuffle vector to determine if it is cost effective to do this as 2671 // discrete instructions, or whether we should use a vperm. 2672 if (isFourElementShuffle) { 2673 // Compute the index in the perfect shuffle table. 2674 unsigned PFTableIndex = 2675 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2676 2677 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2678 unsigned Cost = (PFEntry >> 30); 2679 2680 // Determining when to avoid vperm is tricky. Many things affect the cost 2681 // of vperm, particularly how many times the perm mask needs to be computed. 2682 // For example, if the perm mask can be hoisted out of a loop or is already 2683 // used (perhaps because there are multiple permutes with the same shuffle 2684 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 2685 // the loop requires an extra register. 2686 // 2687 // As a compromise, we only emit discrete instructions if the shuffle can be 2688 // generated in 3 or fewer operations. When we have loop information 2689 // available, if this block is within a loop, we should avoid using vperm 2690 // for 3-operation perms and use a constant pool load instead. 2691 if (Cost < 3) 2692 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 2693 } 2694 2695 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 2696 // vector that will get spilled to the constant pool. 2697 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 2698 2699 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 2700 // that it is in input element units, not in bytes. Convert now. 2701 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); 2702 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 2703 2704 SmallVector<SDOperand, 16> ResultMask; 2705 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 2706 unsigned SrcElt; 2707 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 2708 SrcElt = 0; 2709 else 2710 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 2711 2712 for (unsigned j = 0; j != BytesPerElement; ++j) 2713 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 2714 MVT::i8)); 2715 } 2716 2717 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 2718 &ResultMask[0], ResultMask.size()); 2719 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 2720} 2721 2722/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 2723/// altivec comparison. If it is, return true and fill in Opc/isDot with 2724/// information about the intrinsic. 2725static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 2726 bool &isDot) { 2727 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 2728 CompareOpc = -1; 2729 isDot = false; 2730 switch (IntrinsicID) { 2731 default: return false; 2732 // Comparison predicates. 2733 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 2734 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 2735 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 2736 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 2737 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 2738 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 2739 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 2740 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 2741 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 2742 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 2743 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 2744 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 2745 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 2746 2747 // Normal Comparisons. 2748 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 2749 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 2750 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 2751 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 2752 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 2753 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 2754 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 2755 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 2756 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 2757 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 2758 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 2759 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 2760 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 2761 } 2762 return true; 2763} 2764 2765/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 2766/// lower, do it, otherwise return null. 2767static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 2768 // If this is a lowered altivec predicate compare, CompareOpc is set to the 2769 // opcode number of the comparison. 2770 int CompareOpc; 2771 bool isDot; 2772 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 2773 return SDOperand(); // Don't custom lower most intrinsics. 2774 2775 // If this is a non-dot comparison, make the VCMP node and we are done. 2776 if (!isDot) { 2777 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 2778 Op.getOperand(1), Op.getOperand(2), 2779 DAG.getConstant(CompareOpc, MVT::i32)); 2780 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 2781 } 2782 2783 // Create the PPCISD altivec 'dot' comparison node. 2784 SDOperand Ops[] = { 2785 Op.getOperand(2), // LHS 2786 Op.getOperand(3), // RHS 2787 DAG.getConstant(CompareOpc, MVT::i32) 2788 }; 2789 std::vector<MVT::ValueType> VTs; 2790 VTs.push_back(Op.getOperand(2).getValueType()); 2791 VTs.push_back(MVT::Flag); 2792 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2793 2794 // Now that we have the comparison, emit a copy from the CR to a GPR. 2795 // This is flagged to the above dot comparison. 2796 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 2797 DAG.getRegister(PPC::CR6, MVT::i32), 2798 CompNode.getValue(1)); 2799 2800 // Unpack the result based on how the target uses it. 2801 unsigned BitNo; // Bit # of CR6. 2802 bool InvertBit; // Invert result? 2803 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 2804 default: // Can't happen, don't crash on invalid number though. 2805 case 0: // Return the value of the EQ bit of CR6. 2806 BitNo = 0; InvertBit = false; 2807 break; 2808 case 1: // Return the inverted value of the EQ bit of CR6. 2809 BitNo = 0; InvertBit = true; 2810 break; 2811 case 2: // Return the value of the LT bit of CR6. 2812 BitNo = 2; InvertBit = false; 2813 break; 2814 case 3: // Return the inverted value of the LT bit of CR6. 2815 BitNo = 2; InvertBit = true; 2816 break; 2817 } 2818 2819 // Shift the bit into the low position. 2820 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 2821 DAG.getConstant(8-(3-BitNo), MVT::i32)); 2822 // Isolate the bit. 2823 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 2824 DAG.getConstant(1, MVT::i32)); 2825 2826 // If we are supposed to, toggle the bit. 2827 if (InvertBit) 2828 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 2829 DAG.getConstant(1, MVT::i32)); 2830 return Flags; 2831} 2832 2833static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2834 // Create a stack slot that is 16-byte aligned. 2835 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2836 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 2837 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2838 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2839 2840 // Store the input value into Value#0 of the stack slot. 2841 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 2842 Op.getOperand(0), FIdx, NULL, 0); 2843 // Load it out. 2844 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 2845} 2846 2847static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 2848 if (Op.getValueType() == MVT::v4i32) { 2849 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2850 2851 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 2852 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 2853 2854 SDOperand RHSSwap = // = vrlw RHS, 16 2855 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 2856 2857 // Shrinkify inputs to v8i16. 2858 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 2859 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 2860 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 2861 2862 // Low parts multiplied together, generating 32-bit results (we ignore the 2863 // top parts). 2864 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 2865 LHS, RHS, DAG, MVT::v4i32); 2866 2867 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 2868 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 2869 // Shift the high parts up 16 bits. 2870 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 2871 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 2872 } else if (Op.getValueType() == MVT::v8i16) { 2873 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2874 2875 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 2876 2877 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 2878 LHS, RHS, Zero, DAG); 2879 } else if (Op.getValueType() == MVT::v16i8) { 2880 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2881 2882 // Multiply the even 8-bit parts, producing 16-bit sums. 2883 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 2884 LHS, RHS, DAG, MVT::v8i16); 2885 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 2886 2887 // Multiply the odd 8-bit parts, producing 16-bit sums. 2888 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 2889 LHS, RHS, DAG, MVT::v8i16); 2890 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 2891 2892 // Merge the results together. 2893 SDOperand Ops[16]; 2894 for (unsigned i = 0; i != 8; ++i) { 2895 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 2896 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 2897 } 2898 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 2899 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2900 } else { 2901 assert(0 && "Unknown mul to lower!"); 2902 abort(); 2903 } 2904} 2905 2906/// LowerOperation - Provide custom lowering hooks for some operations. 2907/// 2908SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2909 switch (Op.getOpcode()) { 2910 default: assert(0 && "Wasn't expecting to be able to lower this!"); 2911 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2912 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2913 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 2914 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 2915 case ISD::SETCC: return LowerSETCC(Op, DAG); 2916 case ISD::VASTART: 2917 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 2918 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 2919 2920 case ISD::VAARG: 2921 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 2922 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 2923 2924 case ISD::FORMAL_ARGUMENTS: 2925 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, 2926 VarArgsStackOffset, VarArgsNumGPR, 2927 VarArgsNumFPR, PPCSubTarget); 2928 2929 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget); 2930 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); 2931 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 2932 case ISD::DYNAMIC_STACKALLOC: 2933 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 2934 2935 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 2936 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 2937 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 2938 2939 // Lower 64-bit shifts. 2940 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 2941 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 2942 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 2943 2944 // Vector-related lowering. 2945 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 2946 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 2947 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 2948 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 2949 case ISD::MUL: return LowerMUL(Op, DAG); 2950 2951 // Frame & Return address. Currently unimplemented 2952 case ISD::RETURNADDR: break; 2953 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 2954 } 2955 return SDOperand(); 2956} 2957 2958//===----------------------------------------------------------------------===// 2959// Other Lowering Code 2960//===----------------------------------------------------------------------===// 2961 2962MachineBasicBlock * 2963PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2964 MachineBasicBlock *BB) { 2965 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2966 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 2967 MI->getOpcode() == PPC::SELECT_CC_I8 || 2968 MI->getOpcode() == PPC::SELECT_CC_F4 || 2969 MI->getOpcode() == PPC::SELECT_CC_F8 || 2970 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 2971 "Unexpected instr type to insert"); 2972 2973 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 2974 // control-flow pattern. The incoming instruction knows the destination vreg 2975 // to set, the condition code register to branch on, the true/false values to 2976 // select between, and a branch opcode to use. 2977 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2978 ilist<MachineBasicBlock>::iterator It = BB; 2979 ++It; 2980 2981 // thisMBB: 2982 // ... 2983 // TrueVal = ... 2984 // cmpTY ccX, r1, r2 2985 // bCC copy1MBB 2986 // fallthrough --> copy0MBB 2987 MachineBasicBlock *thisMBB = BB; 2988 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 2989 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 2990 unsigned SelectPred = MI->getOperand(4).getImm(); 2991 BuildMI(BB, TII->get(PPC::BCC)) 2992 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 2993 MachineFunction *F = BB->getParent(); 2994 F->getBasicBlockList().insert(It, copy0MBB); 2995 F->getBasicBlockList().insert(It, sinkMBB); 2996 // Update machine-CFG edges by first adding all successors of the current 2997 // block to the new block which will contain the Phi node for the select. 2998 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 2999 e = BB->succ_end(); i != e; ++i) 3000 sinkMBB->addSuccessor(*i); 3001 // Next, remove all successors of the current block, and add the true 3002 // and fallthrough blocks as its successors. 3003 while(!BB->succ_empty()) 3004 BB->removeSuccessor(BB->succ_begin()); 3005 BB->addSuccessor(copy0MBB); 3006 BB->addSuccessor(sinkMBB); 3007 3008 // copy0MBB: 3009 // %FalseValue = ... 3010 // # fallthrough to sinkMBB 3011 BB = copy0MBB; 3012 3013 // Update machine-CFG edges 3014 BB->addSuccessor(sinkMBB); 3015 3016 // sinkMBB: 3017 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 3018 // ... 3019 BB = sinkMBB; 3020 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 3021 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 3022 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 3023 3024 delete MI; // The pseudo instruction is gone now. 3025 return BB; 3026} 3027 3028//===----------------------------------------------------------------------===// 3029// Target Optimization Hooks 3030//===----------------------------------------------------------------------===// 3031 3032SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 3033 DAGCombinerInfo &DCI) const { 3034 TargetMachine &TM = getTargetMachine(); 3035 SelectionDAG &DAG = DCI.DAG; 3036 switch (N->getOpcode()) { 3037 default: break; 3038 case PPCISD::SHL: 3039 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3040 if (C->getValue() == 0) // 0 << V -> 0. 3041 return N->getOperand(0); 3042 } 3043 break; 3044 case PPCISD::SRL: 3045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3046 if (C->getValue() == 0) // 0 >>u V -> 0. 3047 return N->getOperand(0); 3048 } 3049 break; 3050 case PPCISD::SRA: 3051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3052 if (C->getValue() == 0 || // 0 >>s V -> 0. 3053 C->isAllOnesValue()) // -1 >>s V -> -1. 3054 return N->getOperand(0); 3055 } 3056 break; 3057 3058 case ISD::SINT_TO_FP: 3059 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 3060 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 3061 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 3062 // We allow the src/dst to be either f32/f64, but the intermediate 3063 // type must be i64. 3064 if (N->getOperand(0).getValueType() == MVT::i64) { 3065 SDOperand Val = N->getOperand(0).getOperand(0); 3066 if (Val.getValueType() == MVT::f32) { 3067 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3068 DCI.AddToWorklist(Val.Val); 3069 } 3070 3071 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 3072 DCI.AddToWorklist(Val.Val); 3073 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 3074 DCI.AddToWorklist(Val.Val); 3075 if (N->getValueType(0) == MVT::f32) { 3076 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 3077 DCI.AddToWorklist(Val.Val); 3078 } 3079 return Val; 3080 } else if (N->getOperand(0).getValueType() == MVT::i32) { 3081 // If the intermediate type is i32, we can avoid the load/store here 3082 // too. 3083 } 3084 } 3085 } 3086 break; 3087 case ISD::STORE: 3088 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 3089 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 3090 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 3091 N->getOperand(1).getValueType() == MVT::i32) { 3092 SDOperand Val = N->getOperand(1).getOperand(0); 3093 if (Val.getValueType() == MVT::f32) { 3094 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3095 DCI.AddToWorklist(Val.Val); 3096 } 3097 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 3098 DCI.AddToWorklist(Val.Val); 3099 3100 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 3101 N->getOperand(2), N->getOperand(3)); 3102 DCI.AddToWorklist(Val.Val); 3103 return Val; 3104 } 3105 3106 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 3107 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 3108 N->getOperand(1).Val->hasOneUse() && 3109 (N->getOperand(1).getValueType() == MVT::i32 || 3110 N->getOperand(1).getValueType() == MVT::i16)) { 3111 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 3112 // Do an any-extend to 32-bits if this is a half-word input. 3113 if (BSwapOp.getValueType() == MVT::i16) 3114 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 3115 3116 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 3117 N->getOperand(2), N->getOperand(3), 3118 DAG.getValueType(N->getOperand(1).getValueType())); 3119 } 3120 break; 3121 case ISD::BSWAP: 3122 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 3123 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 3124 N->getOperand(0).hasOneUse() && 3125 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 3126 SDOperand Load = N->getOperand(0); 3127 LoadSDNode *LD = cast<LoadSDNode>(Load); 3128 // Create the byte-swapping load. 3129 std::vector<MVT::ValueType> VTs; 3130 VTs.push_back(MVT::i32); 3131 VTs.push_back(MVT::Other); 3132 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); 3133 SDOperand Ops[] = { 3134 LD->getChain(), // Chain 3135 LD->getBasePtr(), // Ptr 3136 SV, // SrcValue 3137 DAG.getValueType(N->getValueType(0)) // VT 3138 }; 3139 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 3140 3141 // If this is an i16 load, insert the truncate. 3142 SDOperand ResVal = BSLoad; 3143 if (N->getValueType(0) == MVT::i16) 3144 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 3145 3146 // First, combine the bswap away. This makes the value produced by the 3147 // load dead. 3148 DCI.CombineTo(N, ResVal); 3149 3150 // Next, combine the load away, we give it a bogus result value but a real 3151 // chain result. The result value is dead because the bswap is dead. 3152 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 3153 3154 // Return N so it doesn't get rechecked! 3155 return SDOperand(N, 0); 3156 } 3157 3158 break; 3159 case PPCISD::VCMP: { 3160 // If a VCMPo node already exists with exactly the same operands as this 3161 // node, use its result instead of this node (VCMPo computes both a CR6 and 3162 // a normal output). 3163 // 3164 if (!N->getOperand(0).hasOneUse() && 3165 !N->getOperand(1).hasOneUse() && 3166 !N->getOperand(2).hasOneUse()) { 3167 3168 // Scan all of the users of the LHS, looking for VCMPo's that match. 3169 SDNode *VCMPoNode = 0; 3170 3171 SDNode *LHSN = N->getOperand(0).Val; 3172 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 3173 UI != E; ++UI) 3174 if ((*UI)->getOpcode() == PPCISD::VCMPo && 3175 (*UI)->getOperand(1) == N->getOperand(1) && 3176 (*UI)->getOperand(2) == N->getOperand(2) && 3177 (*UI)->getOperand(0) == N->getOperand(0)) { 3178 VCMPoNode = *UI; 3179 break; 3180 } 3181 3182 // If there is no VCMPo node, or if the flag value has a single use, don't 3183 // transform this. 3184 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 3185 break; 3186 3187 // Look at the (necessarily single) use of the flag value. If it has a 3188 // chain, this transformation is more complex. Note that multiple things 3189 // could use the value result, which we should ignore. 3190 SDNode *FlagUser = 0; 3191 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 3192 FlagUser == 0; ++UI) { 3193 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 3194 SDNode *User = *UI; 3195 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 3196 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 3197 FlagUser = User; 3198 break; 3199 } 3200 } 3201 } 3202 3203 // If the user is a MFCR instruction, we know this is safe. Otherwise we 3204 // give up for right now. 3205 if (FlagUser->getOpcode() == PPCISD::MFCR) 3206 return SDOperand(VCMPoNode, 0); 3207 } 3208 break; 3209 } 3210 case ISD::BR_CC: { 3211 // If this is a branch on an altivec predicate comparison, lower this so 3212 // that we don't have to do a MFCR: instead, branch directly on CR6. This 3213 // lowering is done pre-legalize, because the legalizer lowers the predicate 3214 // compare down to code that is difficult to reassemble. 3215 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 3216 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 3217 int CompareOpc; 3218 bool isDot; 3219 3220 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 3221 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 3222 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 3223 assert(isDot && "Can't compare against a vector result!"); 3224 3225 // If this is a comparison against something other than 0/1, then we know 3226 // that the condition is never/always true. 3227 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 3228 if (Val != 0 && Val != 1) { 3229 if (CC == ISD::SETEQ) // Cond never true, remove branch. 3230 return N->getOperand(0); 3231 // Always !=, turn it into an unconditional branch. 3232 return DAG.getNode(ISD::BR, MVT::Other, 3233 N->getOperand(0), N->getOperand(4)); 3234 } 3235 3236 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 3237 3238 // Create the PPCISD altivec 'dot' comparison node. 3239 std::vector<MVT::ValueType> VTs; 3240 SDOperand Ops[] = { 3241 LHS.getOperand(2), // LHS of compare 3242 LHS.getOperand(3), // RHS of compare 3243 DAG.getConstant(CompareOpc, MVT::i32) 3244 }; 3245 VTs.push_back(LHS.getOperand(2).getValueType()); 3246 VTs.push_back(MVT::Flag); 3247 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 3248 3249 // Unpack the result based on how the target uses it. 3250 PPC::Predicate CompOpc; 3251 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 3252 default: // Can't happen, don't crash on invalid number though. 3253 case 0: // Branch on the value of the EQ bit of CR6. 3254 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 3255 break; 3256 case 1: // Branch on the inverted value of the EQ bit of CR6. 3257 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 3258 break; 3259 case 2: // Branch on the value of the LT bit of CR6. 3260 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 3261 break; 3262 case 3: // Branch on the inverted value of the LT bit of CR6. 3263 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 3264 break; 3265 } 3266 3267 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 3268 DAG.getConstant(CompOpc, MVT::i32), 3269 DAG.getRegister(PPC::CR6, MVT::i32), 3270 N->getOperand(4), CompNode.getValue(1)); 3271 } 3272 break; 3273 } 3274 } 3275 3276 return SDOperand(); 3277} 3278 3279//===----------------------------------------------------------------------===// 3280// Inline Assembly Support 3281//===----------------------------------------------------------------------===// 3282 3283void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 3284 uint64_t Mask, 3285 uint64_t &KnownZero, 3286 uint64_t &KnownOne, 3287 const SelectionDAG &DAG, 3288 unsigned Depth) const { 3289 KnownZero = 0; 3290 KnownOne = 0; 3291 switch (Op.getOpcode()) { 3292 default: break; 3293 case PPCISD::LBRX: { 3294 // lhbrx is known to have the top bits cleared out. 3295 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 3296 KnownZero = 0xFFFF0000; 3297 break; 3298 } 3299 case ISD::INTRINSIC_WO_CHAIN: { 3300 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 3301 default: break; 3302 case Intrinsic::ppc_altivec_vcmpbfp_p: 3303 case Intrinsic::ppc_altivec_vcmpeqfp_p: 3304 case Intrinsic::ppc_altivec_vcmpequb_p: 3305 case Intrinsic::ppc_altivec_vcmpequh_p: 3306 case Intrinsic::ppc_altivec_vcmpequw_p: 3307 case Intrinsic::ppc_altivec_vcmpgefp_p: 3308 case Intrinsic::ppc_altivec_vcmpgtfp_p: 3309 case Intrinsic::ppc_altivec_vcmpgtsb_p: 3310 case Intrinsic::ppc_altivec_vcmpgtsh_p: 3311 case Intrinsic::ppc_altivec_vcmpgtsw_p: 3312 case Intrinsic::ppc_altivec_vcmpgtub_p: 3313 case Intrinsic::ppc_altivec_vcmpgtuh_p: 3314 case Intrinsic::ppc_altivec_vcmpgtuw_p: 3315 KnownZero = ~1U; // All bits but the low one are known to be zero. 3316 break; 3317 } 3318 } 3319 } 3320} 3321 3322 3323/// getConstraintType - Given a constraint, return the type of 3324/// constraint it is for this target. 3325PPCTargetLowering::ConstraintType 3326PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 3327 if (Constraint.size() == 1) { 3328 switch (Constraint[0]) { 3329 default: break; 3330 case 'b': 3331 case 'r': 3332 case 'f': 3333 case 'v': 3334 case 'y': 3335 return C_RegisterClass; 3336 } 3337 } 3338 return TargetLowering::getConstraintType(Constraint); 3339} 3340 3341std::pair<unsigned, const TargetRegisterClass*> 3342PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3343 MVT::ValueType VT) const { 3344 if (Constraint.size() == 1) { 3345 // GCC RS6000 Constraint Letters 3346 switch (Constraint[0]) { 3347 case 'b': // R1-R31 3348 case 'r': // R0-R31 3349 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 3350 return std::make_pair(0U, PPC::G8RCRegisterClass); 3351 return std::make_pair(0U, PPC::GPRCRegisterClass); 3352 case 'f': 3353 if (VT == MVT::f32) 3354 return std::make_pair(0U, PPC::F4RCRegisterClass); 3355 else if (VT == MVT::f64) 3356 return std::make_pair(0U, PPC::F8RCRegisterClass); 3357 break; 3358 case 'v': 3359 return std::make_pair(0U, PPC::VRRCRegisterClass); 3360 case 'y': // crrc 3361 return std::make_pair(0U, PPC::CRRCRegisterClass); 3362 } 3363 } 3364 3365 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3366} 3367 3368 3369/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3370/// vector. If it is invalid, don't add anything to Ops. 3371void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter, 3372 std::vector<SDOperand>&Ops, 3373 SelectionDAG &DAG) { 3374 SDOperand Result(0,0); 3375 switch (Letter) { 3376 default: break; 3377 case 'I': 3378 case 'J': 3379 case 'K': 3380 case 'L': 3381 case 'M': 3382 case 'N': 3383 case 'O': 3384 case 'P': { 3385 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 3386 if (!CST) return; // Must be an immediate to match. 3387 unsigned Value = CST->getValue(); 3388 switch (Letter) { 3389 default: assert(0 && "Unknown constraint letter!"); 3390 case 'I': // "I" is a signed 16-bit constant. 3391 if ((short)Value == (int)Value) 3392 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3393 break; 3394 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 3395 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 3396 if ((short)Value == 0) 3397 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3398 break; 3399 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 3400 if ((Value >> 16) == 0) 3401 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3402 break; 3403 case 'M': // "M" is a constant that is greater than 31. 3404 if (Value > 31) 3405 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3406 break; 3407 case 'N': // "N" is a positive constant that is an exact power of two. 3408 if ((int)Value > 0 && isPowerOf2_32(Value)) 3409 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3410 break; 3411 case 'O': // "O" is the constant zero. 3412 if (Value == 0) 3413 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3414 break; 3415 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 3416 if ((short)-Value == (int)-Value) 3417 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3418 break; 3419 } 3420 break; 3421 } 3422 } 3423 3424 if (Result.Val) { 3425 Ops.push_back(Result); 3426 return; 3427 } 3428 3429 // Handle standard constraint letters. 3430 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); 3431} 3432 3433// isLegalAddressingMode - Return true if the addressing mode represented 3434// by AM is legal for this target, for a load/store of the specified type. 3435bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3436 const Type *Ty) const { 3437 // FIXME: PPC does not allow r+i addressing modes for vectors! 3438 3439 // PPC allows a sign-extended 16-bit immediate field. 3440 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3441 return false; 3442 3443 // No global is ever allowed as a base. 3444 if (AM.BaseGV) 3445 return false; 3446 3447 // PPC only support r+r, 3448 switch (AM.Scale) { 3449 case 0: // "r+i" or just "i", depending on HasBaseReg. 3450 break; 3451 case 1: 3452 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3453 return false; 3454 // Otherwise we have r+r or r+i. 3455 break; 3456 case 2: 3457 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3458 return false; 3459 // Allow 2*r as r+r. 3460 break; 3461 default: 3462 // No other scales are supported. 3463 return false; 3464 } 3465 3466 return true; 3467} 3468 3469/// isLegalAddressImmediate - Return true if the integer value can be used 3470/// as the offset of the target addressing mode for load / store of the 3471/// given type. 3472bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 3473 // PPC allows a sign-extended 16-bit immediate field. 3474 return (V > -(1 << 16) && V < (1 << 16)-1); 3475} 3476 3477bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 3478 return false; 3479} 3480 3481SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) 3482{ 3483 // Depths > 0 not supported yet! 3484 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3485 return SDOperand(); 3486 3487 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3488 bool isPPC64 = PtrVT == MVT::i64; 3489 3490 MachineFunction &MF = DAG.getMachineFunction(); 3491 MachineFrameInfo *MFI = MF.getFrameInfo(); 3492 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 3493 && MFI->getStackSize(); 3494 3495 if (isPPC64) 3496 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, 3497 MVT::i64); 3498 else 3499 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, 3500 MVT::i32); 3501} 3502