PPCISelLowering.cpp revision 6eaeff29b8a6990107735f7e5f5e49da38f56223
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/Analysis/ScalarEvolutionExpressions.h" 22#include "llvm/CodeGen/CallingConvLower.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Constants.h" 29#include "llvm/Function.h" 30#include "llvm/Intrinsics.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/Target/TargetOptions.h" 33#include "llvm/Support/CommandLine.h" 34using namespace llvm; 35 36static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 37cl::desc("enable preincrement load/store generation on PPC (experimental)"), 38 cl::Hidden); 39 40PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 41 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 42 43 setPow2DivIsCheap(); 44 45 // Use _setjmp/_longjmp instead of setjmp/longjmp. 46 setUseUnderscoreSetJmp(true); 47 setUseUnderscoreLongJmp(true); 48 49 // Set up the register classes. 50 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 51 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 52 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 53 54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 55 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 56 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 57 58 // PowerPC does not have truncstore for i1. 59 setStoreXAction(MVT::i1, Promote); 60 61 // PowerPC has pre-inc load and store's. 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 72 73 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 74 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 75 76 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) 77 setConvertAction(MVT::ppcf128, MVT::f64, Expand); 78 setConvertAction(MVT::ppcf128, MVT::f32, Expand); 79 // This is used in the ppcf128->int sequence. Note it has different semantics 80 // from FP_ROUND: that rounds to nearest, this rounds to zero. 81 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 82 83 // PowerPC has no intrinsics for these particular operations 84 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 85 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 86 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 87 88 // PowerPC has no SREM/UREM instructions 89 setOperationAction(ISD::SREM, MVT::i32, Expand); 90 setOperationAction(ISD::UREM, MVT::i32, Expand); 91 setOperationAction(ISD::SREM, MVT::i64, Expand); 92 setOperationAction(ISD::UREM, MVT::i64, Expand); 93 94 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 95 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 96 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 97 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 98 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 99 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 100 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 101 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 102 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 103 104 // We don't support sin/cos/sqrt/fmod 105 setOperationAction(ISD::FSIN , MVT::f64, Expand); 106 setOperationAction(ISD::FCOS , MVT::f64, Expand); 107 setOperationAction(ISD::FREM , MVT::f64, Expand); 108 setOperationAction(ISD::FSIN , MVT::f32, Expand); 109 setOperationAction(ISD::FCOS , MVT::f32, Expand); 110 setOperationAction(ISD::FREM , MVT::f32, Expand); 111 112 // If we're enabling GP optimizations, use hardware square root 113 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 114 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 115 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 116 } 117 118 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 119 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 120 121 // PowerPC does not have BSWAP, CTPOP or CTTZ 122 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 123 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 124 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 125 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 126 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 127 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 128 129 // PowerPC does not have ROTR 130 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 131 132 // PowerPC does not have Select 133 setOperationAction(ISD::SELECT, MVT::i32, Expand); 134 setOperationAction(ISD::SELECT, MVT::i64, Expand); 135 setOperationAction(ISD::SELECT, MVT::f32, Expand); 136 setOperationAction(ISD::SELECT, MVT::f64, Expand); 137 138 // PowerPC wants to turn select_cc of FP into fsel when possible. 139 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 140 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 141 142 // PowerPC wants to optimize integer setcc a bit 143 setOperationAction(ISD::SETCC, MVT::i32, Custom); 144 145 // PowerPC does not have BRCOND which requires SetCC 146 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 147 148 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 149 150 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 151 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 152 153 // PowerPC does not have [U|S]INT_TO_FP 154 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 155 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 156 157 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 158 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 159 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 160 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 161 162 // We cannot sextinreg(i1). Expand to shifts. 163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 164 165 // Support label based line numbers. 166 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 167 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 168 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) { 169 setOperationAction(ISD::LABEL, MVT::Other, Expand); 170 } else { 171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 172 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 174 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 175 } 176 177 // We want to legalize GlobalAddress and ConstantPool nodes into the 178 // appropriate instructions to materialize the address. 179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 180 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 182 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 183 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 184 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 185 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 186 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 187 188 // RET must be custom lowered, to meet ABI requirements 189 setOperationAction(ISD::RET , MVT::Other, Custom); 190 191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 192 setOperationAction(ISD::VASTART , MVT::Other, Custom); 193 194 // VAARG is custom lowered with ELF 32 ABI 195 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) 196 setOperationAction(ISD::VAARG, MVT::Other, Custom); 197 else 198 setOperationAction(ISD::VAARG, MVT::Other, Expand); 199 200 // Use the default implementation. 201 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 202 setOperationAction(ISD::VAEND , MVT::Other, Expand); 203 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 204 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 207 208 // We want to custom lower some of our intrinsics. 209 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 210 211 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 212 // They also have instructions for converting between i64 and fp. 213 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 214 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 215 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 217 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 218 219 // FIXME: disable this lowered code. This generates 64-bit register values, 220 // and we don't model the fact that the top part is clobbered by calls. We 221 // need to flag these together so that the value isn't live across a call. 222 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 223 224 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 226 } else { 227 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 228 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 229 } 230 231 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 232 // 64 bit PowerPC implementations can support i64 types directly 233 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 234 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 235 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 236 } else { 237 // 32 bit PowerPC wants to expand i64 shifts itself. 238 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 239 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 240 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 241 } 242 243 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 244 // First set operation action for all vector types to expand. Then we 245 // will selectively turn on ones that can be effectively codegen'd. 246 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 247 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 248 // add/sub are legal for all supported vector VT's. 249 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 250 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 251 252 // We promote all shuffles to v16i8. 253 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 254 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 255 256 // We promote all non-typed operations to v4i32. 257 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 258 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 259 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 260 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 261 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 262 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 263 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 264 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 265 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 266 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 267 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 268 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 269 270 // No other operations are legal. 271 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 272 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 273 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 274 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 275 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 276 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 277 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); 278 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 279 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 280 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 281 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); 282 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); 283 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); 284 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); 285 286 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 287 } 288 289 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 290 // with merges, splats, etc. 291 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 292 293 setOperationAction(ISD::AND , MVT::v4i32, Legal); 294 setOperationAction(ISD::OR , MVT::v4i32, Legal); 295 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 296 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 297 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 298 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 299 300 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 301 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 302 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 303 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 304 305 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 306 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 307 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 308 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 309 310 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 311 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 312 313 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 314 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 315 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 316 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 317 } 318 319 setSetCCResultType(MVT::i32); 320 setShiftAmountType(MVT::i32); 321 setSetCCResultContents(ZeroOrOneSetCCResult); 322 323 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 324 setStackPointerRegisterToSaveRestore(PPC::X1); 325 setExceptionPointerRegister(PPC::X3); 326 setExceptionSelectorRegister(PPC::X4); 327 } else { 328 setStackPointerRegisterToSaveRestore(PPC::R1); 329 setExceptionPointerRegister(PPC::R3); 330 setExceptionSelectorRegister(PPC::R4); 331 } 332 333 // We have target-specific dag combine patterns for the following nodes: 334 setTargetDAGCombine(ISD::SINT_TO_FP); 335 setTargetDAGCombine(ISD::STORE); 336 setTargetDAGCombine(ISD::BR_CC); 337 setTargetDAGCombine(ISD::BSWAP); 338 339 computeRegisterProperties(); 340} 341 342const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 343 switch (Opcode) { 344 default: return 0; 345 case PPCISD::FSEL: return "PPCISD::FSEL"; 346 case PPCISD::FCFID: return "PPCISD::FCFID"; 347 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 348 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 349 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 350 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 351 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 352 case PPCISD::VPERM: return "PPCISD::VPERM"; 353 case PPCISD::Hi: return "PPCISD::Hi"; 354 case PPCISD::Lo: return "PPCISD::Lo"; 355 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 356 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 357 case PPCISD::SRL: return "PPCISD::SRL"; 358 case PPCISD::SRA: return "PPCISD::SRA"; 359 case PPCISD::SHL: return "PPCISD::SHL"; 360 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 361 case PPCISD::STD_32: return "PPCISD::STD_32"; 362 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 363 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 364 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 365 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 366 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 367 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 368 case PPCISD::MFCR: return "PPCISD::MFCR"; 369 case PPCISD::VCMP: return "PPCISD::VCMP"; 370 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 371 case PPCISD::LBRX: return "PPCISD::LBRX"; 372 case PPCISD::STBRX: return "PPCISD::STBRX"; 373 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 374 } 375} 376 377//===----------------------------------------------------------------------===// 378// Node matching predicates, for use by the tblgen matching code. 379//===----------------------------------------------------------------------===// 380 381/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 382static bool isFloatingPointZero(SDOperand Op) { 383 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 384 return CFP->getValueAPF().isZero(); 385 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 386 // Maybe this has already been legalized into the constant pool? 387 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 388 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 389 return CFP->getValueAPF().isZero(); 390 } 391 return false; 392} 393 394/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 395/// true if Op is undef or if it matches the specified value. 396static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 397 return Op.getOpcode() == ISD::UNDEF || 398 cast<ConstantSDNode>(Op)->getValue() == Val; 399} 400 401/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 402/// VPKUHUM instruction. 403bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 404 if (!isUnary) { 405 for (unsigned i = 0; i != 16; ++i) 406 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 407 return false; 408 } else { 409 for (unsigned i = 0; i != 8; ++i) 410 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 411 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 412 return false; 413 } 414 return true; 415} 416 417/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 418/// VPKUWUM instruction. 419bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 420 if (!isUnary) { 421 for (unsigned i = 0; i != 16; i += 2) 422 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 423 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 424 return false; 425 } else { 426 for (unsigned i = 0; i != 8; i += 2) 427 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 428 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 429 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 430 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 431 return false; 432 } 433 return true; 434} 435 436/// isVMerge - Common function, used to match vmrg* shuffles. 437/// 438static bool isVMerge(SDNode *N, unsigned UnitSize, 439 unsigned LHSStart, unsigned RHSStart) { 440 assert(N->getOpcode() == ISD::BUILD_VECTOR && 441 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 442 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 443 "Unsupported merge size!"); 444 445 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 446 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 447 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 448 LHSStart+j+i*UnitSize) || 449 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 450 RHSStart+j+i*UnitSize)) 451 return false; 452 } 453 return true; 454} 455 456/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 457/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 458bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 459 if (!isUnary) 460 return isVMerge(N, UnitSize, 8, 24); 461 return isVMerge(N, UnitSize, 8, 8); 462} 463 464/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 465/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 466bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 467 if (!isUnary) 468 return isVMerge(N, UnitSize, 0, 16); 469 return isVMerge(N, UnitSize, 0, 0); 470} 471 472 473/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 474/// amount, otherwise return -1. 475int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 476 assert(N->getOpcode() == ISD::BUILD_VECTOR && 477 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 478 // Find the first non-undef value in the shuffle mask. 479 unsigned i; 480 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 481 /*search*/; 482 483 if (i == 16) return -1; // all undef. 484 485 // Otherwise, check to see if the rest of the elements are consequtively 486 // numbered from this value. 487 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 488 if (ShiftAmt < i) return -1; 489 ShiftAmt -= i; 490 491 if (!isUnary) { 492 // Check the rest of the elements to see if they are consequtive. 493 for (++i; i != 16; ++i) 494 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 495 return -1; 496 } else { 497 // Check the rest of the elements to see if they are consequtive. 498 for (++i; i != 16; ++i) 499 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 500 return -1; 501 } 502 503 return ShiftAmt; 504} 505 506/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 507/// specifies a splat of a single element that is suitable for input to 508/// VSPLTB/VSPLTH/VSPLTW. 509bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 510 assert(N->getOpcode() == ISD::BUILD_VECTOR && 511 N->getNumOperands() == 16 && 512 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 513 514 // This is a splat operation if each element of the permute is the same, and 515 // if the value doesn't reference the second vector. 516 unsigned ElementBase = 0; 517 SDOperand Elt = N->getOperand(0); 518 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 519 ElementBase = EltV->getValue(); 520 else 521 return false; // FIXME: Handle UNDEF elements too! 522 523 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 524 return false; 525 526 // Check that they are consequtive. 527 for (unsigned i = 1; i != EltSize; ++i) { 528 if (!isa<ConstantSDNode>(N->getOperand(i)) || 529 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 530 return false; 531 } 532 533 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 534 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 535 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 536 assert(isa<ConstantSDNode>(N->getOperand(i)) && 537 "Invalid VECTOR_SHUFFLE mask!"); 538 for (unsigned j = 0; j != EltSize; ++j) 539 if (N->getOperand(i+j) != N->getOperand(j)) 540 return false; 541 } 542 543 return true; 544} 545 546/// isAllNegativeZeroVector - Returns true if all elements of build_vector 547/// are -0.0. 548bool PPC::isAllNegativeZeroVector(SDNode *N) { 549 assert(N->getOpcode() == ISD::BUILD_VECTOR); 550 if (PPC::isSplatShuffleMask(N, N->getNumOperands())) 551 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) 552 return CFP->getValueAPF().isNegZero(); 553 return false; 554} 555 556/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 557/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 558unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 559 assert(isSplatShuffleMask(N, EltSize)); 560 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 561} 562 563/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 564/// by using a vspltis[bhw] instruction of the specified element size, return 565/// the constant being splatted. The ByteSize field indicates the number of 566/// bytes of each element [124] -> [bhw]. 567SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 568 SDOperand OpVal(0, 0); 569 570 // If ByteSize of the splat is bigger than the element size of the 571 // build_vector, then we have a case where we are checking for a splat where 572 // multiple elements of the buildvector are folded together into a single 573 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 574 unsigned EltSize = 16/N->getNumOperands(); 575 if (EltSize < ByteSize) { 576 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 577 SDOperand UniquedVals[4]; 578 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 579 580 // See if all of the elements in the buildvector agree across. 581 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 582 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 583 // If the element isn't a constant, bail fully out. 584 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 585 586 587 if (UniquedVals[i&(Multiple-1)].Val == 0) 588 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 589 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 590 return SDOperand(); // no match. 591 } 592 593 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 594 // either constant or undef values that are identical for each chunk. See 595 // if these chunks can form into a larger vspltis*. 596 597 // Check to see if all of the leading entries are either 0 or -1. If 598 // neither, then this won't fit into the immediate field. 599 bool LeadingZero = true; 600 bool LeadingOnes = true; 601 for (unsigned i = 0; i != Multiple-1; ++i) { 602 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 603 604 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 605 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 606 } 607 // Finally, check the least significant entry. 608 if (LeadingZero) { 609 if (UniquedVals[Multiple-1].Val == 0) 610 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 611 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 612 if (Val < 16) 613 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 614 } 615 if (LeadingOnes) { 616 if (UniquedVals[Multiple-1].Val == 0) 617 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 618 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 619 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 620 return DAG.getTargetConstant(Val, MVT::i32); 621 } 622 623 return SDOperand(); 624 } 625 626 // Check to see if this buildvec has a single non-undef value in its elements. 627 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 628 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 629 if (OpVal.Val == 0) 630 OpVal = N->getOperand(i); 631 else if (OpVal != N->getOperand(i)) 632 return SDOperand(); 633 } 634 635 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 636 637 unsigned ValSizeInBytes = 0; 638 uint64_t Value = 0; 639 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 640 Value = CN->getValue(); 641 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 642 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 643 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 644 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 645 ValSizeInBytes = 4; 646 } 647 648 // If the splat value is larger than the element value, then we can never do 649 // this splat. The only case that we could fit the replicated bits into our 650 // immediate field for would be zero, and we prefer to use vxor for it. 651 if (ValSizeInBytes < ByteSize) return SDOperand(); 652 653 // If the element value is larger than the splat value, cut it in half and 654 // check to see if the two halves are equal. Continue doing this until we 655 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 656 while (ValSizeInBytes > ByteSize) { 657 ValSizeInBytes >>= 1; 658 659 // If the top half equals the bottom half, we're still ok. 660 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 661 (Value & ((1 << (8*ValSizeInBytes))-1))) 662 return SDOperand(); 663 } 664 665 // Properly sign extend the value. 666 int ShAmt = (4-ByteSize)*8; 667 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 668 669 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 670 if (MaskVal == 0) return SDOperand(); 671 672 // Finally, if this value fits in a 5 bit sext field, return it 673 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 674 return DAG.getTargetConstant(MaskVal, MVT::i32); 675 return SDOperand(); 676} 677 678//===----------------------------------------------------------------------===// 679// Addressing Mode Selection 680//===----------------------------------------------------------------------===// 681 682/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 683/// or 64-bit immediate, and if the value can be accurately represented as a 684/// sign extension from a 16-bit value. If so, this returns true and the 685/// immediate. 686static bool isIntS16Immediate(SDNode *N, short &Imm) { 687 if (N->getOpcode() != ISD::Constant) 688 return false; 689 690 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 691 if (N->getValueType(0) == MVT::i32) 692 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 693 else 694 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 695} 696static bool isIntS16Immediate(SDOperand Op, short &Imm) { 697 return isIntS16Immediate(Op.Val, Imm); 698} 699 700 701/// SelectAddressRegReg - Given the specified addressed, check to see if it 702/// can be represented as an indexed [r+r] operation. Returns false if it 703/// can be more efficiently represented with [r+imm]. 704bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, 705 SDOperand &Index, 706 SelectionDAG &DAG) { 707 short imm = 0; 708 if (N.getOpcode() == ISD::ADD) { 709 if (isIntS16Immediate(N.getOperand(1), imm)) 710 return false; // r+i 711 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 712 return false; // r+i 713 714 Base = N.getOperand(0); 715 Index = N.getOperand(1); 716 return true; 717 } else if (N.getOpcode() == ISD::OR) { 718 if (isIntS16Immediate(N.getOperand(1), imm)) 719 return false; // r+i can fold it if we can. 720 721 // If this is an or of disjoint bitfields, we can codegen this as an add 722 // (for better address arithmetic) if the LHS and RHS of the OR are provably 723 // disjoint. 724 uint64_t LHSKnownZero, LHSKnownOne; 725 uint64_t RHSKnownZero, RHSKnownOne; 726 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 727 728 if (LHSKnownZero) { 729 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); 730 // If all of the bits are known zero on the LHS or RHS, the add won't 731 // carry. 732 if ((LHSKnownZero | RHSKnownZero) == ~0U) { 733 Base = N.getOperand(0); 734 Index = N.getOperand(1); 735 return true; 736 } 737 } 738 } 739 740 return false; 741} 742 743/// Returns true if the address N can be represented by a base register plus 744/// a signed 16-bit displacement [r+imm], and if it is not better 745/// represented as reg+reg. 746bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, 747 SDOperand &Base, SelectionDAG &DAG){ 748 // If this can be more profitably realized as r+r, fail. 749 if (SelectAddressRegReg(N, Disp, Base, DAG)) 750 return false; 751 752 if (N.getOpcode() == ISD::ADD) { 753 short imm = 0; 754 if (isIntS16Immediate(N.getOperand(1), imm)) { 755 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 756 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 757 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 758 } else { 759 Base = N.getOperand(0); 760 } 761 return true; // [r+i] 762 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 763 // Match LOAD (ADD (X, Lo(G))). 764 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 765 && "Cannot handle constant offsets yet!"); 766 Disp = N.getOperand(1).getOperand(0); // The global address. 767 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 768 Disp.getOpcode() == ISD::TargetConstantPool || 769 Disp.getOpcode() == ISD::TargetJumpTable); 770 Base = N.getOperand(0); 771 return true; // [&g+r] 772 } 773 } else if (N.getOpcode() == ISD::OR) { 774 short imm = 0; 775 if (isIntS16Immediate(N.getOperand(1), imm)) { 776 // If this is an or of disjoint bitfields, we can codegen this as an add 777 // (for better address arithmetic) if the LHS and RHS of the OR are 778 // provably disjoint. 779 uint64_t LHSKnownZero, LHSKnownOne; 780 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 781 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 782 // If all of the bits are known zero on the LHS or RHS, the add won't 783 // carry. 784 Base = N.getOperand(0); 785 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 786 return true; 787 } 788 } 789 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 790 // Loading from a constant address. 791 792 // If this address fits entirely in a 16-bit sext immediate field, codegen 793 // this as "d, 0" 794 short Imm; 795 if (isIntS16Immediate(CN, Imm)) { 796 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 797 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 798 return true; 799 } 800 801 // Handle 32-bit sext immediates with LIS + addr mode. 802 if (CN->getValueType(0) == MVT::i32 || 803 (int64_t)CN->getValue() == (int)CN->getValue()) { 804 int Addr = (int)CN->getValue(); 805 806 // Otherwise, break this down into an LIS + disp. 807 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 808 809 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 810 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 811 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 812 return true; 813 } 814 } 815 816 Disp = DAG.getTargetConstant(0, getPointerTy()); 817 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 818 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 819 else 820 Base = N; 821 return true; // [r+0] 822} 823 824/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 825/// represented as an indexed [r+r] operation. 826bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, 827 SDOperand &Index, 828 SelectionDAG &DAG) { 829 // Check to see if we can easily represent this as an [r+r] address. This 830 // will fail if it thinks that the address is more profitably represented as 831 // reg+imm, e.g. where imm = 0. 832 if (SelectAddressRegReg(N, Base, Index, DAG)) 833 return true; 834 835 // If the operand is an addition, always emit this as [r+r], since this is 836 // better (for code size, and execution, as the memop does the add for free) 837 // than emitting an explicit add. 838 if (N.getOpcode() == ISD::ADD) { 839 Base = N.getOperand(0); 840 Index = N.getOperand(1); 841 return true; 842 } 843 844 // Otherwise, do it the hard way, using R0 as the base register. 845 Base = DAG.getRegister(PPC::R0, N.getValueType()); 846 Index = N; 847 return true; 848} 849 850/// SelectAddressRegImmShift - Returns true if the address N can be 851/// represented by a base register plus a signed 14-bit displacement 852/// [r+imm*4]. Suitable for use by STD and friends. 853bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, 854 SDOperand &Base, 855 SelectionDAG &DAG) { 856 // If this can be more profitably realized as r+r, fail. 857 if (SelectAddressRegReg(N, Disp, Base, DAG)) 858 return false; 859 860 if (N.getOpcode() == ISD::ADD) { 861 short imm = 0; 862 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 863 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 864 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 865 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 866 } else { 867 Base = N.getOperand(0); 868 } 869 return true; // [r+i] 870 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 871 // Match LOAD (ADD (X, Lo(G))). 872 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 873 && "Cannot handle constant offsets yet!"); 874 Disp = N.getOperand(1).getOperand(0); // The global address. 875 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 876 Disp.getOpcode() == ISD::TargetConstantPool || 877 Disp.getOpcode() == ISD::TargetJumpTable); 878 Base = N.getOperand(0); 879 return true; // [&g+r] 880 } 881 } else if (N.getOpcode() == ISD::OR) { 882 short imm = 0; 883 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 884 // If this is an or of disjoint bitfields, we can codegen this as an add 885 // (for better address arithmetic) if the LHS and RHS of the OR are 886 // provably disjoint. 887 uint64_t LHSKnownZero, LHSKnownOne; 888 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 889 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 890 // If all of the bits are known zero on the LHS or RHS, the add won't 891 // carry. 892 Base = N.getOperand(0); 893 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 894 return true; 895 } 896 } 897 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 898 // Loading from a constant address. Verify low two bits are clear. 899 if ((CN->getValue() & 3) == 0) { 900 // If this address fits entirely in a 14-bit sext immediate field, codegen 901 // this as "d, 0" 902 short Imm; 903 if (isIntS16Immediate(CN, Imm)) { 904 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 905 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 906 return true; 907 } 908 909 // Fold the low-part of 32-bit absolute addresses into addr mode. 910 if (CN->getValueType(0) == MVT::i32 || 911 (int64_t)CN->getValue() == (int)CN->getValue()) { 912 int Addr = (int)CN->getValue(); 913 914 // Otherwise, break this down into an LIS + disp. 915 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 916 917 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 918 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 919 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 920 return true; 921 } 922 } 923 } 924 925 Disp = DAG.getTargetConstant(0, getPointerTy()); 926 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 927 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 928 else 929 Base = N; 930 return true; // [r+0] 931} 932 933 934/// getPreIndexedAddressParts - returns true by value, base pointer and 935/// offset pointer and addressing mode by reference if the node's address 936/// can be legally represented as pre-indexed load / store address. 937bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 938 SDOperand &Offset, 939 ISD::MemIndexedMode &AM, 940 SelectionDAG &DAG) { 941 // Disabled by default for now. 942 if (!EnablePPCPreinc) return false; 943 944 SDOperand Ptr; 945 MVT::ValueType VT; 946 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 947 Ptr = LD->getBasePtr(); 948 VT = LD->getLoadedVT(); 949 950 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 951 ST = ST; 952 Ptr = ST->getBasePtr(); 953 VT = ST->getStoredVT(); 954 } else 955 return false; 956 957 // PowerPC doesn't have preinc load/store instructions for vectors. 958 if (MVT::isVector(VT)) 959 return false; 960 961 // TODO: Check reg+reg first. 962 963 // LDU/STU use reg+imm*4, others use reg+imm. 964 if (VT != MVT::i64) { 965 // reg + imm 966 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 967 return false; 968 } else { 969 // reg + imm * 4. 970 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 971 return false; 972 } 973 974 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 975 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 976 // sext i32 to i64 when addr mode is r+i. 977 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 && 978 LD->getExtensionType() == ISD::SEXTLOAD && 979 isa<ConstantSDNode>(Offset)) 980 return false; 981 } 982 983 AM = ISD::PRE_INC; 984 return true; 985} 986 987//===----------------------------------------------------------------------===// 988// LowerOperation implementation 989//===----------------------------------------------------------------------===// 990 991static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 992 MVT::ValueType PtrVT = Op.getValueType(); 993 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 994 Constant *C = CP->getConstVal(); 995 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 996 SDOperand Zero = DAG.getConstant(0, PtrVT); 997 998 const TargetMachine &TM = DAG.getTarget(); 999 1000 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 1001 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 1002 1003 // If this is a non-darwin platform, we don't support non-static relo models 1004 // yet. 1005 if (TM.getRelocationModel() == Reloc::Static || 1006 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1007 // Generate non-pic code that has direct accesses to the constant pool. 1008 // The address of the global is just (hi(&g)+lo(&g)). 1009 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1010 } 1011 1012 if (TM.getRelocationModel() == Reloc::PIC_) { 1013 // With PIC, the first instruction is actually "GR+hi(&G)". 1014 Hi = DAG.getNode(ISD::ADD, PtrVT, 1015 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1016 } 1017 1018 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1019 return Lo; 1020} 1021 1022static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 1023 MVT::ValueType PtrVT = Op.getValueType(); 1024 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1025 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1026 SDOperand Zero = DAG.getConstant(0, PtrVT); 1027 1028 const TargetMachine &TM = DAG.getTarget(); 1029 1030 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 1031 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 1032 1033 // If this is a non-darwin platform, we don't support non-static relo models 1034 // yet. 1035 if (TM.getRelocationModel() == Reloc::Static || 1036 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1037 // Generate non-pic code that has direct accesses to the constant pool. 1038 // The address of the global is just (hi(&g)+lo(&g)). 1039 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1040 } 1041 1042 if (TM.getRelocationModel() == Reloc::PIC_) { 1043 // With PIC, the first instruction is actually "GR+hi(&G)". 1044 Hi = DAG.getNode(ISD::ADD, PtrVT, 1045 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1046 } 1047 1048 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1049 return Lo; 1050} 1051 1052static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 1053 assert(0 && "TLS not implemented for PPC."); 1054} 1055 1056static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 1057 MVT::ValueType PtrVT = Op.getValueType(); 1058 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1059 GlobalValue *GV = GSDN->getGlobal(); 1060 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1061 SDOperand Zero = DAG.getConstant(0, PtrVT); 1062 1063 const TargetMachine &TM = DAG.getTarget(); 1064 1065 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 1066 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1067 1068 // If this is a non-darwin platform, we don't support non-static relo models 1069 // yet. 1070 if (TM.getRelocationModel() == Reloc::Static || 1071 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1072 // Generate non-pic code that has direct accesses to globals. 1073 // The address of the global is just (hi(&g)+lo(&g)). 1074 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1075 } 1076 1077 if (TM.getRelocationModel() == Reloc::PIC_) { 1078 // With PIC, the first instruction is actually "GR+hi(&G)". 1079 Hi = DAG.getNode(ISD::ADD, PtrVT, 1080 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1081 } 1082 1083 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1084 1085 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1086 return Lo; 1087 1088 // If the global is weak or external, we have to go through the lazy 1089 // resolution stub. 1090 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1091} 1092 1093static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 1094 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1095 1096 // If we're comparing for equality to zero, expose the fact that this is 1097 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1098 // fold the new nodes. 1099 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1100 if (C->isNullValue() && CC == ISD::SETEQ) { 1101 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1102 SDOperand Zext = Op.getOperand(0); 1103 if (VT < MVT::i32) { 1104 VT = MVT::i32; 1105 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1106 } 1107 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1108 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1109 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1110 DAG.getConstant(Log2b, MVT::i32)); 1111 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1112 } 1113 // Leave comparisons against 0 and -1 alone for now, since they're usually 1114 // optimized. FIXME: revisit this when we can custom lower all setcc 1115 // optimizations. 1116 if (C->isAllOnesValue() || C->isNullValue()) 1117 return SDOperand(); 1118 } 1119 1120 // If we have an integer seteq/setne, turn it into a compare against zero 1121 // by xor'ing the rhs with the lhs, which is faster than setting a 1122 // condition register, reading it back out, and masking the correct bit. The 1123 // normal approach here uses sub to do this instead of xor. Using xor exposes 1124 // the result to other bit-twiddling opportunities. 1125 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1126 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1127 MVT::ValueType VT = Op.getValueType(); 1128 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1129 Op.getOperand(1)); 1130 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1131 } 1132 return SDOperand(); 1133} 1134 1135static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, 1136 int VarArgsFrameIndex, 1137 int VarArgsStackOffset, 1138 unsigned VarArgsNumGPR, 1139 unsigned VarArgsNumFPR, 1140 const PPCSubtarget &Subtarget) { 1141 1142 assert(0 && "VAARG in ELF32 ABI not implemented yet!"); 1143} 1144 1145static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 1146 int VarArgsFrameIndex, 1147 int VarArgsStackOffset, 1148 unsigned VarArgsNumGPR, 1149 unsigned VarArgsNumFPR, 1150 const PPCSubtarget &Subtarget) { 1151 1152 if (Subtarget.isMachoABI()) { 1153 // vastart just stores the address of the VarArgsFrameIndex slot into the 1154 // memory location argument. 1155 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1156 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1157 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1158 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 1159 SV->getOffset()); 1160 } 1161 1162 // For ELF 32 ABI we follow the layout of the va_list struct. 1163 // We suppose the given va_list is already allocated. 1164 // 1165 // typedef struct { 1166 // char gpr; /* index into the array of 8 GPRs 1167 // * stored in the register save area 1168 // * gpr=0 corresponds to r3, 1169 // * gpr=1 to r4, etc. 1170 // */ 1171 // char fpr; /* index into the array of 8 FPRs 1172 // * stored in the register save area 1173 // * fpr=0 corresponds to f1, 1174 // * fpr=1 to f2, etc. 1175 // */ 1176 // char *overflow_arg_area; 1177 // /* location on stack that holds 1178 // * the next overflow argument 1179 // */ 1180 // char *reg_save_area; 1181 // /* where r3:r10 and f1:f8 (if saved) 1182 // * are stored 1183 // */ 1184 // } va_list[1]; 1185 1186 1187 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); 1188 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); 1189 1190 1191 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1192 1193 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1194 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1195 1196 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, 1197 PtrVT); 1198 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1, 1199 PtrVT); 1200 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT); 1201 1202 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1203 1204 // Store first byte : number of int regs 1205 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, 1206 Op.getOperand(1), SV->getValue(), 1207 SV->getOffset()); 1208 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), 1209 ConstFPROffset); 1210 1211 // Store second byte : number of float regs 1212 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, 1213 SV->getValue(), SV->getOffset()); 1214 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); 1215 1216 // Store second word : arguments given on stack 1217 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr, 1218 SV->getValue(), SV->getOffset()); 1219 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); 1220 1221 // Store third word : arguments given in registers 1222 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(), 1223 SV->getOffset()); 1224 1225} 1226 1227#include "PPCGenCallingConv.inc" 1228 1229/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1230/// depending on which subtarget is selected. 1231static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1232 if (Subtarget.isMachoABI()) { 1233 static const unsigned FPR[] = { 1234 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1235 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1236 }; 1237 return FPR; 1238 } 1239 1240 1241 static const unsigned FPR[] = { 1242 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1243 PPC::F8 1244 }; 1245 return FPR; 1246} 1247 1248static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 1249 int &VarArgsFrameIndex, 1250 int &VarArgsStackOffset, 1251 unsigned &VarArgsNumGPR, 1252 unsigned &VarArgsNumFPR, 1253 const PPCSubtarget &Subtarget) { 1254 // TODO: add description of PPC stack frame format, or at least some docs. 1255 // 1256 MachineFunction &MF = DAG.getMachineFunction(); 1257 MachineFrameInfo *MFI = MF.getFrameInfo(); 1258 SSARegMap *RegMap = MF.getSSARegMap(); 1259 SmallVector<SDOperand, 8> ArgValues; 1260 SDOperand Root = Op.getOperand(0); 1261 1262 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1263 bool isPPC64 = PtrVT == MVT::i64; 1264 bool isMachoABI = Subtarget.isMachoABI(); 1265 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1266 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1267 1268 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1269 1270 static const unsigned GPR_32[] = { // 32-bit registers. 1271 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1272 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1273 }; 1274 static const unsigned GPR_64[] = { // 64-bit registers. 1275 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1276 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1277 }; 1278 1279 static const unsigned *FPR = GetFPR(Subtarget); 1280 1281 static const unsigned VR[] = { 1282 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1283 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1284 }; 1285 1286 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1287 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; 1288 const unsigned Num_VR_Regs = array_lengthof( VR); 1289 1290 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1291 1292 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1293 1294 // Add DAG nodes to load the arguments or copy them out of registers. On 1295 // entry to a function on PPC, the arguments start after the linkage area, 1296 // although the first ones are often in registers. 1297 // 1298 // In the ELF 32 ABI, GPRs and stack are double word align: an argument 1299 // represented with two words (long long or double) must be copied to an 1300 // even GPR_idx value or to an even ArgOffset value. 1301 1302 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1303 SDOperand ArgVal; 1304 bool needsLoad = false; 1305 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 1306 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 1307 unsigned ArgSize = ObjSize; 1308 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue(); 1309 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1310 // See if next argument requires stack alignment in ELF 1311 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) && 1312 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) && 1313 (!(Flags & AlignFlag))); 1314 1315 unsigned CurArgOffset = ArgOffset; 1316 switch (ObjectVT) { 1317 default: assert(0 && "Unhandled argument type!"); 1318 case MVT::i32: 1319 // Double word align in ELF 1320 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1321 if (GPR_idx != Num_GPR_Regs) { 1322 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1323 MF.addLiveIn(GPR[GPR_idx], VReg); 1324 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1325 ++GPR_idx; 1326 } else { 1327 needsLoad = true; 1328 ArgSize = PtrByteSize; 1329 } 1330 // Stack align in ELF 1331 if (needsLoad && Expand && isELF32_ABI) 1332 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1333 // All int arguments reserve stack space in Macho ABI. 1334 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1335 break; 1336 1337 case MVT::i64: // PPC64 1338 if (GPR_idx != Num_GPR_Regs) { 1339 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1340 MF.addLiveIn(GPR[GPR_idx], VReg); 1341 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1342 ++GPR_idx; 1343 } else { 1344 needsLoad = true; 1345 } 1346 // All int arguments reserve stack space in Macho ABI. 1347 if (isMachoABI || needsLoad) ArgOffset += 8; 1348 break; 1349 1350 case MVT::f32: 1351 case MVT::f64: 1352 // Every 4 bytes of argument space consumes one of the GPRs available for 1353 // argument passing. 1354 if (GPR_idx != Num_GPR_Regs && isMachoABI) { 1355 ++GPR_idx; 1356 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1357 ++GPR_idx; 1358 } 1359 if (FPR_idx != Num_FPR_Regs) { 1360 unsigned VReg; 1361 if (ObjectVT == MVT::f32) 1362 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 1363 else 1364 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1365 MF.addLiveIn(FPR[FPR_idx], VReg); 1366 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1367 ++FPR_idx; 1368 } else { 1369 needsLoad = true; 1370 } 1371 1372 // Stack align in ELF 1373 if (needsLoad && Expand && isELF32_ABI) 1374 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1375 // All FP arguments reserve stack space in Macho ABI. 1376 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1377 break; 1378 case MVT::v4f32: 1379 case MVT::v4i32: 1380 case MVT::v8i16: 1381 case MVT::v16i8: 1382 // Note that vector arguments in registers don't reserve stack space. 1383 if (VR_idx != Num_VR_Regs) { 1384 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); 1385 MF.addLiveIn(VR[VR_idx], VReg); 1386 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1387 ++VR_idx; 1388 } else { 1389 // This should be simple, but requires getting 16-byte aligned stack 1390 // values. 1391 assert(0 && "Loading VR argument not implemented yet!"); 1392 needsLoad = true; 1393 } 1394 break; 1395 } 1396 1397 // We need to load the argument to a virtual register if we determined above 1398 // that we ran out of physical registers of the appropriate type 1399 if (needsLoad) { 1400 // If the argument is actually used, emit a load from the right stack 1401 // slot. 1402 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 1403 int FI = MFI->CreateFixedObject(ObjSize, 1404 CurArgOffset + (ArgSize - ObjSize)); 1405 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1406 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1407 } else { 1408 // Don't emit a dead load. 1409 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); 1410 } 1411 } 1412 1413 ArgValues.push_back(ArgVal); 1414 } 1415 1416 // If the function takes variable number of arguments, make a frame index for 1417 // the start of the first vararg value... for expansion of llvm.va_start. 1418 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1419 if (isVarArg) { 1420 1421 int depth; 1422 if (isELF32_ABI) { 1423 VarArgsNumGPR = GPR_idx; 1424 VarArgsNumFPR = FPR_idx; 1425 1426 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame 1427 // pointer. 1428 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 + 1429 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 + 1430 MVT::getSizeInBits(PtrVT)/8); 1431 1432 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1433 ArgOffset); 1434 1435 } 1436 else 1437 depth = ArgOffset; 1438 1439 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1440 depth); 1441 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1442 1443 SmallVector<SDOperand, 8> MemOps; 1444 1445 // In ELF 32 ABI, the fixed integer arguments of a variadic function are 1446 // stored to the VarArgsFrameIndex on the stack. 1447 if (isELF32_ABI) { 1448 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { 1449 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT); 1450 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1451 MemOps.push_back(Store); 1452 // Increment the address by four for the next argument to store 1453 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1454 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1455 } 1456 } 1457 1458 // If this function is vararg, store any remaining integer argument regs 1459 // to their spots on the stack so that they may be loaded by deferencing the 1460 // result of va_next. 1461 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1462 unsigned VReg; 1463 if (isPPC64) 1464 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1465 else 1466 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1467 1468 MF.addLiveIn(GPR[GPR_idx], VReg); 1469 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1470 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1471 MemOps.push_back(Store); 1472 // Increment the address by four for the next argument to store 1473 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1474 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1475 } 1476 1477 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex 1478 // on the stack. 1479 if (isELF32_ABI) { 1480 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { 1481 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); 1482 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1483 MemOps.push_back(Store); 1484 // Increment the address by eight for the next argument to store 1485 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1486 PtrVT); 1487 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1488 } 1489 1490 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { 1491 unsigned VReg; 1492 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1493 1494 MF.addLiveIn(FPR[FPR_idx], VReg); 1495 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); 1496 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1497 MemOps.push_back(Store); 1498 // Increment the address by eight for the next argument to store 1499 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1500 PtrVT); 1501 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1502 } 1503 } 1504 1505 if (!MemOps.empty()) 1506 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1507 } 1508 1509 ArgValues.push_back(Root); 1510 1511 // Return the new list of results. 1512 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1513 Op.Val->value_end()); 1514 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1515} 1516 1517/// isCallCompatibleAddress - Return the immediate to use if the specified 1518/// 32-bit value is representable in the immediate field of a BxA instruction. 1519static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 1520 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1521 if (!C) return 0; 1522 1523 int Addr = C->getValue(); 1524 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1525 (Addr << 6 >> 6) != Addr) 1526 return 0; // Top 6 bits have to be sext of immediate. 1527 1528 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val; 1529} 1530 1531 1532static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, 1533 const PPCSubtarget &Subtarget) { 1534 SDOperand Chain = Op.getOperand(0); 1535 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1536 SDOperand Callee = Op.getOperand(4); 1537 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1538 1539 bool isMachoABI = Subtarget.isMachoABI(); 1540 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1541 1542 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1543 bool isPPC64 = PtrVT == MVT::i64; 1544 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1545 1546 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1547 // SelectExpr to use to put the arguments in the appropriate registers. 1548 std::vector<SDOperand> args_to_use; 1549 1550 // Count how many bytes are to be pushed on the stack, including the linkage 1551 // area, and parameter passing area. We start with 24/48 bytes, which is 1552 // prereserved space for [SP][CR][LR][3 x unused]. 1553 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1554 1555 // Add up all the space actually used. 1556 for (unsigned i = 0; i != NumOps; ++i) { 1557 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 1558 ArgSize = std::max(ArgSize, PtrByteSize); 1559 NumBytes += ArgSize; 1560 } 1561 1562 // The prolog code of the callee may store up to 8 GPR argument registers to 1563 // the stack, allowing va_start to index over them in memory if its varargs. 1564 // Because we cannot tell if this is needed on the caller side, we have to 1565 // conservatively assume that it is needed. As such, make sure we have at 1566 // least enough stack space for the caller to store the 8 GPRs. 1567 NumBytes = std::max(NumBytes, 1568 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1569 1570 // Adjust the stack pointer for the new arguments... 1571 // These operations are automatically eliminated by the prolog/epilog pass 1572 Chain = DAG.getCALLSEQ_START(Chain, 1573 DAG.getConstant(NumBytes, PtrVT)); 1574 1575 // Set up a copy of the stack pointer for use loading and storing any 1576 // arguments that may not fit in the registers available for argument 1577 // passing. 1578 SDOperand StackPtr; 1579 if (isPPC64) 1580 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 1581 else 1582 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1583 1584 // Figure out which arguments are going to go in registers, and which in 1585 // memory. Also, if this is a vararg function, floating point operations 1586 // must be stored to our stack, and loaded into integer regs as well, if 1587 // any integer regs are available for argument passing. 1588 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1589 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1590 1591 static const unsigned GPR_32[] = { // 32-bit registers. 1592 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1593 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1594 }; 1595 static const unsigned GPR_64[] = { // 64-bit registers. 1596 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1597 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1598 }; 1599 static const unsigned *FPR = GetFPR(Subtarget); 1600 1601 static const unsigned VR[] = { 1602 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1603 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1604 }; 1605 const unsigned NumGPRs = array_lengthof(GPR_32); 1606 const unsigned NumFPRs = isMachoABI ? 13 : 8; 1607 const unsigned NumVRs = array_lengthof( VR); 1608 1609 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1610 1611 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1612 SmallVector<SDOperand, 8> MemOpChains; 1613 for (unsigned i = 0; i != NumOps; ++i) { 1614 bool inMem = false; 1615 SDOperand Arg = Op.getOperand(5+2*i); 1616 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1617 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1618 // See if next argument requires stack alignment in ELF 1619 unsigned next = 5+2*(i+1)+1; 1620 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) && 1621 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) && 1622 (!(Flags & AlignFlag))); 1623 1624 // PtrOff will be used to store the current argument to the stack if a 1625 // register cannot be found for it. 1626 SDOperand PtrOff; 1627 1628 // Stack align in ELF 32 1629 if (isELF32_ABI && Expand) 1630 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, 1631 StackPtr.getValueType()); 1632 else 1633 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1634 1635 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1636 1637 // On PPC64, promote integers to 64-bit values. 1638 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1639 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1640 1641 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1642 } 1643 1644 switch (Arg.getValueType()) { 1645 default: assert(0 && "Unexpected ValueType for argument!"); 1646 case MVT::i32: 1647 case MVT::i64: 1648 // Double word align in ELF 1649 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2); 1650 if (GPR_idx != NumGPRs) { 1651 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1652 } else { 1653 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1654 inMem = true; 1655 } 1656 if (inMem || isMachoABI) { 1657 // Stack align in ELF 1658 if (isELF32_ABI && Expand) 1659 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1660 1661 ArgOffset += PtrByteSize; 1662 } 1663 break; 1664 case MVT::f32: 1665 case MVT::f64: 1666 if (isVarArg) { 1667 // Float varargs need to be promoted to double. 1668 if (Arg.getValueType() == MVT::f32) 1669 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); 1670 } 1671 1672 if (FPR_idx != NumFPRs) { 1673 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1674 1675 if (isVarArg) { 1676 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1677 MemOpChains.push_back(Store); 1678 1679 // Float varargs are always shadowed in available integer registers 1680 if (GPR_idx != NumGPRs) { 1681 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1682 MemOpChains.push_back(Load.getValue(1)); 1683 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1684 Load)); 1685 } 1686 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 1687 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1688 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1689 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1690 MemOpChains.push_back(Load.getValue(1)); 1691 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1692 Load)); 1693 } 1694 } else { 1695 // If we have any FPRs remaining, we may also have GPRs remaining. 1696 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1697 // GPRs. 1698 if (isMachoABI) { 1699 if (GPR_idx != NumGPRs) 1700 ++GPR_idx; 1701 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 1702 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 1703 ++GPR_idx; 1704 } 1705 } 1706 } else { 1707 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1708 inMem = true; 1709 } 1710 if (inMem || isMachoABI) { 1711 // Stack align in ELF 1712 if (isELF32_ABI && Expand) 1713 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1714 if (isPPC64) 1715 ArgOffset += 8; 1716 else 1717 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1718 } 1719 break; 1720 case MVT::v4f32: 1721 case MVT::v4i32: 1722 case MVT::v8i16: 1723 case MVT::v16i8: 1724 assert(!isVarArg && "Don't support passing vectors to varargs yet!"); 1725 assert(VR_idx != NumVRs && 1726 "Don't support passing more than 12 vector args yet!"); 1727 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 1728 break; 1729 } 1730 } 1731 if (!MemOpChains.empty()) 1732 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1733 &MemOpChains[0], MemOpChains.size()); 1734 1735 // Build a sequence of copy-to-reg nodes chained together with token chain 1736 // and flag operands which copy the outgoing args into the appropriate regs. 1737 SDOperand InFlag; 1738 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1739 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1740 InFlag); 1741 InFlag = Chain.getValue(1); 1742 } 1743 1744 // With the ELF 32 ABI, set CR6 to true if this is a vararg call. 1745 if (isVarArg && isELF32_ABI) { 1746 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0); 1747 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag); 1748 InFlag = Chain.getValue(1); 1749 } 1750 1751 std::vector<MVT::ValueType> NodeTys; 1752 NodeTys.push_back(MVT::Other); // Returns a chain 1753 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1754 1755 SmallVector<SDOperand, 8> Ops; 1756 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 1757 1758 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1759 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1760 // node so that legalize doesn't hack it. 1761 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1762 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 1763 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1764 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 1765 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 1766 // If this is an absolute destination address, use the munged value. 1767 Callee = SDOperand(Dest, 0); 1768 else { 1769 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 1770 // to do the call, we can't use PPCISD::CALL. 1771 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 1772 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 1773 InFlag = Chain.getValue(1); 1774 1775 // Copy the callee address into R12 on darwin. 1776 if (isMachoABI) { 1777 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); 1778 InFlag = Chain.getValue(1); 1779 } 1780 1781 NodeTys.clear(); 1782 NodeTys.push_back(MVT::Other); 1783 NodeTys.push_back(MVT::Flag); 1784 Ops.push_back(Chain); 1785 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 1786 Callee.Val = 0; 1787 } 1788 1789 // If this is a direct call, pass the chain and the callee. 1790 if (Callee.Val) { 1791 Ops.push_back(Chain); 1792 Ops.push_back(Callee); 1793 } 1794 1795 // Add argument registers to the end of the list so that they are known live 1796 // into the call. 1797 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1798 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1799 RegsToPass[i].second.getValueType())); 1800 1801 if (InFlag.Val) 1802 Ops.push_back(InFlag); 1803 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 1804 InFlag = Chain.getValue(1); 1805 1806 SDOperand ResultVals[3]; 1807 unsigned NumResults = 0; 1808 NodeTys.clear(); 1809 1810 // If the call has results, copy the values out of the ret val registers. 1811 switch (Op.Val->getValueType(0)) { 1812 default: assert(0 && "Unexpected ret value!"); 1813 case MVT::Other: break; 1814 case MVT::i32: 1815 if (Op.Val->getValueType(1) == MVT::i32) { 1816 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1817 ResultVals[0] = Chain.getValue(0); 1818 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, 1819 Chain.getValue(2)).getValue(1); 1820 ResultVals[1] = Chain.getValue(0); 1821 NumResults = 2; 1822 NodeTys.push_back(MVT::i32); 1823 } else { 1824 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1825 ResultVals[0] = Chain.getValue(0); 1826 NumResults = 1; 1827 } 1828 NodeTys.push_back(MVT::i32); 1829 break; 1830 case MVT::i64: 1831 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 1832 ResultVals[0] = Chain.getValue(0); 1833 NumResults = 1; 1834 NodeTys.push_back(MVT::i64); 1835 break; 1836 case MVT::f64: 1837 if (Op.Val->getValueType(1) == MVT::f64) { 1838 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1); 1839 ResultVals[0] = Chain.getValue(0); 1840 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64, 1841 Chain.getValue(2)).getValue(1); 1842 ResultVals[1] = Chain.getValue(0); 1843 NumResults = 2; 1844 NodeTys.push_back(MVT::f64); 1845 NodeTys.push_back(MVT::f64); 1846 break; 1847 } 1848 // else fall through 1849 case MVT::f32: 1850 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 1851 InFlag).getValue(1); 1852 ResultVals[0] = Chain.getValue(0); 1853 NumResults = 1; 1854 NodeTys.push_back(Op.Val->getValueType(0)); 1855 break; 1856 case MVT::v4f32: 1857 case MVT::v4i32: 1858 case MVT::v8i16: 1859 case MVT::v16i8: 1860 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 1861 InFlag).getValue(1); 1862 ResultVals[0] = Chain.getValue(0); 1863 NumResults = 1; 1864 NodeTys.push_back(Op.Val->getValueType(0)); 1865 break; 1866 } 1867 1868 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 1869 DAG.getConstant(NumBytes, PtrVT)); 1870 NodeTys.push_back(MVT::Other); 1871 1872 // If the function returns void, just return the chain. 1873 if (NumResults == 0) 1874 return Chain; 1875 1876 // Otherwise, merge everything together with a MERGE_VALUES node. 1877 ResultVals[NumResults++] = Chain; 1878 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1879 ResultVals, NumResults); 1880 return Res.getValue(Op.ResNo); 1881} 1882 1883static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { 1884 SmallVector<CCValAssign, 16> RVLocs; 1885 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 1886 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1887 CCState CCInfo(CC, isVarArg, TM, RVLocs); 1888 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC); 1889 1890 // If this is the first return lowered for this function, add the regs to the 1891 // liveout set for the function. 1892 if (DAG.getMachineFunction().liveout_empty()) { 1893 for (unsigned i = 0; i != RVLocs.size(); ++i) 1894 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); 1895 } 1896 1897 SDOperand Chain = Op.getOperand(0); 1898 SDOperand Flag; 1899 1900 // Copy the result values into the output registers. 1901 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1902 CCValAssign &VA = RVLocs[i]; 1903 assert(VA.isRegLoc() && "Can only return in registers!"); 1904 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 1905 Flag = Chain.getValue(1); 1906 } 1907 1908 if (Flag.Val) 1909 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); 1910 else 1911 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); 1912} 1913 1914static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, 1915 const PPCSubtarget &Subtarget) { 1916 // When we pop the dynamic allocation we need to restore the SP link. 1917 1918 // Get the corect type for pointers. 1919 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1920 1921 // Construct the stack pointer operand. 1922 bool IsPPC64 = Subtarget.isPPC64(); 1923 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 1924 SDOperand StackPtr = DAG.getRegister(SP, PtrVT); 1925 1926 // Get the operands for the STACKRESTORE. 1927 SDOperand Chain = Op.getOperand(0); 1928 SDOperand SaveSP = Op.getOperand(1); 1929 1930 // Load the old link SP. 1931 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 1932 1933 // Restore the stack pointer. 1934 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 1935 1936 // Store the old link SP. 1937 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 1938} 1939 1940static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, 1941 const PPCSubtarget &Subtarget) { 1942 MachineFunction &MF = DAG.getMachineFunction(); 1943 bool IsPPC64 = Subtarget.isPPC64(); 1944 bool isMachoABI = Subtarget.isMachoABI(); 1945 1946 // Get current frame pointer save index. The users of this index will be 1947 // primarily DYNALLOC instructions. 1948 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1949 int FPSI = FI->getFramePointerSaveIndex(); 1950 1951 // If the frame pointer save index hasn't been defined yet. 1952 if (!FPSI) { 1953 // Find out what the fix offset of the frame pointer save area. 1954 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 1955 1956 // Allocate the frame index for frame pointer save area. 1957 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 1958 // Save the result. 1959 FI->setFramePointerSaveIndex(FPSI); 1960 } 1961 1962 // Get the inputs. 1963 SDOperand Chain = Op.getOperand(0); 1964 SDOperand Size = Op.getOperand(1); 1965 1966 // Get the corect type for pointers. 1967 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1968 // Negate the size. 1969 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, 1970 DAG.getConstant(0, PtrVT), Size); 1971 // Construct a node for the frame pointer save index. 1972 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); 1973 // Build a DYNALLOC node. 1974 SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; 1975 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 1976 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 1977} 1978 1979 1980/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 1981/// possible. 1982static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 1983 // Not FP? Not a fsel. 1984 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 1985 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 1986 return SDOperand(); 1987 1988 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1989 1990 // Cannot handle SETEQ/SETNE. 1991 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 1992 1993 MVT::ValueType ResVT = Op.getValueType(); 1994 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 1995 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 1996 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 1997 1998 // If the RHS of the comparison is a 0.0, we don't need to do the 1999 // subtraction at all. 2000 if (isFloatingPointZero(RHS)) 2001 switch (CC) { 2002 default: break; // SETUO etc aren't handled by fsel. 2003 case ISD::SETULT: 2004 case ISD::SETOLT: 2005 case ISD::SETLT: 2006 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2007 case ISD::SETUGE: 2008 case ISD::SETOGE: 2009 case ISD::SETGE: 2010 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2011 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2012 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 2013 case ISD::SETUGT: 2014 case ISD::SETOGT: 2015 case ISD::SETGT: 2016 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2017 case ISD::SETULE: 2018 case ISD::SETOLE: 2019 case ISD::SETLE: 2020 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2021 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2022 return DAG.getNode(PPCISD::FSEL, ResVT, 2023 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 2024 } 2025 2026 SDOperand Cmp; 2027 switch (CC) { 2028 default: break; // SETUO etc aren't handled by fsel. 2029 case ISD::SETULT: 2030 case ISD::SETOLT: 2031 case ISD::SETLT: 2032 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2033 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2034 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2035 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2036 case ISD::SETUGE: 2037 case ISD::SETOGE: 2038 case ISD::SETGE: 2039 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2040 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2041 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2042 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2043 case ISD::SETUGT: 2044 case ISD::SETOGT: 2045 case ISD::SETGT: 2046 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2047 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2048 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2049 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2050 case ISD::SETULE: 2051 case ISD::SETOLE: 2052 case ISD::SETLE: 2053 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2054 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2055 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2056 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2057 } 2058 return SDOperand(); 2059} 2060 2061static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 2062 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 2063 SDOperand Src = Op.getOperand(0); 2064 if (Src.getValueType() == MVT::f32) 2065 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 2066 2067 SDOperand Tmp; 2068 switch (Op.getValueType()) { 2069 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 2070 case MVT::i32: 2071 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 2072 break; 2073 case MVT::i64: 2074 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 2075 break; 2076 } 2077 2078 // Convert the FP value to an int value through memory. 2079 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 2080 if (Op.getValueType() == MVT::i32) 2081 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 2082 return Bits; 2083} 2084 2085static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) { 2086 assert(Op.getValueType() == MVT::ppcf128); 2087 SDNode *Node = Op.Val; 2088 assert(Node->getOperand(0).getValueType() == MVT::ppcf128); 2089 assert(Node->getOperand(0).Val->getOpcode()==ISD::BUILD_PAIR); 2090 SDOperand Lo = Node->getOperand(0).Val->getOperand(0); 2091 SDOperand Hi = Node->getOperand(0).Val->getOperand(1); 2092 2093 // This sequence changes FPSCR to do round-to-zero, adds the two halves 2094 // of the long double, and puts FPSCR back the way it was. We do not 2095 // actually model FPSCR. 2096 std::vector<MVT::ValueType> NodeTys; 2097 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg; 2098 2099 NodeTys.push_back(MVT::f64); // Return register 2100 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 2101 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 2102 MFFSreg = Result.getValue(0); 2103 InFlag = Result.getValue(1); 2104 2105 NodeTys.clear(); 2106 NodeTys.push_back(MVT::Flag); // Returns a flag 2107 Ops[0] = DAG.getConstant(31, MVT::i32); 2108 Ops[1] = InFlag; 2109 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); 2110 InFlag = Result.getValue(0); 2111 2112 NodeTys.clear(); 2113 NodeTys.push_back(MVT::Flag); // Returns a flag 2114 Ops[0] = DAG.getConstant(30, MVT::i32); 2115 Ops[1] = InFlag; 2116 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); 2117 InFlag = Result.getValue(0); 2118 2119 NodeTys.clear(); 2120 NodeTys.push_back(MVT::f64); // result of add 2121 NodeTys.push_back(MVT::Flag); // Returns a flag 2122 Ops[0] = Lo; 2123 Ops[1] = Hi; 2124 Ops[2] = InFlag; 2125 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); 2126 FPreg = Result.getValue(0); 2127 InFlag = Result.getValue(1); 2128 2129 NodeTys.clear(); 2130 NodeTys.push_back(MVT::f64); 2131 Ops[0] = DAG.getConstant(1, MVT::i32); 2132 Ops[1] = MFFSreg; 2133 Ops[2] = FPreg; 2134 Ops[3] = InFlag; 2135 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); 2136 FPreg = Result.getValue(0); 2137 2138 // We know the low half is about to be thrown away, so just use something 2139 // convenient. 2140 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); 2141} 2142 2143static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 2144 if (Op.getOperand(0).getValueType() == MVT::i64) { 2145 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 2146 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 2147 if (Op.getValueType() == MVT::f32) 2148 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 2149 return FP; 2150 } 2151 2152 assert(Op.getOperand(0).getValueType() == MVT::i32 && 2153 "Unhandled SINT_TO_FP type in custom expander!"); 2154 // Since we only generate this in 64-bit mode, we can take advantage of 2155 // 64-bit registers. In particular, sign extend the input value into the 2156 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 2157 // then lfd it and fcfid it. 2158 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2159 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 2160 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2161 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2162 2163 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 2164 Op.getOperand(0)); 2165 2166 // STD the extended value into the stack slot. 2167 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 2168 DAG.getEntryNode(), Ext64, FIdx, 2169 DAG.getSrcValue(NULL)); 2170 // Load the value as a double. 2171 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 2172 2173 // FCFID it and return it. 2174 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 2175 if (Op.getValueType() == MVT::f32) 2176 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 2177 return FP; 2178} 2179 2180static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2181 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2182 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 2183 2184 // Expand into a bunch of logical ops. Note that these ops 2185 // depend on the PPC behavior for oversized shift amounts. 2186 SDOperand Lo = Op.getOperand(0); 2187 SDOperand Hi = Op.getOperand(1); 2188 SDOperand Amt = Op.getOperand(2); 2189 2190 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2191 DAG.getConstant(32, MVT::i32), Amt); 2192 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 2193 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 2194 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2195 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2196 DAG.getConstant(-32U, MVT::i32)); 2197 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 2198 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2199 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 2200 SDOperand OutOps[] = { OutLo, OutHi }; 2201 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2202 OutOps, 2); 2203} 2204 2205static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2206 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2207 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); 2208 2209 // Otherwise, expand into a bunch of logical ops. Note that these ops 2210 // depend on the PPC behavior for oversized shift amounts. 2211 SDOperand Lo = Op.getOperand(0); 2212 SDOperand Hi = Op.getOperand(1); 2213 SDOperand Amt = Op.getOperand(2); 2214 2215 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2216 DAG.getConstant(32, MVT::i32), Amt); 2217 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2218 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2219 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2220 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2221 DAG.getConstant(-32U, MVT::i32)); 2222 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 2223 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2224 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 2225 SDOperand OutOps[] = { OutLo, OutHi }; 2226 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2227 OutOps, 2); 2228} 2229 2230static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 2231 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2232 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 2233 2234 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 2235 SDOperand Lo = Op.getOperand(0); 2236 SDOperand Hi = Op.getOperand(1); 2237 SDOperand Amt = Op.getOperand(2); 2238 2239 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2240 DAG.getConstant(32, MVT::i32), Amt); 2241 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2242 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2243 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2244 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2245 DAG.getConstant(-32U, MVT::i32)); 2246 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 2247 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 2248 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 2249 Tmp4, Tmp6, ISD::SETLE); 2250 SDOperand OutOps[] = { OutLo, OutHi }; 2251 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2252 OutOps, 2); 2253} 2254 2255//===----------------------------------------------------------------------===// 2256// Vector related lowering. 2257// 2258 2259// If this is a vector of constants or undefs, get the bits. A bit in 2260// UndefBits is set if the corresponding element of the vector is an 2261// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2262// zero. Return true if this is not an array of constants, false if it is. 2263// 2264static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 2265 uint64_t UndefBits[2]) { 2266 // Start with zero'd results. 2267 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 2268 2269 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 2270 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 2271 SDOperand OpVal = BV->getOperand(i); 2272 2273 unsigned PartNo = i >= e/2; // In the upper 128 bits? 2274 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 2275 2276 uint64_t EltBits = 0; 2277 if (OpVal.getOpcode() == ISD::UNDEF) { 2278 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 2279 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 2280 continue; 2281 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 2282 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 2283 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 2284 assert(CN->getValueType(0) == MVT::f32 && 2285 "Only one legal FP vector type!"); 2286 EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); 2287 } else { 2288 // Nonconstant element. 2289 return true; 2290 } 2291 2292 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 2293 } 2294 2295 //printf("%llx %llx %llx %llx\n", 2296 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 2297 return false; 2298} 2299 2300// If this is a splat (repetition) of a value across the whole vector, return 2301// the smallest size that splats it. For example, "0x01010101010101..." is a 2302// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2303// SplatSize = 1 byte. 2304static bool isConstantSplat(const uint64_t Bits128[2], 2305 const uint64_t Undef128[2], 2306 unsigned &SplatBits, unsigned &SplatUndef, 2307 unsigned &SplatSize) { 2308 2309 // Don't let undefs prevent splats from matching. See if the top 64-bits are 2310 // the same as the lower 64-bits, ignoring undefs. 2311 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 2312 return false; // Can't be a splat if two pieces don't match. 2313 2314 uint64_t Bits64 = Bits128[0] | Bits128[1]; 2315 uint64_t Undef64 = Undef128[0] & Undef128[1]; 2316 2317 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 2318 // undefs. 2319 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 2320 return false; // Can't be a splat if two pieces don't match. 2321 2322 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 2323 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 2324 2325 // If the top 16-bits are different than the lower 16-bits, ignoring 2326 // undefs, we have an i32 splat. 2327 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 2328 SplatBits = Bits32; 2329 SplatUndef = Undef32; 2330 SplatSize = 4; 2331 return true; 2332 } 2333 2334 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 2335 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 2336 2337 // If the top 8-bits are different than the lower 8-bits, ignoring 2338 // undefs, we have an i16 splat. 2339 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 2340 SplatBits = Bits16; 2341 SplatUndef = Undef16; 2342 SplatSize = 2; 2343 return true; 2344 } 2345 2346 // Otherwise, we have an 8-bit splat. 2347 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 2348 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 2349 SplatSize = 1; 2350 return true; 2351} 2352 2353/// BuildSplatI - Build a canonical splati of Val with an element size of 2354/// SplatSize. Cast the result to VT. 2355static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 2356 SelectionDAG &DAG) { 2357 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 2358 2359 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 2360 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 2361 }; 2362 2363 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 2364 2365 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 2366 if (Val == -1) 2367 SplatSize = 1; 2368 2369 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 2370 2371 // Build a canonical splat for this value. 2372 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT)); 2373 SmallVector<SDOperand, 8> Ops; 2374 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 2375 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 2376 &Ops[0], Ops.size()); 2377 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 2378} 2379 2380/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 2381/// specified intrinsic ID. 2382static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 2383 SelectionDAG &DAG, 2384 MVT::ValueType DestVT = MVT::Other) { 2385 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 2386 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2387 DAG.getConstant(IID, MVT::i32), LHS, RHS); 2388} 2389 2390/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 2391/// specified intrinsic ID. 2392static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 2393 SDOperand Op2, SelectionDAG &DAG, 2394 MVT::ValueType DestVT = MVT::Other) { 2395 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 2396 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2397 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 2398} 2399 2400 2401/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 2402/// amount. The result has the specified value type. 2403static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 2404 MVT::ValueType VT, SelectionDAG &DAG) { 2405 // Force LHS/RHS to be the right type. 2406 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 2407 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 2408 2409 SDOperand Ops[16]; 2410 for (unsigned i = 0; i != 16; ++i) 2411 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 2412 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 2413 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 2414 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 2415} 2416 2417// If this is a case we can't handle, return null and let the default 2418// expansion code take care of it. If we CAN select this case, and if it 2419// selects to a single instruction, return Op. Otherwise, if we can codegen 2420// this case more efficiently than a constant pool load, lower it to the 2421// sequence of ops that should be used. 2422static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2423 // If this is a vector of constants or undefs, get the bits. A bit in 2424 // UndefBits is set if the corresponding element of the vector is an 2425 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2426 // zero. 2427 uint64_t VectorBits[2]; 2428 uint64_t UndefBits[2]; 2429 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 2430 return SDOperand(); // Not a constant vector. 2431 2432 // If this is a splat (repetition) of a value across the whole vector, return 2433 // the smallest size that splats it. For example, "0x01010101010101..." is a 2434 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2435 // SplatSize = 1 byte. 2436 unsigned SplatBits, SplatUndef, SplatSize; 2437 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 2438 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 2439 2440 // First, handle single instruction cases. 2441 2442 // All zeros? 2443 if (SplatBits == 0) { 2444 // Canonicalize all zero vectors to be v4i32. 2445 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 2446 SDOperand Z = DAG.getConstant(0, MVT::i32); 2447 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 2448 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 2449 } 2450 return Op; 2451 } 2452 2453 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 2454 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 2455 if (SextVal >= -16 && SextVal <= 15) 2456 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 2457 2458 2459 // Two instruction sequences. 2460 2461 // If this value is in the range [-32,30] and is even, use: 2462 // tmp = VSPLTI[bhw], result = add tmp, tmp 2463 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 2464 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 2465 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 2466 } 2467 2468 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 2469 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 2470 // for fneg/fabs. 2471 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 2472 // Make -1 and vspltisw -1: 2473 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 2474 2475 // Make the VSLW intrinsic, computing 0x8000_0000. 2476 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 2477 OnesV, DAG); 2478 2479 // xor by OnesV to invert it. 2480 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 2481 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2482 } 2483 2484 // Check to see if this is a wide variety of vsplti*, binop self cases. 2485 unsigned SplatBitSize = SplatSize*8; 2486 static const signed char SplatCsts[] = { 2487 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 2488 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 2489 }; 2490 2491 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 2492 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 2493 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 2494 int i = SplatCsts[idx]; 2495 2496 // Figure out what shift amount will be used by altivec if shifted by i in 2497 // this splat size. 2498 unsigned TypeShiftAmt = i & (SplatBitSize-1); 2499 2500 // vsplti + shl self. 2501 if (SextVal == (i << (int)TypeShiftAmt)) { 2502 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2503 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2504 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 2505 Intrinsic::ppc_altivec_vslw 2506 }; 2507 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2508 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2509 } 2510 2511 // vsplti + srl self. 2512 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2513 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2514 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2515 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 2516 Intrinsic::ppc_altivec_vsrw 2517 }; 2518 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2519 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2520 } 2521 2522 // vsplti + sra self. 2523 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2524 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2525 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2526 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 2527 Intrinsic::ppc_altivec_vsraw 2528 }; 2529 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2530 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2531 } 2532 2533 // vsplti + rol self. 2534 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 2535 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 2536 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2537 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2538 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 2539 Intrinsic::ppc_altivec_vrlw 2540 }; 2541 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2542 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2543 } 2544 2545 // t = vsplti c, result = vsldoi t, t, 1 2546 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 2547 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2548 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 2549 } 2550 // t = vsplti c, result = vsldoi t, t, 2 2551 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 2552 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2553 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 2554 } 2555 // t = vsplti c, result = vsldoi t, t, 3 2556 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 2557 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2558 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 2559 } 2560 } 2561 2562 // Three instruction sequences. 2563 2564 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 2565 if (SextVal >= 0 && SextVal <= 31) { 2566 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 2567 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2568 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS); 2569 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2570 } 2571 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 2572 if (SextVal >= -31 && SextVal <= 0) { 2573 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 2574 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2575 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS); 2576 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2577 } 2578 } 2579 2580 return SDOperand(); 2581} 2582 2583/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2584/// the specified operations to build the shuffle. 2585static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 2586 SDOperand RHS, SelectionDAG &DAG) { 2587 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2588 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2589 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2590 2591 enum { 2592 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2593 OP_VMRGHW, 2594 OP_VMRGLW, 2595 OP_VSPLTISW0, 2596 OP_VSPLTISW1, 2597 OP_VSPLTISW2, 2598 OP_VSPLTISW3, 2599 OP_VSLDOI4, 2600 OP_VSLDOI8, 2601 OP_VSLDOI12 2602 }; 2603 2604 if (OpNum == OP_COPY) { 2605 if (LHSID == (1*9+2)*9+3) return LHS; 2606 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2607 return RHS; 2608 } 2609 2610 SDOperand OpLHS, OpRHS; 2611 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 2612 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 2613 2614 unsigned ShufIdxs[16]; 2615 switch (OpNum) { 2616 default: assert(0 && "Unknown i32 permute!"); 2617 case OP_VMRGHW: 2618 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 2619 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 2620 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 2621 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 2622 break; 2623 case OP_VMRGLW: 2624 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 2625 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 2626 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 2627 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 2628 break; 2629 case OP_VSPLTISW0: 2630 for (unsigned i = 0; i != 16; ++i) 2631 ShufIdxs[i] = (i&3)+0; 2632 break; 2633 case OP_VSPLTISW1: 2634 for (unsigned i = 0; i != 16; ++i) 2635 ShufIdxs[i] = (i&3)+4; 2636 break; 2637 case OP_VSPLTISW2: 2638 for (unsigned i = 0; i != 16; ++i) 2639 ShufIdxs[i] = (i&3)+8; 2640 break; 2641 case OP_VSPLTISW3: 2642 for (unsigned i = 0; i != 16; ++i) 2643 ShufIdxs[i] = (i&3)+12; 2644 break; 2645 case OP_VSLDOI4: 2646 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 2647 case OP_VSLDOI8: 2648 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 2649 case OP_VSLDOI12: 2650 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 2651 } 2652 SDOperand Ops[16]; 2653 for (unsigned i = 0; i != 16; ++i) 2654 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 2655 2656 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 2657 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2658} 2659 2660/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 2661/// is a shuffle we can handle in a single instruction, return it. Otherwise, 2662/// return the code it can be lowered into. Worst case, it can always be 2663/// lowered into a vperm. 2664static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 2665 SDOperand V1 = Op.getOperand(0); 2666 SDOperand V2 = Op.getOperand(1); 2667 SDOperand PermMask = Op.getOperand(2); 2668 2669 // Cases that are handled by instructions that take permute immediates 2670 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 2671 // selected by the instruction selector. 2672 if (V2.getOpcode() == ISD::UNDEF) { 2673 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 2674 PPC::isSplatShuffleMask(PermMask.Val, 2) || 2675 PPC::isSplatShuffleMask(PermMask.Val, 4) || 2676 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 2677 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 2678 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 2679 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 2680 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 2681 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 2682 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 2683 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 2684 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 2685 return Op; 2686 } 2687 } 2688 2689 // Altivec has a variety of "shuffle immediates" that take two vector inputs 2690 // and produce a fixed permutation. If any of these match, do not lower to 2691 // VPERM. 2692 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 2693 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 2694 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 2695 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 2696 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 2697 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 2698 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 2699 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 2700 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 2701 return Op; 2702 2703 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 2704 // perfect shuffle table to emit an optimal matching sequence. 2705 unsigned PFIndexes[4]; 2706 bool isFourElementShuffle = true; 2707 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 2708 unsigned EltNo = 8; // Start out undef. 2709 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 2710 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 2711 continue; // Undef, ignore it. 2712 2713 unsigned ByteSource = 2714 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 2715 if ((ByteSource & 3) != j) { 2716 isFourElementShuffle = false; 2717 break; 2718 } 2719 2720 if (EltNo == 8) { 2721 EltNo = ByteSource/4; 2722 } else if (EltNo != ByteSource/4) { 2723 isFourElementShuffle = false; 2724 break; 2725 } 2726 } 2727 PFIndexes[i] = EltNo; 2728 } 2729 2730 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 2731 // perfect shuffle vector to determine if it is cost effective to do this as 2732 // discrete instructions, or whether we should use a vperm. 2733 if (isFourElementShuffle) { 2734 // Compute the index in the perfect shuffle table. 2735 unsigned PFTableIndex = 2736 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2737 2738 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2739 unsigned Cost = (PFEntry >> 30); 2740 2741 // Determining when to avoid vperm is tricky. Many things affect the cost 2742 // of vperm, particularly how many times the perm mask needs to be computed. 2743 // For example, if the perm mask can be hoisted out of a loop or is already 2744 // used (perhaps because there are multiple permutes with the same shuffle 2745 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 2746 // the loop requires an extra register. 2747 // 2748 // As a compromise, we only emit discrete instructions if the shuffle can be 2749 // generated in 3 or fewer operations. When we have loop information 2750 // available, if this block is within a loop, we should avoid using vperm 2751 // for 3-operation perms and use a constant pool load instead. 2752 if (Cost < 3) 2753 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 2754 } 2755 2756 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 2757 // vector that will get spilled to the constant pool. 2758 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 2759 2760 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 2761 // that it is in input element units, not in bytes. Convert now. 2762 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); 2763 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 2764 2765 SmallVector<SDOperand, 16> ResultMask; 2766 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 2767 unsigned SrcElt; 2768 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 2769 SrcElt = 0; 2770 else 2771 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 2772 2773 for (unsigned j = 0; j != BytesPerElement; ++j) 2774 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 2775 MVT::i8)); 2776 } 2777 2778 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 2779 &ResultMask[0], ResultMask.size()); 2780 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 2781} 2782 2783/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 2784/// altivec comparison. If it is, return true and fill in Opc/isDot with 2785/// information about the intrinsic. 2786static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 2787 bool &isDot) { 2788 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 2789 CompareOpc = -1; 2790 isDot = false; 2791 switch (IntrinsicID) { 2792 default: return false; 2793 // Comparison predicates. 2794 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 2795 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 2796 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 2797 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 2798 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 2799 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 2800 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 2801 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 2802 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 2803 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 2804 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 2805 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 2806 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 2807 2808 // Normal Comparisons. 2809 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 2810 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 2811 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 2812 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 2813 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 2814 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 2815 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 2816 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 2817 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 2818 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 2819 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 2820 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 2821 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 2822 } 2823 return true; 2824} 2825 2826/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 2827/// lower, do it, otherwise return null. 2828static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 2829 // If this is a lowered altivec predicate compare, CompareOpc is set to the 2830 // opcode number of the comparison. 2831 int CompareOpc; 2832 bool isDot; 2833 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 2834 return SDOperand(); // Don't custom lower most intrinsics. 2835 2836 // If this is a non-dot comparison, make the VCMP node and we are done. 2837 if (!isDot) { 2838 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 2839 Op.getOperand(1), Op.getOperand(2), 2840 DAG.getConstant(CompareOpc, MVT::i32)); 2841 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 2842 } 2843 2844 // Create the PPCISD altivec 'dot' comparison node. 2845 SDOperand Ops[] = { 2846 Op.getOperand(2), // LHS 2847 Op.getOperand(3), // RHS 2848 DAG.getConstant(CompareOpc, MVT::i32) 2849 }; 2850 std::vector<MVT::ValueType> VTs; 2851 VTs.push_back(Op.getOperand(2).getValueType()); 2852 VTs.push_back(MVT::Flag); 2853 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2854 2855 // Now that we have the comparison, emit a copy from the CR to a GPR. 2856 // This is flagged to the above dot comparison. 2857 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 2858 DAG.getRegister(PPC::CR6, MVT::i32), 2859 CompNode.getValue(1)); 2860 2861 // Unpack the result based on how the target uses it. 2862 unsigned BitNo; // Bit # of CR6. 2863 bool InvertBit; // Invert result? 2864 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 2865 default: // Can't happen, don't crash on invalid number though. 2866 case 0: // Return the value of the EQ bit of CR6. 2867 BitNo = 0; InvertBit = false; 2868 break; 2869 case 1: // Return the inverted value of the EQ bit of CR6. 2870 BitNo = 0; InvertBit = true; 2871 break; 2872 case 2: // Return the value of the LT bit of CR6. 2873 BitNo = 2; InvertBit = false; 2874 break; 2875 case 3: // Return the inverted value of the LT bit of CR6. 2876 BitNo = 2; InvertBit = true; 2877 break; 2878 } 2879 2880 // Shift the bit into the low position. 2881 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 2882 DAG.getConstant(8-(3-BitNo), MVT::i32)); 2883 // Isolate the bit. 2884 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 2885 DAG.getConstant(1, MVT::i32)); 2886 2887 // If we are supposed to, toggle the bit. 2888 if (InvertBit) 2889 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 2890 DAG.getConstant(1, MVT::i32)); 2891 return Flags; 2892} 2893 2894static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2895 // Create a stack slot that is 16-byte aligned. 2896 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2897 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 2898 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2899 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2900 2901 // Store the input value into Value#0 of the stack slot. 2902 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 2903 Op.getOperand(0), FIdx, NULL, 0); 2904 // Load it out. 2905 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 2906} 2907 2908static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 2909 if (Op.getValueType() == MVT::v4i32) { 2910 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2911 2912 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 2913 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 2914 2915 SDOperand RHSSwap = // = vrlw RHS, 16 2916 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 2917 2918 // Shrinkify inputs to v8i16. 2919 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 2920 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 2921 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 2922 2923 // Low parts multiplied together, generating 32-bit results (we ignore the 2924 // top parts). 2925 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 2926 LHS, RHS, DAG, MVT::v4i32); 2927 2928 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 2929 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 2930 // Shift the high parts up 16 bits. 2931 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 2932 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 2933 } else if (Op.getValueType() == MVT::v8i16) { 2934 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2935 2936 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 2937 2938 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 2939 LHS, RHS, Zero, DAG); 2940 } else if (Op.getValueType() == MVT::v16i8) { 2941 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2942 2943 // Multiply the even 8-bit parts, producing 16-bit sums. 2944 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 2945 LHS, RHS, DAG, MVT::v8i16); 2946 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 2947 2948 // Multiply the odd 8-bit parts, producing 16-bit sums. 2949 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 2950 LHS, RHS, DAG, MVT::v8i16); 2951 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 2952 2953 // Merge the results together. 2954 SDOperand Ops[16]; 2955 for (unsigned i = 0; i != 8; ++i) { 2956 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 2957 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 2958 } 2959 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 2960 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2961 } else { 2962 assert(0 && "Unknown mul to lower!"); 2963 abort(); 2964 } 2965} 2966 2967/// LowerOperation - Provide custom lowering hooks for some operations. 2968/// 2969SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2970 switch (Op.getOpcode()) { 2971 default: assert(0 && "Wasn't expecting to be able to lower this!"); 2972 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2973 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2974 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 2975 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 2976 case ISD::SETCC: return LowerSETCC(Op, DAG); 2977 case ISD::VASTART: 2978 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 2979 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 2980 2981 case ISD::VAARG: 2982 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 2983 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 2984 2985 case ISD::FORMAL_ARGUMENTS: 2986 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, 2987 VarArgsStackOffset, VarArgsNumGPR, 2988 VarArgsNumFPR, PPCSubTarget); 2989 2990 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget); 2991 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); 2992 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 2993 case ISD::DYNAMIC_STACKALLOC: 2994 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 2995 2996 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 2997 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 2998 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 2999 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG); 3000 3001 // Lower 64-bit shifts. 3002 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 3003 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 3004 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 3005 3006 // Vector-related lowering. 3007 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3008 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3009 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 3010 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 3011 case ISD::MUL: return LowerMUL(Op, DAG); 3012 3013 // Frame & Return address. Currently unimplemented 3014 case ISD::RETURNADDR: break; 3015 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3016 } 3017 return SDOperand(); 3018} 3019 3020//===----------------------------------------------------------------------===// 3021// Other Lowering Code 3022//===----------------------------------------------------------------------===// 3023 3024MachineBasicBlock * 3025PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3026 MachineBasicBlock *BB) { 3027 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3028 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 3029 MI->getOpcode() == PPC::SELECT_CC_I8 || 3030 MI->getOpcode() == PPC::SELECT_CC_F4 || 3031 MI->getOpcode() == PPC::SELECT_CC_F8 || 3032 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 3033 "Unexpected instr type to insert"); 3034 3035 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 3036 // control-flow pattern. The incoming instruction knows the destination vreg 3037 // to set, the condition code register to branch on, the true/false values to 3038 // select between, and a branch opcode to use. 3039 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3040 ilist<MachineBasicBlock>::iterator It = BB; 3041 ++It; 3042 3043 // thisMBB: 3044 // ... 3045 // TrueVal = ... 3046 // cmpTY ccX, r1, r2 3047 // bCC copy1MBB 3048 // fallthrough --> copy0MBB 3049 MachineBasicBlock *thisMBB = BB; 3050 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 3051 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 3052 unsigned SelectPred = MI->getOperand(4).getImm(); 3053 BuildMI(BB, TII->get(PPC::BCC)) 3054 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 3055 MachineFunction *F = BB->getParent(); 3056 F->getBasicBlockList().insert(It, copy0MBB); 3057 F->getBasicBlockList().insert(It, sinkMBB); 3058 // Update machine-CFG edges by first adding all successors of the current 3059 // block to the new block which will contain the Phi node for the select. 3060 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 3061 e = BB->succ_end(); i != e; ++i) 3062 sinkMBB->addSuccessor(*i); 3063 // Next, remove all successors of the current block, and add the true 3064 // and fallthrough blocks as its successors. 3065 while(!BB->succ_empty()) 3066 BB->removeSuccessor(BB->succ_begin()); 3067 BB->addSuccessor(copy0MBB); 3068 BB->addSuccessor(sinkMBB); 3069 3070 // copy0MBB: 3071 // %FalseValue = ... 3072 // # fallthrough to sinkMBB 3073 BB = copy0MBB; 3074 3075 // Update machine-CFG edges 3076 BB->addSuccessor(sinkMBB); 3077 3078 // sinkMBB: 3079 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 3080 // ... 3081 BB = sinkMBB; 3082 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 3083 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 3084 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 3085 3086 delete MI; // The pseudo instruction is gone now. 3087 return BB; 3088} 3089 3090//===----------------------------------------------------------------------===// 3091// Target Optimization Hooks 3092//===----------------------------------------------------------------------===// 3093 3094SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 3095 DAGCombinerInfo &DCI) const { 3096 TargetMachine &TM = getTargetMachine(); 3097 SelectionDAG &DAG = DCI.DAG; 3098 switch (N->getOpcode()) { 3099 default: break; 3100 case PPCISD::SHL: 3101 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3102 if (C->getValue() == 0) // 0 << V -> 0. 3103 return N->getOperand(0); 3104 } 3105 break; 3106 case PPCISD::SRL: 3107 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3108 if (C->getValue() == 0) // 0 >>u V -> 0. 3109 return N->getOperand(0); 3110 } 3111 break; 3112 case PPCISD::SRA: 3113 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3114 if (C->getValue() == 0 || // 0 >>s V -> 0. 3115 C->isAllOnesValue()) // -1 >>s V -> -1. 3116 return N->getOperand(0); 3117 } 3118 break; 3119 3120 case ISD::SINT_TO_FP: 3121 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 3122 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 3123 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 3124 // We allow the src/dst to be either f32/f64, but the intermediate 3125 // type must be i64. 3126 if (N->getOperand(0).getValueType() == MVT::i64) { 3127 SDOperand Val = N->getOperand(0).getOperand(0); 3128 if (Val.getValueType() == MVT::f32) { 3129 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3130 DCI.AddToWorklist(Val.Val); 3131 } 3132 3133 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 3134 DCI.AddToWorklist(Val.Val); 3135 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 3136 DCI.AddToWorklist(Val.Val); 3137 if (N->getValueType(0) == MVT::f32) { 3138 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 3139 DCI.AddToWorklist(Val.Val); 3140 } 3141 return Val; 3142 } else if (N->getOperand(0).getValueType() == MVT::i32) { 3143 // If the intermediate type is i32, we can avoid the load/store here 3144 // too. 3145 } 3146 } 3147 } 3148 break; 3149 case ISD::STORE: 3150 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 3151 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 3152 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 3153 N->getOperand(1).getValueType() == MVT::i32) { 3154 SDOperand Val = N->getOperand(1).getOperand(0); 3155 if (Val.getValueType() == MVT::f32) { 3156 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3157 DCI.AddToWorklist(Val.Val); 3158 } 3159 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 3160 DCI.AddToWorklist(Val.Val); 3161 3162 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 3163 N->getOperand(2), N->getOperand(3)); 3164 DCI.AddToWorklist(Val.Val); 3165 return Val; 3166 } 3167 3168 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 3169 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 3170 N->getOperand(1).Val->hasOneUse() && 3171 (N->getOperand(1).getValueType() == MVT::i32 || 3172 N->getOperand(1).getValueType() == MVT::i16)) { 3173 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 3174 // Do an any-extend to 32-bits if this is a half-word input. 3175 if (BSwapOp.getValueType() == MVT::i16) 3176 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 3177 3178 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 3179 N->getOperand(2), N->getOperand(3), 3180 DAG.getValueType(N->getOperand(1).getValueType())); 3181 } 3182 break; 3183 case ISD::BSWAP: 3184 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 3185 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 3186 N->getOperand(0).hasOneUse() && 3187 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 3188 SDOperand Load = N->getOperand(0); 3189 LoadSDNode *LD = cast<LoadSDNode>(Load); 3190 // Create the byte-swapping load. 3191 std::vector<MVT::ValueType> VTs; 3192 VTs.push_back(MVT::i32); 3193 VTs.push_back(MVT::Other); 3194 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); 3195 SDOperand Ops[] = { 3196 LD->getChain(), // Chain 3197 LD->getBasePtr(), // Ptr 3198 SV, // SrcValue 3199 DAG.getValueType(N->getValueType(0)) // VT 3200 }; 3201 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 3202 3203 // If this is an i16 load, insert the truncate. 3204 SDOperand ResVal = BSLoad; 3205 if (N->getValueType(0) == MVT::i16) 3206 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 3207 3208 // First, combine the bswap away. This makes the value produced by the 3209 // load dead. 3210 DCI.CombineTo(N, ResVal); 3211 3212 // Next, combine the load away, we give it a bogus result value but a real 3213 // chain result. The result value is dead because the bswap is dead. 3214 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 3215 3216 // Return N so it doesn't get rechecked! 3217 return SDOperand(N, 0); 3218 } 3219 3220 break; 3221 case PPCISD::VCMP: { 3222 // If a VCMPo node already exists with exactly the same operands as this 3223 // node, use its result instead of this node (VCMPo computes both a CR6 and 3224 // a normal output). 3225 // 3226 if (!N->getOperand(0).hasOneUse() && 3227 !N->getOperand(1).hasOneUse() && 3228 !N->getOperand(2).hasOneUse()) { 3229 3230 // Scan all of the users of the LHS, looking for VCMPo's that match. 3231 SDNode *VCMPoNode = 0; 3232 3233 SDNode *LHSN = N->getOperand(0).Val; 3234 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 3235 UI != E; ++UI) 3236 if ((*UI)->getOpcode() == PPCISD::VCMPo && 3237 (*UI)->getOperand(1) == N->getOperand(1) && 3238 (*UI)->getOperand(2) == N->getOperand(2) && 3239 (*UI)->getOperand(0) == N->getOperand(0)) { 3240 VCMPoNode = *UI; 3241 break; 3242 } 3243 3244 // If there is no VCMPo node, or if the flag value has a single use, don't 3245 // transform this. 3246 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 3247 break; 3248 3249 // Look at the (necessarily single) use of the flag value. If it has a 3250 // chain, this transformation is more complex. Note that multiple things 3251 // could use the value result, which we should ignore. 3252 SDNode *FlagUser = 0; 3253 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 3254 FlagUser == 0; ++UI) { 3255 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 3256 SDNode *User = *UI; 3257 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 3258 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 3259 FlagUser = User; 3260 break; 3261 } 3262 } 3263 } 3264 3265 // If the user is a MFCR instruction, we know this is safe. Otherwise we 3266 // give up for right now. 3267 if (FlagUser->getOpcode() == PPCISD::MFCR) 3268 return SDOperand(VCMPoNode, 0); 3269 } 3270 break; 3271 } 3272 case ISD::BR_CC: { 3273 // If this is a branch on an altivec predicate comparison, lower this so 3274 // that we don't have to do a MFCR: instead, branch directly on CR6. This 3275 // lowering is done pre-legalize, because the legalizer lowers the predicate 3276 // compare down to code that is difficult to reassemble. 3277 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 3278 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 3279 int CompareOpc; 3280 bool isDot; 3281 3282 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 3283 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 3284 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 3285 assert(isDot && "Can't compare against a vector result!"); 3286 3287 // If this is a comparison against something other than 0/1, then we know 3288 // that the condition is never/always true. 3289 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 3290 if (Val != 0 && Val != 1) { 3291 if (CC == ISD::SETEQ) // Cond never true, remove branch. 3292 return N->getOperand(0); 3293 // Always !=, turn it into an unconditional branch. 3294 return DAG.getNode(ISD::BR, MVT::Other, 3295 N->getOperand(0), N->getOperand(4)); 3296 } 3297 3298 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 3299 3300 // Create the PPCISD altivec 'dot' comparison node. 3301 std::vector<MVT::ValueType> VTs; 3302 SDOperand Ops[] = { 3303 LHS.getOperand(2), // LHS of compare 3304 LHS.getOperand(3), // RHS of compare 3305 DAG.getConstant(CompareOpc, MVT::i32) 3306 }; 3307 VTs.push_back(LHS.getOperand(2).getValueType()); 3308 VTs.push_back(MVT::Flag); 3309 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 3310 3311 // Unpack the result based on how the target uses it. 3312 PPC::Predicate CompOpc; 3313 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 3314 default: // Can't happen, don't crash on invalid number though. 3315 case 0: // Branch on the value of the EQ bit of CR6. 3316 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 3317 break; 3318 case 1: // Branch on the inverted value of the EQ bit of CR6. 3319 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 3320 break; 3321 case 2: // Branch on the value of the LT bit of CR6. 3322 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 3323 break; 3324 case 3: // Branch on the inverted value of the LT bit of CR6. 3325 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 3326 break; 3327 } 3328 3329 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 3330 DAG.getConstant(CompOpc, MVT::i32), 3331 DAG.getRegister(PPC::CR6, MVT::i32), 3332 N->getOperand(4), CompNode.getValue(1)); 3333 } 3334 break; 3335 } 3336 } 3337 3338 return SDOperand(); 3339} 3340 3341//===----------------------------------------------------------------------===// 3342// Inline Assembly Support 3343//===----------------------------------------------------------------------===// 3344 3345void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 3346 uint64_t Mask, 3347 uint64_t &KnownZero, 3348 uint64_t &KnownOne, 3349 const SelectionDAG &DAG, 3350 unsigned Depth) const { 3351 KnownZero = 0; 3352 KnownOne = 0; 3353 switch (Op.getOpcode()) { 3354 default: break; 3355 case PPCISD::LBRX: { 3356 // lhbrx is known to have the top bits cleared out. 3357 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 3358 KnownZero = 0xFFFF0000; 3359 break; 3360 } 3361 case ISD::INTRINSIC_WO_CHAIN: { 3362 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 3363 default: break; 3364 case Intrinsic::ppc_altivec_vcmpbfp_p: 3365 case Intrinsic::ppc_altivec_vcmpeqfp_p: 3366 case Intrinsic::ppc_altivec_vcmpequb_p: 3367 case Intrinsic::ppc_altivec_vcmpequh_p: 3368 case Intrinsic::ppc_altivec_vcmpequw_p: 3369 case Intrinsic::ppc_altivec_vcmpgefp_p: 3370 case Intrinsic::ppc_altivec_vcmpgtfp_p: 3371 case Intrinsic::ppc_altivec_vcmpgtsb_p: 3372 case Intrinsic::ppc_altivec_vcmpgtsh_p: 3373 case Intrinsic::ppc_altivec_vcmpgtsw_p: 3374 case Intrinsic::ppc_altivec_vcmpgtub_p: 3375 case Intrinsic::ppc_altivec_vcmpgtuh_p: 3376 case Intrinsic::ppc_altivec_vcmpgtuw_p: 3377 KnownZero = ~1U; // All bits but the low one are known to be zero. 3378 break; 3379 } 3380 } 3381 } 3382} 3383 3384 3385/// getConstraintType - Given a constraint, return the type of 3386/// constraint it is for this target. 3387PPCTargetLowering::ConstraintType 3388PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 3389 if (Constraint.size() == 1) { 3390 switch (Constraint[0]) { 3391 default: break; 3392 case 'b': 3393 case 'r': 3394 case 'f': 3395 case 'v': 3396 case 'y': 3397 return C_RegisterClass; 3398 } 3399 } 3400 return TargetLowering::getConstraintType(Constraint); 3401} 3402 3403std::pair<unsigned, const TargetRegisterClass*> 3404PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3405 MVT::ValueType VT) const { 3406 if (Constraint.size() == 1) { 3407 // GCC RS6000 Constraint Letters 3408 switch (Constraint[0]) { 3409 case 'b': // R1-R31 3410 case 'r': // R0-R31 3411 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 3412 return std::make_pair(0U, PPC::G8RCRegisterClass); 3413 return std::make_pair(0U, PPC::GPRCRegisterClass); 3414 case 'f': 3415 if (VT == MVT::f32) 3416 return std::make_pair(0U, PPC::F4RCRegisterClass); 3417 else if (VT == MVT::f64) 3418 return std::make_pair(0U, PPC::F8RCRegisterClass); 3419 break; 3420 case 'v': 3421 return std::make_pair(0U, PPC::VRRCRegisterClass); 3422 case 'y': // crrc 3423 return std::make_pair(0U, PPC::CRRCRegisterClass); 3424 } 3425 } 3426 3427 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3428} 3429 3430 3431/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3432/// vector. If it is invalid, don't add anything to Ops. 3433void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter, 3434 std::vector<SDOperand>&Ops, 3435 SelectionDAG &DAG) { 3436 SDOperand Result(0,0); 3437 switch (Letter) { 3438 default: break; 3439 case 'I': 3440 case 'J': 3441 case 'K': 3442 case 'L': 3443 case 'M': 3444 case 'N': 3445 case 'O': 3446 case 'P': { 3447 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 3448 if (!CST) return; // Must be an immediate to match. 3449 unsigned Value = CST->getValue(); 3450 switch (Letter) { 3451 default: assert(0 && "Unknown constraint letter!"); 3452 case 'I': // "I" is a signed 16-bit constant. 3453 if ((short)Value == (int)Value) 3454 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3455 break; 3456 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 3457 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 3458 if ((short)Value == 0) 3459 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3460 break; 3461 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 3462 if ((Value >> 16) == 0) 3463 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3464 break; 3465 case 'M': // "M" is a constant that is greater than 31. 3466 if (Value > 31) 3467 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3468 break; 3469 case 'N': // "N" is a positive constant that is an exact power of two. 3470 if ((int)Value > 0 && isPowerOf2_32(Value)) 3471 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3472 break; 3473 case 'O': // "O" is the constant zero. 3474 if (Value == 0) 3475 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3476 break; 3477 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 3478 if ((short)-Value == (int)-Value) 3479 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3480 break; 3481 } 3482 break; 3483 } 3484 } 3485 3486 if (Result.Val) { 3487 Ops.push_back(Result); 3488 return; 3489 } 3490 3491 // Handle standard constraint letters. 3492 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); 3493} 3494 3495// isLegalAddressingMode - Return true if the addressing mode represented 3496// by AM is legal for this target, for a load/store of the specified type. 3497bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3498 const Type *Ty) const { 3499 // FIXME: PPC does not allow r+i addressing modes for vectors! 3500 3501 // PPC allows a sign-extended 16-bit immediate field. 3502 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3503 return false; 3504 3505 // No global is ever allowed as a base. 3506 if (AM.BaseGV) 3507 return false; 3508 3509 // PPC only support r+r, 3510 switch (AM.Scale) { 3511 case 0: // "r+i" or just "i", depending on HasBaseReg. 3512 break; 3513 case 1: 3514 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3515 return false; 3516 // Otherwise we have r+r or r+i. 3517 break; 3518 case 2: 3519 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3520 return false; 3521 // Allow 2*r as r+r. 3522 break; 3523 default: 3524 // No other scales are supported. 3525 return false; 3526 } 3527 3528 return true; 3529} 3530 3531/// isLegalAddressImmediate - Return true if the integer value can be used 3532/// as the offset of the target addressing mode for load / store of the 3533/// given type. 3534bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 3535 // PPC allows a sign-extended 16-bit immediate field. 3536 return (V > -(1 << 16) && V < (1 << 16)-1); 3537} 3538 3539bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 3540 return false; 3541} 3542 3543SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) 3544{ 3545 // Depths > 0 not supported yet! 3546 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3547 return SDOperand(); 3548 3549 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3550 bool isPPC64 = PtrVT == MVT::i64; 3551 3552 MachineFunction &MF = DAG.getMachineFunction(); 3553 MachineFrameInfo *MFI = MF.getFrameInfo(); 3554 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 3555 && MFI->getStackSize(); 3556 3557 if (isPPC64) 3558 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, 3559 MVT::i64); 3560 else 3561 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, 3562 MVT::i32); 3563} 3564