PPCISelLowering.cpp revision 10da9575740d9515c70a171a7c40405302d62f4a
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCTargetMachine.h" 16#include "PPCPerfectShuffle.h" 17#include "llvm/ADT/VectorExtras.h" 18#include "llvm/Analysis/ScalarEvolutionExpressions.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Constants.h" 25#include "llvm/Function.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/Support/MathExtras.h" 28#include "llvm/Target/TargetOptions.h" 29using namespace llvm; 30 31PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) 32 : TargetLowering(TM) { 33 34 // Fold away setcc operations if possible. 35 setSetCCIsExpensive(); 36 setPow2DivIsCheap(); 37 38 // Use _setjmp/_longjmp instead of setjmp/longjmp. 39 setUseUnderscoreSetJmpLongJmp(true); 40 41 // Set up the register classes. 42 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 43 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 44 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 45 46 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 47 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 48 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 49 50 // PowerPC does not have truncstore for i1. 51 setStoreXAction(MVT::i1, Promote); 52 53 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 54 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 55 56 // PowerPC has no intrinsics for these particular operations 57 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 58 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 59 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 60 61 // PowerPC has no SREM/UREM instructions 62 setOperationAction(ISD::SREM, MVT::i32, Expand); 63 setOperationAction(ISD::UREM, MVT::i32, Expand); 64 setOperationAction(ISD::SREM, MVT::i64, Expand); 65 setOperationAction(ISD::UREM, MVT::i64, Expand); 66 67 // We don't support sin/cos/sqrt/fmod 68 setOperationAction(ISD::FSIN , MVT::f64, Expand); 69 setOperationAction(ISD::FCOS , MVT::f64, Expand); 70 setOperationAction(ISD::FREM , MVT::f64, Expand); 71 setOperationAction(ISD::FSIN , MVT::f32, Expand); 72 setOperationAction(ISD::FCOS , MVT::f32, Expand); 73 setOperationAction(ISD::FREM , MVT::f32, Expand); 74 75 // If we're enabling GP optimizations, use hardware square root 76 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 77 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 78 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 79 } 80 81 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 82 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 83 84 // PowerPC does not have BSWAP, CTPOP or CTTZ 85 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 86 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 87 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 88 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 89 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 90 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 91 92 // PowerPC does not have ROTR 93 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 94 95 // PowerPC does not have Select 96 setOperationAction(ISD::SELECT, MVT::i32, Expand); 97 setOperationAction(ISD::SELECT, MVT::i64, Expand); 98 setOperationAction(ISD::SELECT, MVT::f32, Expand); 99 setOperationAction(ISD::SELECT, MVT::f64, Expand); 100 101 // PowerPC wants to turn select_cc of FP into fsel when possible. 102 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 103 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 104 105 // PowerPC wants to optimize integer setcc a bit 106 setOperationAction(ISD::SETCC, MVT::i32, Custom); 107 108 // PowerPC does not have BRCOND which requires SetCC 109 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 110 111 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 112 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 113 114 // PowerPC does not have [U|S]INT_TO_FP 115 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 116 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 117 118 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 119 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 120 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 121 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 122 123 // We cannot sextinreg(i1). Expand to shifts. 124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 125 126 127 // Support label based line numbers. 128 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 129 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 130 // FIXME - use subtarget debug flags 131 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) 132 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 133 134 // We want to legalize GlobalAddress and ConstantPool nodes into the 135 // appropriate instructions to materialize the address. 136 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 137 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 138 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 139 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 140 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 141 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 142 143 // RET must be custom lowered, to meet ABI requirements 144 setOperationAction(ISD::RET , MVT::Other, Custom); 145 146 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 147 setOperationAction(ISD::VASTART , MVT::Other, Custom); 148 149 // Use the default implementation. 150 setOperationAction(ISD::VAARG , MVT::Other, Expand); 151 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 152 setOperationAction(ISD::VAEND , MVT::Other, Expand); 153 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 154 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 155 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 156 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand); 157 158 // We want to custom lower some of our intrinsics. 159 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 160 161 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 162 // They also have instructions for converting between i64 and fp. 163 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 164 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 165 166 // FIXME: disable this lowered code. This generates 64-bit register values, 167 // and we don't model the fact that the top part is clobbered by calls. We 168 // need to flag these together so that the value isn't live across a call. 169 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 170 171 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 172 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 173 } else { 174 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 175 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 176 } 177 178 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 179 // 64 bit PowerPC implementations can support i64 types directly 180 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 181 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 182 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 183 } else { 184 // 32 bit PowerPC wants to expand i64 shifts itself. 185 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 186 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 187 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 188 } 189 190 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 191 // First set operation action for all vector types to expand. Then we 192 // will selectively turn on ones that can be effectively codegen'd. 193 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 194 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 195 // add/sub are legal for all supported vector VT's. 196 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 197 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 198 199 // We promote all shuffles to v16i8. 200 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 201 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 202 203 // We promote all non-typed operations to v4i32. 204 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 205 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 206 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 207 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 208 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 209 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 210 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 211 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 212 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 213 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 214 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 215 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 216 217 // No other operations are legal. 218 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 219 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 220 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 221 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 222 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 223 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 224 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 225 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 226 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 227 228 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 229 } 230 231 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 232 // with merges, splats, etc. 233 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 234 235 setOperationAction(ISD::AND , MVT::v4i32, Legal); 236 setOperationAction(ISD::OR , MVT::v4i32, Legal); 237 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 238 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 239 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 240 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 241 242 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 243 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 244 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 245 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 246 247 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 248 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 249 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 250 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 251 252 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 253 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 254 255 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 256 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 257 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 258 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 259 } 260 261 setSetCCResultType(MVT::i32); 262 setShiftAmountType(MVT::i32); 263 setSetCCResultContents(ZeroOrOneSetCCResult); 264 265 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) 266 setStackPointerRegisterToSaveRestore(PPC::X1); 267 else 268 setStackPointerRegisterToSaveRestore(PPC::R1); 269 270 // We have target-specific dag combine patterns for the following nodes: 271 setTargetDAGCombine(ISD::SINT_TO_FP); 272 setTargetDAGCombine(ISD::STORE); 273 setTargetDAGCombine(ISD::BR_CC); 274 setTargetDAGCombine(ISD::BSWAP); 275 276 computeRegisterProperties(); 277} 278 279const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 280 switch (Opcode) { 281 default: return 0; 282 case PPCISD::FSEL: return "PPCISD::FSEL"; 283 case PPCISD::FCFID: return "PPCISD::FCFID"; 284 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 285 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 286 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 287 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 288 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 289 case PPCISD::VPERM: return "PPCISD::VPERM"; 290 case PPCISD::Hi: return "PPCISD::Hi"; 291 case PPCISD::Lo: return "PPCISD::Lo"; 292 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 293 case PPCISD::SRL: return "PPCISD::SRL"; 294 case PPCISD::SRA: return "PPCISD::SRA"; 295 case PPCISD::SHL: return "PPCISD::SHL"; 296 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 297 case PPCISD::STD_32: return "PPCISD::STD_32"; 298 case PPCISD::CALL: return "PPCISD::CALL"; 299 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 300 case PPCISD::BCTRL: return "PPCISD::BCTRL"; 301 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 302 case PPCISD::MFCR: return "PPCISD::MFCR"; 303 case PPCISD::VCMP: return "PPCISD::VCMP"; 304 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 305 case PPCISD::LBRX: return "PPCISD::LBRX"; 306 case PPCISD::STBRX: return "PPCISD::STBRX"; 307 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 308 } 309} 310 311//===----------------------------------------------------------------------===// 312// Node matching predicates, for use by the tblgen matching code. 313//===----------------------------------------------------------------------===// 314 315/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 316static bool isFloatingPointZero(SDOperand Op) { 317 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 318 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 319 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 320 // Maybe this has already been legalized into the constant pool? 321 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 322 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 323 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 324 } 325 return false; 326} 327 328/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 329/// true if Op is undef or if it matches the specified value. 330static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 331 return Op.getOpcode() == ISD::UNDEF || 332 cast<ConstantSDNode>(Op)->getValue() == Val; 333} 334 335/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 336/// VPKUHUM instruction. 337bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 338 if (!isUnary) { 339 for (unsigned i = 0; i != 16; ++i) 340 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 341 return false; 342 } else { 343 for (unsigned i = 0; i != 8; ++i) 344 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 345 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 346 return false; 347 } 348 return true; 349} 350 351/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 352/// VPKUWUM instruction. 353bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 354 if (!isUnary) { 355 for (unsigned i = 0; i != 16; i += 2) 356 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 357 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 358 return false; 359 } else { 360 for (unsigned i = 0; i != 8; i += 2) 361 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 362 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 363 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 364 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 365 return false; 366 } 367 return true; 368} 369 370/// isVMerge - Common function, used to match vmrg* shuffles. 371/// 372static bool isVMerge(SDNode *N, unsigned UnitSize, 373 unsigned LHSStart, unsigned RHSStart) { 374 assert(N->getOpcode() == ISD::BUILD_VECTOR && 375 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 376 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 377 "Unsupported merge size!"); 378 379 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 380 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 381 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 382 LHSStart+j+i*UnitSize) || 383 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 384 RHSStart+j+i*UnitSize)) 385 return false; 386 } 387 return true; 388} 389 390/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 391/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 392bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 393 if (!isUnary) 394 return isVMerge(N, UnitSize, 8, 24); 395 return isVMerge(N, UnitSize, 8, 8); 396} 397 398/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 399/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 400bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 401 if (!isUnary) 402 return isVMerge(N, UnitSize, 0, 16); 403 return isVMerge(N, UnitSize, 0, 0); 404} 405 406 407/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 408/// amount, otherwise return -1. 409int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 410 assert(N->getOpcode() == ISD::BUILD_VECTOR && 411 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 412 // Find the first non-undef value in the shuffle mask. 413 unsigned i; 414 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 415 /*search*/; 416 417 if (i == 16) return -1; // all undef. 418 419 // Otherwise, check to see if the rest of the elements are consequtively 420 // numbered from this value. 421 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 422 if (ShiftAmt < i) return -1; 423 ShiftAmt -= i; 424 425 if (!isUnary) { 426 // Check the rest of the elements to see if they are consequtive. 427 for (++i; i != 16; ++i) 428 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 429 return -1; 430 } else { 431 // Check the rest of the elements to see if they are consequtive. 432 for (++i; i != 16; ++i) 433 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 434 return -1; 435 } 436 437 return ShiftAmt; 438} 439 440/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 441/// specifies a splat of a single element that is suitable for input to 442/// VSPLTB/VSPLTH/VSPLTW. 443bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 444 assert(N->getOpcode() == ISD::BUILD_VECTOR && 445 N->getNumOperands() == 16 && 446 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 447 448 // This is a splat operation if each element of the permute is the same, and 449 // if the value doesn't reference the second vector. 450 unsigned ElementBase = 0; 451 SDOperand Elt = N->getOperand(0); 452 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 453 ElementBase = EltV->getValue(); 454 else 455 return false; // FIXME: Handle UNDEF elements too! 456 457 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 458 return false; 459 460 // Check that they are consequtive. 461 for (unsigned i = 1; i != EltSize; ++i) { 462 if (!isa<ConstantSDNode>(N->getOperand(i)) || 463 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 464 return false; 465 } 466 467 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 468 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 469 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 470 assert(isa<ConstantSDNode>(N->getOperand(i)) && 471 "Invalid VECTOR_SHUFFLE mask!"); 472 for (unsigned j = 0; j != EltSize; ++j) 473 if (N->getOperand(i+j) != N->getOperand(j)) 474 return false; 475 } 476 477 return true; 478} 479 480/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 481/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 482unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 483 assert(isSplatShuffleMask(N, EltSize)); 484 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 485} 486 487/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 488/// by using a vspltis[bhw] instruction of the specified element size, return 489/// the constant being splatted. The ByteSize field indicates the number of 490/// bytes of each element [124] -> [bhw]. 491SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 492 SDOperand OpVal(0, 0); 493 494 // If ByteSize of the splat is bigger than the element size of the 495 // build_vector, then we have a case where we are checking for a splat where 496 // multiple elements of the buildvector are folded together into a single 497 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 498 unsigned EltSize = 16/N->getNumOperands(); 499 if (EltSize < ByteSize) { 500 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 501 SDOperand UniquedVals[4]; 502 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 503 504 // See if all of the elements in the buildvector agree across. 505 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 506 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 507 // If the element isn't a constant, bail fully out. 508 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 509 510 511 if (UniquedVals[i&(Multiple-1)].Val == 0) 512 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 513 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 514 return SDOperand(); // no match. 515 } 516 517 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 518 // either constant or undef values that are identical for each chunk. See 519 // if these chunks can form into a larger vspltis*. 520 521 // Check to see if all of the leading entries are either 0 or -1. If 522 // neither, then this won't fit into the immediate field. 523 bool LeadingZero = true; 524 bool LeadingOnes = true; 525 for (unsigned i = 0; i != Multiple-1; ++i) { 526 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 527 528 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 529 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 530 } 531 // Finally, check the least significant entry. 532 if (LeadingZero) { 533 if (UniquedVals[Multiple-1].Val == 0) 534 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 535 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 536 if (Val < 16) 537 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 538 } 539 if (LeadingOnes) { 540 if (UniquedVals[Multiple-1].Val == 0) 541 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 542 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 543 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 544 return DAG.getTargetConstant(Val, MVT::i32); 545 } 546 547 return SDOperand(); 548 } 549 550 // Check to see if this buildvec has a single non-undef value in its elements. 551 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 552 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 553 if (OpVal.Val == 0) 554 OpVal = N->getOperand(i); 555 else if (OpVal != N->getOperand(i)) 556 return SDOperand(); 557 } 558 559 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 560 561 unsigned ValSizeInBytes = 0; 562 uint64_t Value = 0; 563 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 564 Value = CN->getValue(); 565 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 566 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 567 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 568 Value = FloatToBits(CN->getValue()); 569 ValSizeInBytes = 4; 570 } 571 572 // If the splat value is larger than the element value, then we can never do 573 // this splat. The only case that we could fit the replicated bits into our 574 // immediate field for would be zero, and we prefer to use vxor for it. 575 if (ValSizeInBytes < ByteSize) return SDOperand(); 576 577 // If the element value is larger than the splat value, cut it in half and 578 // check to see if the two halves are equal. Continue doing this until we 579 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 580 while (ValSizeInBytes > ByteSize) { 581 ValSizeInBytes >>= 1; 582 583 // If the top half equals the bottom half, we're still ok. 584 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 585 (Value & ((1 << (8*ValSizeInBytes))-1))) 586 return SDOperand(); 587 } 588 589 // Properly sign extend the value. 590 int ShAmt = (4-ByteSize)*8; 591 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 592 593 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 594 if (MaskVal == 0) return SDOperand(); 595 596 // Finally, if this value fits in a 5 bit sext field, return it 597 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 598 return DAG.getTargetConstant(MaskVal, MVT::i32); 599 return SDOperand(); 600} 601 602//===----------------------------------------------------------------------===// 603// LowerOperation implementation 604//===----------------------------------------------------------------------===// 605 606static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 607 MVT::ValueType PtrVT = Op.getValueType(); 608 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 609 Constant *C = CP->getConstVal(); 610 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 611 SDOperand Zero = DAG.getConstant(0, PtrVT); 612 613 const TargetMachine &TM = DAG.getTarget(); 614 615 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 616 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 617 618 // If this is a non-darwin platform, we don't support non-static relo models 619 // yet. 620 if (TM.getRelocationModel() == Reloc::Static || 621 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 622 // Generate non-pic code that has direct accesses to the constant pool. 623 // The address of the global is just (hi(&g)+lo(&g)). 624 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 625 } 626 627 if (TM.getRelocationModel() == Reloc::PIC_) { 628 // With PIC, the first instruction is actually "GR+hi(&G)". 629 Hi = DAG.getNode(ISD::ADD, PtrVT, 630 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 631 } 632 633 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 634 return Lo; 635} 636 637static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 638 MVT::ValueType PtrVT = Op.getValueType(); 639 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 640 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 641 SDOperand Zero = DAG.getConstant(0, PtrVT); 642 643 const TargetMachine &TM = DAG.getTarget(); 644 645 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 646 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 647 648 // If this is a non-darwin platform, we don't support non-static relo models 649 // yet. 650 if (TM.getRelocationModel() == Reloc::Static || 651 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 652 // Generate non-pic code that has direct accesses to the constant pool. 653 // The address of the global is just (hi(&g)+lo(&g)). 654 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 655 } 656 657 if (TM.getRelocationModel() == Reloc::PIC_) { 658 // With PIC, the first instruction is actually "GR+hi(&G)". 659 Hi = DAG.getNode(ISD::ADD, PtrVT, 660 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 661 } 662 663 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 664 return Lo; 665} 666 667static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 668 MVT::ValueType PtrVT = Op.getValueType(); 669 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 670 GlobalValue *GV = GSDN->getGlobal(); 671 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 672 SDOperand Zero = DAG.getConstant(0, PtrVT); 673 674 const TargetMachine &TM = DAG.getTarget(); 675 676 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 677 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 678 679 // If this is a non-darwin platform, we don't support non-static relo models 680 // yet. 681 if (TM.getRelocationModel() == Reloc::Static || 682 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 683 // Generate non-pic code that has direct accesses to globals. 684 // The address of the global is just (hi(&g)+lo(&g)). 685 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 686 } 687 688 if (TM.getRelocationModel() == Reloc::PIC_) { 689 // With PIC, the first instruction is actually "GR+hi(&G)". 690 Hi = DAG.getNode(ISD::ADD, PtrVT, 691 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 692 } 693 694 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 695 696 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && 697 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode())) 698 return Lo; 699 700 // If the global is weak or external, we have to go through the lazy 701 // resolution stub. 702 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 703} 704 705static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 706 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 707 708 // If we're comparing for equality to zero, expose the fact that this is 709 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 710 // fold the new nodes. 711 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 712 if (C->isNullValue() && CC == ISD::SETEQ) { 713 MVT::ValueType VT = Op.getOperand(0).getValueType(); 714 SDOperand Zext = Op.getOperand(0); 715 if (VT < MVT::i32) { 716 VT = MVT::i32; 717 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 718 } 719 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 720 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 721 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 722 DAG.getConstant(Log2b, MVT::i32)); 723 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 724 } 725 // Leave comparisons against 0 and -1 alone for now, since they're usually 726 // optimized. FIXME: revisit this when we can custom lower all setcc 727 // optimizations. 728 if (C->isAllOnesValue() || C->isNullValue()) 729 return SDOperand(); 730 } 731 732 // If we have an integer seteq/setne, turn it into a compare against zero 733 // by subtracting the rhs from the lhs, which is faster than setting a 734 // condition register, reading it back out, and masking the correct bit. 735 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 736 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 737 MVT::ValueType VT = Op.getValueType(); 738 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0), 739 Op.getOperand(1)); 740 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 741 } 742 return SDOperand(); 743} 744 745static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 746 unsigned VarArgsFrameIndex) { 747 // vastart just stores the address of the VarArgsFrameIndex slot into the 748 // memory location argument. 749 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 750 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 751 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 752 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 753 SV->getOffset()); 754} 755 756static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 757 int &VarArgsFrameIndex) { 758 // TODO: add description of PPC stack frame format, or at least some docs. 759 // 760 MachineFunction &MF = DAG.getMachineFunction(); 761 MachineFrameInfo *MFI = MF.getFrameInfo(); 762 SSARegMap *RegMap = MF.getSSARegMap(); 763 SmallVector<SDOperand, 8> ArgValues; 764 SDOperand Root = Op.getOperand(0); 765 766 unsigned ArgOffset = 24; 767 const unsigned Num_GPR_Regs = 8; 768 const unsigned Num_FPR_Regs = 13; 769 const unsigned Num_VR_Regs = 12; 770 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 771 772 static const unsigned GPR_32[] = { // 32-bit registers. 773 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 774 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 775 }; 776 static const unsigned GPR_64[] = { // 64-bit registers. 777 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 778 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 779 }; 780 static const unsigned FPR[] = { 781 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 782 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 783 }; 784 static const unsigned VR[] = { 785 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 786 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 787 }; 788 789 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 790 bool isPPC64 = PtrVT == MVT::i64; 791 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 792 793 // Add DAG nodes to load the arguments or copy them out of registers. On 794 // entry to a function on PPC, the arguments start at offset 24, although the 795 // first ones are often in registers. 796 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 797 SDOperand ArgVal; 798 bool needsLoad = false; 799 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 800 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 801 802 unsigned CurArgOffset = ArgOffset; 803 switch (ObjectVT) { 804 default: assert(0 && "Unhandled argument type!"); 805 case MVT::i32: 806 // All int arguments reserve stack space. 807 ArgOffset += isPPC64 ? 8 : 4; 808 809 if (GPR_idx != Num_GPR_Regs) { 810 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 811 MF.addLiveIn(GPR[GPR_idx], VReg); 812 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 813 ++GPR_idx; 814 } else { 815 needsLoad = true; 816 } 817 break; 818 case MVT::i64: // PPC64 819 // All int arguments reserve stack space. 820 ArgOffset += 8; 821 822 if (GPR_idx != Num_GPR_Regs) { 823 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 824 MF.addLiveIn(GPR[GPR_idx], VReg); 825 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 826 ++GPR_idx; 827 } else { 828 needsLoad = true; 829 } 830 break; 831 case MVT::f32: 832 case MVT::f64: 833 // All FP arguments reserve stack space. 834 ArgOffset += ObjSize; 835 836 // Every 4 bytes of argument space consumes one of the GPRs available for 837 // argument passing. 838 if (GPR_idx != Num_GPR_Regs) { 839 ++GPR_idx; 840 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs) 841 ++GPR_idx; 842 } 843 if (FPR_idx != Num_FPR_Regs) { 844 unsigned VReg; 845 if (ObjectVT == MVT::f32) 846 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 847 else 848 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 849 MF.addLiveIn(FPR[FPR_idx], VReg); 850 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 851 ++FPR_idx; 852 } else { 853 needsLoad = true; 854 } 855 break; 856 case MVT::v4f32: 857 case MVT::v4i32: 858 case MVT::v8i16: 859 case MVT::v16i8: 860 // Note that vector arguments in registers don't reserve stack space. 861 if (VR_idx != Num_VR_Regs) { 862 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); 863 MF.addLiveIn(VR[VR_idx], VReg); 864 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 865 ++VR_idx; 866 } else { 867 // This should be simple, but requires getting 16-byte aligned stack 868 // values. 869 assert(0 && "Loading VR argument not implemented yet!"); 870 needsLoad = true; 871 } 872 break; 873 } 874 875 // We need to load the argument to a virtual register if we determined above 876 // that we ran out of physical registers of the appropriate type 877 if (needsLoad) { 878 // If the argument is actually used, emit a load from the right stack 879 // slot. 880 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 881 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); 882 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 883 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 884 } else { 885 // Don't emit a dead load. 886 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); 887 } 888 } 889 890 ArgValues.push_back(ArgVal); 891 } 892 893 // If the function takes variable number of arguments, make a frame index for 894 // the start of the first vararg value... for expansion of llvm.va_start. 895 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 896 if (isVarArg) { 897 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 898 ArgOffset); 899 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 900 // If this function is vararg, store any remaining integer argument regs 901 // to their spots on the stack so that they may be loaded by deferencing the 902 // result of va_next. 903 SmallVector<SDOperand, 8> MemOps; 904 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 905 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 906 MF.addLiveIn(GPR[GPR_idx], VReg); 907 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 908 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 909 MemOps.push_back(Store); 910 // Increment the address by four for the next argument to store 911 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 912 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 913 } 914 if (!MemOps.empty()) 915 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 916 } 917 918 ArgValues.push_back(Root); 919 920 // Return the new list of results. 921 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 922 Op.Val->value_end()); 923 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 924} 925 926/// isCallCompatibleAddress - Return the immediate to use if the specified 927/// 32-bit value is representable in the immediate field of a BxA instruction. 928static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 930 if (!C) return 0; 931 932 int Addr = C->getValue(); 933 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 934 (Addr << 6 >> 6) != Addr) 935 return 0; // Top 6 bits have to be sext of immediate. 936 937 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val; 938} 939 940 941static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { 942 SDOperand Chain = Op.getOperand(0); 943 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 944 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 945 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 946 SDOperand Callee = Op.getOperand(4); 947 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 948 949 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 950 bool isPPC64 = PtrVT == MVT::i64; 951 unsigned PtrByteSize = isPPC64 ? 8 : 4; 952 953 954 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 955 // SelectExpr to use to put the arguments in the appropriate registers. 956 std::vector<SDOperand> args_to_use; 957 958 // Count how many bytes are to be pushed on the stack, including the linkage 959 // area, and parameter passing area. We start with 24/48 bytes, which is 960 // prereserved space for [SP][CR][LR][3 x unused]. 961 unsigned NumBytes = 6*PtrByteSize; 962 963 // Add up all the space actually used. 964 for (unsigned i = 0; i != NumOps; ++i) 965 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 966 967 // The prolog code of the callee may store up to 8 GPR argument registers to 968 // the stack, allowing va_start to index over them in memory if its varargs. 969 // Because we cannot tell if this is needed on the caller side, we have to 970 // conservatively assume that it is needed. As such, make sure we have at 971 // least enough stack space for the caller to store the 8 GPRs. 972 if (NumBytes < 6*PtrByteSize+8*PtrByteSize) 973 NumBytes = 6*PtrByteSize+8*PtrByteSize; 974 975 // Adjust the stack pointer for the new arguments... 976 // These operations are automatically eliminated by the prolog/epilog pass 977 Chain = DAG.getCALLSEQ_START(Chain, 978 DAG.getConstant(NumBytes, PtrVT)); 979 980 // Set up a copy of the stack pointer for use loading and storing any 981 // arguments that may not fit in the registers available for argument 982 // passing. 983 SDOperand StackPtr; 984 if (isPPC64) 985 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 986 else 987 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 988 989 // Figure out which arguments are going to go in registers, and which in 990 // memory. Also, if this is a vararg function, floating point operations 991 // must be stored to our stack, and loaded into integer regs as well, if 992 // any integer regs are available for argument passing. 993 unsigned ArgOffset = 6*PtrByteSize; 994 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 995 static const unsigned GPR_32[] = { // 32-bit registers. 996 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 997 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 998 }; 999 static const unsigned GPR_64[] = { // 64-bit registers. 1000 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1001 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1002 }; 1003 static const unsigned FPR[] = { 1004 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1005 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1006 }; 1007 static const unsigned VR[] = { 1008 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1009 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1010 }; 1011 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]); 1012 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]); 1013 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]); 1014 1015 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1016 1017 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1018 SmallVector<SDOperand, 8> MemOpChains; 1019 for (unsigned i = 0; i != NumOps; ++i) { 1020 SDOperand Arg = Op.getOperand(5+2*i); 1021 1022 // PtrOff will be used to store the current argument to the stack if a 1023 // register cannot be found for it. 1024 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1025 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1026 1027 // On PPC64, promote integers to 64-bit values. 1028 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1029 unsigned ExtOp = ISD::ZERO_EXTEND; 1030 if (cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue()) 1031 ExtOp = ISD::SIGN_EXTEND; 1032 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1033 } 1034 1035 switch (Arg.getValueType()) { 1036 default: assert(0 && "Unexpected ValueType for argument!"); 1037 case MVT::i32: 1038 case MVT::i64: 1039 if (GPR_idx != NumGPRs) { 1040 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1041 } else { 1042 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1043 } 1044 ArgOffset += PtrByteSize; 1045 break; 1046 case MVT::f32: 1047 case MVT::f64: 1048 if (FPR_idx != NumFPRs) { 1049 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1050 1051 if (isVarArg) { 1052 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1053 MemOpChains.push_back(Store); 1054 1055 // Float varargs are always shadowed in available integer registers 1056 if (GPR_idx != NumGPRs) { 1057 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1058 MemOpChains.push_back(Load.getValue(1)); 1059 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 1060 } 1061 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) { 1062 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1063 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1064 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1065 MemOpChains.push_back(Load.getValue(1)); 1066 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 1067 } 1068 } else { 1069 // If we have any FPRs remaining, we may also have GPRs remaining. 1070 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1071 // GPRs. 1072 if (GPR_idx != NumGPRs) 1073 ++GPR_idx; 1074 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64) 1075 ++GPR_idx; 1076 } 1077 } else { 1078 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1079 } 1080 if (isPPC64) 1081 ArgOffset += 8; 1082 else 1083 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1084 break; 1085 case MVT::v4f32: 1086 case MVT::v4i32: 1087 case MVT::v8i16: 1088 case MVT::v16i8: 1089 assert(!isVarArg && "Don't support passing vectors to varargs yet!"); 1090 assert(VR_idx != NumVRs && 1091 "Don't support passing more than 12 vector args yet!"); 1092 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 1093 break; 1094 } 1095 } 1096 if (!MemOpChains.empty()) 1097 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1098 &MemOpChains[0], MemOpChains.size()); 1099 1100 // Build a sequence of copy-to-reg nodes chained together with token chain 1101 // and flag operands which copy the outgoing args into the appropriate regs. 1102 SDOperand InFlag; 1103 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1104 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1105 InFlag); 1106 InFlag = Chain.getValue(1); 1107 } 1108 1109 std::vector<MVT::ValueType> NodeTys; 1110 NodeTys.push_back(MVT::Other); // Returns a chain 1111 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1112 1113 SmallVector<SDOperand, 8> Ops; 1114 unsigned CallOpc = PPCISD::CALL; 1115 1116 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1117 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1118 // node so that legalize doesn't hack it. 1119 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1120 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 1121 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1122 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 1123 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 1124 // If this is an absolute destination address, use the munged value. 1125 Callee = SDOperand(Dest, 0); 1126 else { 1127 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 1128 // to do the call, we can't use PPCISD::CALL. 1129 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 1130 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 1131 InFlag = Chain.getValue(1); 1132 1133 // Copy the callee address into R12 on darwin. 1134 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); 1135 InFlag = Chain.getValue(1); 1136 1137 NodeTys.clear(); 1138 NodeTys.push_back(MVT::Other); 1139 NodeTys.push_back(MVT::Flag); 1140 Ops.push_back(Chain); 1141 CallOpc = PPCISD::BCTRL; 1142 Callee.Val = 0; 1143 } 1144 1145 // If this is a direct call, pass the chain and the callee. 1146 if (Callee.Val) { 1147 Ops.push_back(Chain); 1148 Ops.push_back(Callee); 1149 } 1150 1151 // Add argument registers to the end of the list so that they are known live 1152 // into the call. 1153 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1154 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1155 RegsToPass[i].second.getValueType())); 1156 1157 if (InFlag.Val) 1158 Ops.push_back(InFlag); 1159 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 1160 InFlag = Chain.getValue(1); 1161 1162 SDOperand ResultVals[3]; 1163 unsigned NumResults = 0; 1164 NodeTys.clear(); 1165 1166 // If the call has results, copy the values out of the ret val registers. 1167 switch (Op.Val->getValueType(0)) { 1168 default: assert(0 && "Unexpected ret value!"); 1169 case MVT::Other: break; 1170 case MVT::i32: 1171 if (Op.Val->getValueType(1) == MVT::i32) { 1172 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1); 1173 ResultVals[0] = Chain.getValue(0); 1174 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, 1175 Chain.getValue(2)).getValue(1); 1176 ResultVals[1] = Chain.getValue(0); 1177 NumResults = 2; 1178 NodeTys.push_back(MVT::i32); 1179 } else { 1180 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1181 ResultVals[0] = Chain.getValue(0); 1182 NumResults = 1; 1183 } 1184 NodeTys.push_back(MVT::i32); 1185 break; 1186 case MVT::i64: 1187 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 1188 ResultVals[0] = Chain.getValue(0); 1189 NumResults = 1; 1190 NodeTys.push_back(MVT::i64); 1191 break; 1192 case MVT::f32: 1193 case MVT::f64: 1194 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 1195 InFlag).getValue(1); 1196 ResultVals[0] = Chain.getValue(0); 1197 NumResults = 1; 1198 NodeTys.push_back(Op.Val->getValueType(0)); 1199 break; 1200 case MVT::v4f32: 1201 case MVT::v4i32: 1202 case MVT::v8i16: 1203 case MVT::v16i8: 1204 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 1205 InFlag).getValue(1); 1206 ResultVals[0] = Chain.getValue(0); 1207 NumResults = 1; 1208 NodeTys.push_back(Op.Val->getValueType(0)); 1209 break; 1210 } 1211 1212 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 1213 DAG.getConstant(NumBytes, PtrVT)); 1214 NodeTys.push_back(MVT::Other); 1215 1216 // If the function returns void, just return the chain. 1217 if (NumResults == 0) 1218 return Chain; 1219 1220 // Otherwise, merge everything together with a MERGE_VALUES node. 1221 ResultVals[NumResults++] = Chain; 1222 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1223 ResultVals, NumResults); 1224 return Res.getValue(Op.ResNo); 1225} 1226 1227static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 1228 SDOperand Copy; 1229 switch(Op.getNumOperands()) { 1230 default: 1231 assert(0 && "Do not know how to return this many arguments!"); 1232 abort(); 1233 case 1: 1234 return SDOperand(); // ret void is legal 1235 case 3: { 1236 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 1237 unsigned ArgReg; 1238 if (ArgVT == MVT::i32) { 1239 ArgReg = PPC::R3; 1240 } else if (ArgVT == MVT::i64) { 1241 ArgReg = PPC::X3; 1242 } else if (MVT::isVector(ArgVT)) { 1243 ArgReg = PPC::V2; 1244 } else { 1245 assert(MVT::isFloatingPoint(ArgVT)); 1246 ArgReg = PPC::F1; 1247 } 1248 1249 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 1250 SDOperand()); 1251 1252 // If we haven't noted the R3/F1 are live out, do so now. 1253 if (DAG.getMachineFunction().liveout_empty()) 1254 DAG.getMachineFunction().addLiveOut(ArgReg); 1255 break; 1256 } 1257 case 5: 1258 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3), 1259 SDOperand()); 1260 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); 1261 // If we haven't noted the R3+R4 are live out, do so now. 1262 if (DAG.getMachineFunction().liveout_empty()) { 1263 DAG.getMachineFunction().addLiveOut(PPC::R3); 1264 DAG.getMachineFunction().addLiveOut(PPC::R4); 1265 } 1266 break; 1267 } 1268 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 1269} 1270 1271/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 1272/// possible. 1273static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 1274 // Not FP? Not a fsel. 1275 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 1276 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 1277 return SDOperand(); 1278 1279 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1280 1281 // Cannot handle SETEQ/SETNE. 1282 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 1283 1284 MVT::ValueType ResVT = Op.getValueType(); 1285 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 1286 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 1287 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 1288 1289 // If the RHS of the comparison is a 0.0, we don't need to do the 1290 // subtraction at all. 1291 if (isFloatingPointZero(RHS)) 1292 switch (CC) { 1293 default: break; // SETUO etc aren't handled by fsel. 1294 case ISD::SETULT: 1295 case ISD::SETOLT: 1296 case ISD::SETLT: 1297 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 1298 case ISD::SETUGE: 1299 case ISD::SETOGE: 1300 case ISD::SETGE: 1301 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 1302 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 1303 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 1304 case ISD::SETUGT: 1305 case ISD::SETOGT: 1306 case ISD::SETGT: 1307 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 1308 case ISD::SETULE: 1309 case ISD::SETOLE: 1310 case ISD::SETLE: 1311 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 1312 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 1313 return DAG.getNode(PPCISD::FSEL, ResVT, 1314 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 1315 } 1316 1317 SDOperand Cmp; 1318 switch (CC) { 1319 default: break; // SETUO etc aren't handled by fsel. 1320 case ISD::SETULT: 1321 case ISD::SETOLT: 1322 case ISD::SETLT: 1323 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 1324 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1325 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1326 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 1327 case ISD::SETUGE: 1328 case ISD::SETOGE: 1329 case ISD::SETGE: 1330 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 1331 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1332 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1333 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 1334 case ISD::SETUGT: 1335 case ISD::SETOGT: 1336 case ISD::SETGT: 1337 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 1338 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1339 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1340 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 1341 case ISD::SETULE: 1342 case ISD::SETOLE: 1343 case ISD::SETLE: 1344 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 1345 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1346 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1347 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 1348 } 1349 return SDOperand(); 1350} 1351 1352static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 1353 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 1354 SDOperand Src = Op.getOperand(0); 1355 if (Src.getValueType() == MVT::f32) 1356 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 1357 1358 SDOperand Tmp; 1359 switch (Op.getValueType()) { 1360 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 1361 case MVT::i32: 1362 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 1363 break; 1364 case MVT::i64: 1365 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 1366 break; 1367 } 1368 1369 // Convert the FP value to an int value through memory. 1370 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 1371 if (Op.getValueType() == MVT::i32) 1372 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 1373 return Bits; 1374} 1375 1376static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 1377 if (Op.getOperand(0).getValueType() == MVT::i64) { 1378 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 1379 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 1380 if (Op.getValueType() == MVT::f32) 1381 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 1382 return FP; 1383 } 1384 1385 assert(Op.getOperand(0).getValueType() == MVT::i32 && 1386 "Unhandled SINT_TO_FP type in custom expander!"); 1387 // Since we only generate this in 64-bit mode, we can take advantage of 1388 // 64-bit registers. In particular, sign extend the input value into the 1389 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 1390 // then lfd it and fcfid it. 1391 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 1392 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 1393 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1394 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 1395 1396 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 1397 Op.getOperand(0)); 1398 1399 // STD the extended value into the stack slot. 1400 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 1401 DAG.getEntryNode(), Ext64, FIdx, 1402 DAG.getSrcValue(NULL)); 1403 // Load the value as a double. 1404 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 1405 1406 // FCFID it and return it. 1407 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 1408 if (Op.getValueType() == MVT::f32) 1409 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 1410 return FP; 1411} 1412 1413static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 1414 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1415 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 1416 1417 // Expand into a bunch of logical ops. Note that these ops 1418 // depend on the PPC behavior for oversized shift amounts. 1419 SDOperand Lo = Op.getOperand(0); 1420 SDOperand Hi = Op.getOperand(1); 1421 SDOperand Amt = Op.getOperand(2); 1422 1423 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1424 DAG.getConstant(32, MVT::i32), Amt); 1425 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 1426 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 1427 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1428 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1429 DAG.getConstant(-32U, MVT::i32)); 1430 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 1431 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 1432 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 1433 SDOperand OutOps[] = { OutLo, OutHi }; 1434 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1435 OutOps, 2); 1436} 1437 1438static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 1439 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1440 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); 1441 1442 // Otherwise, expand into a bunch of logical ops. Note that these ops 1443 // depend on the PPC behavior for oversized shift amounts. 1444 SDOperand Lo = Op.getOperand(0); 1445 SDOperand Hi = Op.getOperand(1); 1446 SDOperand Amt = Op.getOperand(2); 1447 1448 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1449 DAG.getConstant(32, MVT::i32), Amt); 1450 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 1451 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 1452 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1453 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1454 DAG.getConstant(-32U, MVT::i32)); 1455 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 1456 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 1457 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 1458 SDOperand OutOps[] = { OutLo, OutHi }; 1459 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1460 OutOps, 2); 1461} 1462 1463static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 1464 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1465 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 1466 1467 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 1468 SDOperand Lo = Op.getOperand(0); 1469 SDOperand Hi = Op.getOperand(1); 1470 SDOperand Amt = Op.getOperand(2); 1471 1472 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1473 DAG.getConstant(32, MVT::i32), Amt); 1474 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 1475 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 1476 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1477 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1478 DAG.getConstant(-32U, MVT::i32)); 1479 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 1480 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 1481 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 1482 Tmp4, Tmp6, ISD::SETLE); 1483 SDOperand OutOps[] = { OutLo, OutHi }; 1484 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1485 OutOps, 2); 1486} 1487 1488//===----------------------------------------------------------------------===// 1489// Vector related lowering. 1490// 1491 1492// If this is a vector of constants or undefs, get the bits. A bit in 1493// UndefBits is set if the corresponding element of the vector is an 1494// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 1495// zero. Return true if this is not an array of constants, false if it is. 1496// 1497static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 1498 uint64_t UndefBits[2]) { 1499 // Start with zero'd results. 1500 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 1501 1502 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 1503 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 1504 SDOperand OpVal = BV->getOperand(i); 1505 1506 unsigned PartNo = i >= e/2; // In the upper 128 bits? 1507 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 1508 1509 uint64_t EltBits = 0; 1510 if (OpVal.getOpcode() == ISD::UNDEF) { 1511 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 1512 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 1513 continue; 1514 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 1515 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 1516 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 1517 assert(CN->getValueType(0) == MVT::f32 && 1518 "Only one legal FP vector type!"); 1519 EltBits = FloatToBits(CN->getValue()); 1520 } else { 1521 // Nonconstant element. 1522 return true; 1523 } 1524 1525 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 1526 } 1527 1528 //printf("%llx %llx %llx %llx\n", 1529 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 1530 return false; 1531} 1532 1533// If this is a splat (repetition) of a value across the whole vector, return 1534// the smallest size that splats it. For example, "0x01010101010101..." is a 1535// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 1536// SplatSize = 1 byte. 1537static bool isConstantSplat(const uint64_t Bits128[2], 1538 const uint64_t Undef128[2], 1539 unsigned &SplatBits, unsigned &SplatUndef, 1540 unsigned &SplatSize) { 1541 1542 // Don't let undefs prevent splats from matching. See if the top 64-bits are 1543 // the same as the lower 64-bits, ignoring undefs. 1544 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 1545 return false; // Can't be a splat if two pieces don't match. 1546 1547 uint64_t Bits64 = Bits128[0] | Bits128[1]; 1548 uint64_t Undef64 = Undef128[0] & Undef128[1]; 1549 1550 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 1551 // undefs. 1552 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 1553 return false; // Can't be a splat if two pieces don't match. 1554 1555 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 1556 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 1557 1558 // If the top 16-bits are different than the lower 16-bits, ignoring 1559 // undefs, we have an i32 splat. 1560 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 1561 SplatBits = Bits32; 1562 SplatUndef = Undef32; 1563 SplatSize = 4; 1564 return true; 1565 } 1566 1567 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 1568 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 1569 1570 // If the top 8-bits are different than the lower 8-bits, ignoring 1571 // undefs, we have an i16 splat. 1572 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 1573 SplatBits = Bits16; 1574 SplatUndef = Undef16; 1575 SplatSize = 2; 1576 return true; 1577 } 1578 1579 // Otherwise, we have an 8-bit splat. 1580 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 1581 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 1582 SplatSize = 1; 1583 return true; 1584} 1585 1586/// BuildSplatI - Build a canonical splati of Val with an element size of 1587/// SplatSize. Cast the result to VT. 1588static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 1589 SelectionDAG &DAG) { 1590 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 1591 1592 // Force vspltis[hw] -1 to vspltisb -1. 1593 if (Val == -1) SplatSize = 1; 1594 1595 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 1596 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 1597 }; 1598 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 1599 1600 // Build a canonical splat for this value. 1601 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT)); 1602 SmallVector<SDOperand, 8> Ops; 1603 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 1604 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 1605 &Ops[0], Ops.size()); 1606 return DAG.getNode(ISD::BIT_CONVERT, VT, Res); 1607} 1608 1609/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 1610/// specified intrinsic ID. 1611static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 1612 SelectionDAG &DAG, 1613 MVT::ValueType DestVT = MVT::Other) { 1614 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 1615 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 1616 DAG.getConstant(IID, MVT::i32), LHS, RHS); 1617} 1618 1619/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 1620/// specified intrinsic ID. 1621static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 1622 SDOperand Op2, SelectionDAG &DAG, 1623 MVT::ValueType DestVT = MVT::Other) { 1624 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 1625 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 1626 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 1627} 1628 1629 1630/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 1631/// amount. The result has the specified value type. 1632static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 1633 MVT::ValueType VT, SelectionDAG &DAG) { 1634 // Force LHS/RHS to be the right type. 1635 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 1636 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 1637 1638 SDOperand Ops[16]; 1639 for (unsigned i = 0; i != 16; ++i) 1640 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 1641 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 1642 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 1643 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 1644} 1645 1646// If this is a case we can't handle, return null and let the default 1647// expansion code take care of it. If we CAN select this case, and if it 1648// selects to a single instruction, return Op. Otherwise, if we can codegen 1649// this case more efficiently than a constant pool load, lower it to the 1650// sequence of ops that should be used. 1651static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 1652 // If this is a vector of constants or undefs, get the bits. A bit in 1653 // UndefBits is set if the corresponding element of the vector is an 1654 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 1655 // zero. 1656 uint64_t VectorBits[2]; 1657 uint64_t UndefBits[2]; 1658 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 1659 return SDOperand(); // Not a constant vector. 1660 1661 // If this is a splat (repetition) of a value across the whole vector, return 1662 // the smallest size that splats it. For example, "0x01010101010101..." is a 1663 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 1664 // SplatSize = 1 byte. 1665 unsigned SplatBits, SplatUndef, SplatSize; 1666 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 1667 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 1668 1669 // First, handle single instruction cases. 1670 1671 // All zeros? 1672 if (SplatBits == 0) { 1673 // Canonicalize all zero vectors to be v4i32. 1674 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 1675 SDOperand Z = DAG.getConstant(0, MVT::i32); 1676 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 1677 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 1678 } 1679 return Op; 1680 } 1681 1682 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 1683 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 1684 if (SextVal >= -16 && SextVal <= 15) 1685 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 1686 1687 1688 // Two instruction sequences. 1689 1690 // If this value is in the range [-32,30] and is even, use: 1691 // tmp = VSPLTI[bhw], result = add tmp, tmp 1692 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 1693 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 1694 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 1695 } 1696 1697 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 1698 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 1699 // for fneg/fabs. 1700 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 1701 // Make -1 and vspltisw -1: 1702 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 1703 1704 // Make the VSLW intrinsic, computing 0x8000_0000. 1705 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 1706 OnesV, DAG); 1707 1708 // xor by OnesV to invert it. 1709 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 1710 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 1711 } 1712 1713 // Check to see if this is a wide variety of vsplti*, binop self cases. 1714 unsigned SplatBitSize = SplatSize*8; 1715 static const char SplatCsts[] = { 1716 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 1717 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 1718 }; 1719 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){ 1720 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 1721 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 1722 int i = SplatCsts[idx]; 1723 1724 // Figure out what shift amount will be used by altivec if shifted by i in 1725 // this splat size. 1726 unsigned TypeShiftAmt = i & (SplatBitSize-1); 1727 1728 // vsplti + shl self. 1729 if (SextVal == (i << (int)TypeShiftAmt)) { 1730 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 1731 static const unsigned IIDs[] = { // Intrinsic to use for each size. 1732 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 1733 Intrinsic::ppc_altivec_vslw 1734 }; 1735 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 1736 } 1737 1738 // vsplti + srl self. 1739 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 1740 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 1741 static const unsigned IIDs[] = { // Intrinsic to use for each size. 1742 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 1743 Intrinsic::ppc_altivec_vsrw 1744 }; 1745 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 1746 } 1747 1748 // vsplti + sra self. 1749 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 1750 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 1751 static const unsigned IIDs[] = { // Intrinsic to use for each size. 1752 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 1753 Intrinsic::ppc_altivec_vsraw 1754 }; 1755 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 1756 } 1757 1758 // vsplti + rol self. 1759 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 1760 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 1761 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 1762 static const unsigned IIDs[] = { // Intrinsic to use for each size. 1763 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 1764 Intrinsic::ppc_altivec_vrlw 1765 }; 1766 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 1767 } 1768 1769 // t = vsplti c, result = vsldoi t, t, 1 1770 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 1771 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 1772 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 1773 } 1774 // t = vsplti c, result = vsldoi t, t, 2 1775 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 1776 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 1777 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 1778 } 1779 // t = vsplti c, result = vsldoi t, t, 3 1780 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 1781 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 1782 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 1783 } 1784 } 1785 1786 // Three instruction sequences. 1787 1788 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 1789 if (SextVal >= 0 && SextVal <= 31) { 1790 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG); 1791 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG); 1792 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS); 1793 } 1794 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 1795 if (SextVal >= -31 && SextVal <= 0) { 1796 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG); 1797 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG); 1798 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS); 1799 } 1800 } 1801 1802 return SDOperand(); 1803} 1804 1805/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 1806/// the specified operations to build the shuffle. 1807static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 1808 SDOperand RHS, SelectionDAG &DAG) { 1809 unsigned OpNum = (PFEntry >> 26) & 0x0F; 1810 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 1811 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 1812 1813 enum { 1814 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 1815 OP_VMRGHW, 1816 OP_VMRGLW, 1817 OP_VSPLTISW0, 1818 OP_VSPLTISW1, 1819 OP_VSPLTISW2, 1820 OP_VSPLTISW3, 1821 OP_VSLDOI4, 1822 OP_VSLDOI8, 1823 OP_VSLDOI12 1824 }; 1825 1826 if (OpNum == OP_COPY) { 1827 if (LHSID == (1*9+2)*9+3) return LHS; 1828 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 1829 return RHS; 1830 } 1831 1832 SDOperand OpLHS, OpRHS; 1833 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 1834 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 1835 1836 unsigned ShufIdxs[16]; 1837 switch (OpNum) { 1838 default: assert(0 && "Unknown i32 permute!"); 1839 case OP_VMRGHW: 1840 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 1841 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 1842 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 1843 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 1844 break; 1845 case OP_VMRGLW: 1846 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 1847 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 1848 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 1849 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 1850 break; 1851 case OP_VSPLTISW0: 1852 for (unsigned i = 0; i != 16; ++i) 1853 ShufIdxs[i] = (i&3)+0; 1854 break; 1855 case OP_VSPLTISW1: 1856 for (unsigned i = 0; i != 16; ++i) 1857 ShufIdxs[i] = (i&3)+4; 1858 break; 1859 case OP_VSPLTISW2: 1860 for (unsigned i = 0; i != 16; ++i) 1861 ShufIdxs[i] = (i&3)+8; 1862 break; 1863 case OP_VSPLTISW3: 1864 for (unsigned i = 0; i != 16; ++i) 1865 ShufIdxs[i] = (i&3)+12; 1866 break; 1867 case OP_VSLDOI4: 1868 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 1869 case OP_VSLDOI8: 1870 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 1871 case OP_VSLDOI12: 1872 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 1873 } 1874 SDOperand Ops[16]; 1875 for (unsigned i = 0; i != 16; ++i) 1876 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 1877 1878 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 1879 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 1880} 1881 1882/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 1883/// is a shuffle we can handle in a single instruction, return it. Otherwise, 1884/// return the code it can be lowered into. Worst case, it can always be 1885/// lowered into a vperm. 1886static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 1887 SDOperand V1 = Op.getOperand(0); 1888 SDOperand V2 = Op.getOperand(1); 1889 SDOperand PermMask = Op.getOperand(2); 1890 1891 // Cases that are handled by instructions that take permute immediates 1892 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 1893 // selected by the instruction selector. 1894 if (V2.getOpcode() == ISD::UNDEF) { 1895 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 1896 PPC::isSplatShuffleMask(PermMask.Val, 2) || 1897 PPC::isSplatShuffleMask(PermMask.Val, 4) || 1898 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 1899 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 1900 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 1901 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 1902 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 1903 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 1904 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 1905 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 1906 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 1907 return Op; 1908 } 1909 } 1910 1911 // Altivec has a variety of "shuffle immediates" that take two vector inputs 1912 // and produce a fixed permutation. If any of these match, do not lower to 1913 // VPERM. 1914 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 1915 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 1916 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 1917 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 1918 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 1919 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 1920 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 1921 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 1922 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 1923 return Op; 1924 1925 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 1926 // perfect shuffle table to emit an optimal matching sequence. 1927 unsigned PFIndexes[4]; 1928 bool isFourElementShuffle = true; 1929 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 1930 unsigned EltNo = 8; // Start out undef. 1931 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 1932 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 1933 continue; // Undef, ignore it. 1934 1935 unsigned ByteSource = 1936 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 1937 if ((ByteSource & 3) != j) { 1938 isFourElementShuffle = false; 1939 break; 1940 } 1941 1942 if (EltNo == 8) { 1943 EltNo = ByteSource/4; 1944 } else if (EltNo != ByteSource/4) { 1945 isFourElementShuffle = false; 1946 break; 1947 } 1948 } 1949 PFIndexes[i] = EltNo; 1950 } 1951 1952 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 1953 // perfect shuffle vector to determine if it is cost effective to do this as 1954 // discrete instructions, or whether we should use a vperm. 1955 if (isFourElementShuffle) { 1956 // Compute the index in the perfect shuffle table. 1957 unsigned PFTableIndex = 1958 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 1959 1960 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 1961 unsigned Cost = (PFEntry >> 30); 1962 1963 // Determining when to avoid vperm is tricky. Many things affect the cost 1964 // of vperm, particularly how many times the perm mask needs to be computed. 1965 // For example, if the perm mask can be hoisted out of a loop or is already 1966 // used (perhaps because there are multiple permutes with the same shuffle 1967 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 1968 // the loop requires an extra register. 1969 // 1970 // As a compromise, we only emit discrete instructions if the shuffle can be 1971 // generated in 3 or fewer operations. When we have loop information 1972 // available, if this block is within a loop, we should avoid using vperm 1973 // for 3-operation perms and use a constant pool load instead. 1974 if (Cost < 3) 1975 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 1976 } 1977 1978 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 1979 // vector that will get spilled to the constant pool. 1980 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 1981 1982 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 1983 // that it is in input element units, not in bytes. Convert now. 1984 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType()); 1985 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 1986 1987 SmallVector<SDOperand, 16> ResultMask; 1988 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 1989 unsigned SrcElt; 1990 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 1991 SrcElt = 0; 1992 else 1993 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 1994 1995 for (unsigned j = 0; j != BytesPerElement; ++j) 1996 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 1997 MVT::i8)); 1998 } 1999 2000 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 2001 &ResultMask[0], ResultMask.size()); 2002 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 2003} 2004 2005/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 2006/// altivec comparison. If it is, return true and fill in Opc/isDot with 2007/// information about the intrinsic. 2008static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 2009 bool &isDot) { 2010 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 2011 CompareOpc = -1; 2012 isDot = false; 2013 switch (IntrinsicID) { 2014 default: return false; 2015 // Comparison predicates. 2016 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 2017 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 2018 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 2019 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 2020 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 2021 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 2022 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 2023 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 2024 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 2025 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 2026 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 2027 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 2028 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 2029 2030 // Normal Comparisons. 2031 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 2032 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 2033 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 2034 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 2035 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 2036 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 2037 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 2038 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 2039 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 2040 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 2041 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 2042 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 2043 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 2044 } 2045 return true; 2046} 2047 2048/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 2049/// lower, do it, otherwise return null. 2050static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 2051 // If this is a lowered altivec predicate compare, CompareOpc is set to the 2052 // opcode number of the comparison. 2053 int CompareOpc; 2054 bool isDot; 2055 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 2056 return SDOperand(); // Don't custom lower most intrinsics. 2057 2058 // If this is a non-dot comparison, make the VCMP node and we are done. 2059 if (!isDot) { 2060 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 2061 Op.getOperand(1), Op.getOperand(2), 2062 DAG.getConstant(CompareOpc, MVT::i32)); 2063 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 2064 } 2065 2066 // Create the PPCISD altivec 'dot' comparison node. 2067 SDOperand Ops[] = { 2068 Op.getOperand(2), // LHS 2069 Op.getOperand(3), // RHS 2070 DAG.getConstant(CompareOpc, MVT::i32) 2071 }; 2072 std::vector<MVT::ValueType> VTs; 2073 VTs.push_back(Op.getOperand(2).getValueType()); 2074 VTs.push_back(MVT::Flag); 2075 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2076 2077 // Now that we have the comparison, emit a copy from the CR to a GPR. 2078 // This is flagged to the above dot comparison. 2079 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 2080 DAG.getRegister(PPC::CR6, MVT::i32), 2081 CompNode.getValue(1)); 2082 2083 // Unpack the result based on how the target uses it. 2084 unsigned BitNo; // Bit # of CR6. 2085 bool InvertBit; // Invert result? 2086 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 2087 default: // Can't happen, don't crash on invalid number though. 2088 case 0: // Return the value of the EQ bit of CR6. 2089 BitNo = 0; InvertBit = false; 2090 break; 2091 case 1: // Return the inverted value of the EQ bit of CR6. 2092 BitNo = 0; InvertBit = true; 2093 break; 2094 case 2: // Return the value of the LT bit of CR6. 2095 BitNo = 2; InvertBit = false; 2096 break; 2097 case 3: // Return the inverted value of the LT bit of CR6. 2098 BitNo = 2; InvertBit = true; 2099 break; 2100 } 2101 2102 // Shift the bit into the low position. 2103 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 2104 DAG.getConstant(8-(3-BitNo), MVT::i32)); 2105 // Isolate the bit. 2106 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 2107 DAG.getConstant(1, MVT::i32)); 2108 2109 // If we are supposed to, toggle the bit. 2110 if (InvertBit) 2111 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 2112 DAG.getConstant(1, MVT::i32)); 2113 return Flags; 2114} 2115 2116static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2117 // Create a stack slot that is 16-byte aligned. 2118 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2119 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 2120 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2121 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2122 2123 // Store the input value into Value#0 of the stack slot. 2124 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 2125 Op.getOperand(0), FIdx, NULL, 0); 2126 // Load it out. 2127 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 2128} 2129 2130static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 2131 if (Op.getValueType() == MVT::v4i32) { 2132 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2133 2134 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 2135 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 2136 2137 SDOperand RHSSwap = // = vrlw RHS, 16 2138 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 2139 2140 // Shrinkify inputs to v8i16. 2141 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 2142 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 2143 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 2144 2145 // Low parts multiplied together, generating 32-bit results (we ignore the 2146 // top parts). 2147 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 2148 LHS, RHS, DAG, MVT::v4i32); 2149 2150 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 2151 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 2152 // Shift the high parts up 16 bits. 2153 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 2154 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 2155 } else if (Op.getValueType() == MVT::v8i16) { 2156 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2157 2158 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 2159 2160 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 2161 LHS, RHS, Zero, DAG); 2162 } else if (Op.getValueType() == MVT::v16i8) { 2163 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2164 2165 // Multiply the even 8-bit parts, producing 16-bit sums. 2166 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 2167 LHS, RHS, DAG, MVT::v8i16); 2168 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 2169 2170 // Multiply the odd 8-bit parts, producing 16-bit sums. 2171 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 2172 LHS, RHS, DAG, MVT::v8i16); 2173 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 2174 2175 // Merge the results together. 2176 SDOperand Ops[16]; 2177 for (unsigned i = 0; i != 8; ++i) { 2178 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 2179 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 2180 } 2181 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 2182 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2183 } else { 2184 assert(0 && "Unknown mul to lower!"); 2185 abort(); 2186 } 2187} 2188 2189/// LowerOperation - Provide custom lowering hooks for some operations. 2190/// 2191SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2192 switch (Op.getOpcode()) { 2193 default: assert(0 && "Wasn't expecting to be able to lower this!"); 2194 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2195 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2196 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 2197 case ISD::SETCC: return LowerSETCC(Op, DAG); 2198 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 2199 case ISD::FORMAL_ARGUMENTS: 2200 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex); 2201 case ISD::CALL: return LowerCALL(Op, DAG); 2202 case ISD::RET: return LowerRET(Op, DAG); 2203 2204 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 2205 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 2206 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 2207 2208 // Lower 64-bit shifts. 2209 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 2210 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 2211 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 2212 2213 // Vector-related lowering. 2214 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 2215 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 2216 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 2217 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 2218 case ISD::MUL: return LowerMUL(Op, DAG); 2219 } 2220 return SDOperand(); 2221} 2222 2223//===----------------------------------------------------------------------===// 2224// Other Lowering Code 2225//===----------------------------------------------------------------------===// 2226 2227MachineBasicBlock * 2228PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2229 MachineBasicBlock *BB) { 2230 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 2231 MI->getOpcode() == PPC::SELECT_CC_I8 || 2232 MI->getOpcode() == PPC::SELECT_CC_F4 || 2233 MI->getOpcode() == PPC::SELECT_CC_F8 || 2234 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 2235 "Unexpected instr type to insert"); 2236 2237 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 2238 // control-flow pattern. The incoming instruction knows the destination vreg 2239 // to set, the condition code register to branch on, the true/false values to 2240 // select between, and a branch opcode to use. 2241 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2242 ilist<MachineBasicBlock>::iterator It = BB; 2243 ++It; 2244 2245 // thisMBB: 2246 // ... 2247 // TrueVal = ... 2248 // cmpTY ccX, r1, r2 2249 // bCC copy1MBB 2250 // fallthrough --> copy0MBB 2251 MachineBasicBlock *thisMBB = BB; 2252 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 2253 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 2254 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 2255 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 2256 MachineFunction *F = BB->getParent(); 2257 F->getBasicBlockList().insert(It, copy0MBB); 2258 F->getBasicBlockList().insert(It, sinkMBB); 2259 // Update machine-CFG edges by first adding all successors of the current 2260 // block to the new block which will contain the Phi node for the select. 2261 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 2262 e = BB->succ_end(); i != e; ++i) 2263 sinkMBB->addSuccessor(*i); 2264 // Next, remove all successors of the current block, and add the true 2265 // and fallthrough blocks as its successors. 2266 while(!BB->succ_empty()) 2267 BB->removeSuccessor(BB->succ_begin()); 2268 BB->addSuccessor(copy0MBB); 2269 BB->addSuccessor(sinkMBB); 2270 2271 // copy0MBB: 2272 // %FalseValue = ... 2273 // # fallthrough to sinkMBB 2274 BB = copy0MBB; 2275 2276 // Update machine-CFG edges 2277 BB->addSuccessor(sinkMBB); 2278 2279 // sinkMBB: 2280 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 2281 // ... 2282 BB = sinkMBB; 2283 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 2284 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 2285 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 2286 2287 delete MI; // The pseudo instruction is gone now. 2288 return BB; 2289} 2290 2291//===----------------------------------------------------------------------===// 2292// Target Optimization Hooks 2293//===----------------------------------------------------------------------===// 2294 2295SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 2296 DAGCombinerInfo &DCI) const { 2297 TargetMachine &TM = getTargetMachine(); 2298 SelectionDAG &DAG = DCI.DAG; 2299 switch (N->getOpcode()) { 2300 default: break; 2301 case PPCISD::SHL: 2302 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2303 if (C->getValue() == 0) // 0 << V -> 0. 2304 return N->getOperand(0); 2305 } 2306 break; 2307 case PPCISD::SRL: 2308 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2309 if (C->getValue() == 0) // 0 >>u V -> 0. 2310 return N->getOperand(0); 2311 } 2312 break; 2313 case PPCISD::SRA: 2314 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2315 if (C->getValue() == 0 || // 0 >>s V -> 0. 2316 C->isAllOnesValue()) // -1 >>s V -> -1. 2317 return N->getOperand(0); 2318 } 2319 break; 2320 2321 case ISD::SINT_TO_FP: 2322 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 2323 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 2324 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 2325 // We allow the src/dst to be either f32/f64, but the intermediate 2326 // type must be i64. 2327 if (N->getOperand(0).getValueType() == MVT::i64) { 2328 SDOperand Val = N->getOperand(0).getOperand(0); 2329 if (Val.getValueType() == MVT::f32) { 2330 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 2331 DCI.AddToWorklist(Val.Val); 2332 } 2333 2334 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 2335 DCI.AddToWorklist(Val.Val); 2336 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 2337 DCI.AddToWorklist(Val.Val); 2338 if (N->getValueType(0) == MVT::f32) { 2339 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 2340 DCI.AddToWorklist(Val.Val); 2341 } 2342 return Val; 2343 } else if (N->getOperand(0).getValueType() == MVT::i32) { 2344 // If the intermediate type is i32, we can avoid the load/store here 2345 // too. 2346 } 2347 } 2348 } 2349 break; 2350 case ISD::STORE: 2351 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 2352 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 2353 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 2354 N->getOperand(1).getValueType() == MVT::i32) { 2355 SDOperand Val = N->getOperand(1).getOperand(0); 2356 if (Val.getValueType() == MVT::f32) { 2357 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 2358 DCI.AddToWorklist(Val.Val); 2359 } 2360 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 2361 DCI.AddToWorklist(Val.Val); 2362 2363 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 2364 N->getOperand(2), N->getOperand(3)); 2365 DCI.AddToWorklist(Val.Val); 2366 return Val; 2367 } 2368 2369 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 2370 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 2371 N->getOperand(1).Val->hasOneUse() && 2372 (N->getOperand(1).getValueType() == MVT::i32 || 2373 N->getOperand(1).getValueType() == MVT::i16)) { 2374 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 2375 // Do an any-extend to 32-bits if this is a half-word input. 2376 if (BSwapOp.getValueType() == MVT::i16) 2377 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 2378 2379 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 2380 N->getOperand(2), N->getOperand(3), 2381 DAG.getValueType(N->getOperand(1).getValueType())); 2382 } 2383 break; 2384 case ISD::BSWAP: 2385 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 2386 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 2387 N->getOperand(0).hasOneUse() && 2388 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 2389 SDOperand Load = N->getOperand(0); 2390 LoadSDNode *LD = cast<LoadSDNode>(Load); 2391 // Create the byte-swapping load. 2392 std::vector<MVT::ValueType> VTs; 2393 VTs.push_back(MVT::i32); 2394 VTs.push_back(MVT::Other); 2395 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); 2396 SDOperand Ops[] = { 2397 LD->getChain(), // Chain 2398 LD->getBasePtr(), // Ptr 2399 SV, // SrcValue 2400 DAG.getValueType(N->getValueType(0)) // VT 2401 }; 2402 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 2403 2404 // If this is an i16 load, insert the truncate. 2405 SDOperand ResVal = BSLoad; 2406 if (N->getValueType(0) == MVT::i16) 2407 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 2408 2409 // First, combine the bswap away. This makes the value produced by the 2410 // load dead. 2411 DCI.CombineTo(N, ResVal); 2412 2413 // Next, combine the load away, we give it a bogus result value but a real 2414 // chain result. The result value is dead because the bswap is dead. 2415 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 2416 2417 // Return N so it doesn't get rechecked! 2418 return SDOperand(N, 0); 2419 } 2420 2421 break; 2422 case PPCISD::VCMP: { 2423 // If a VCMPo node already exists with exactly the same operands as this 2424 // node, use its result instead of this node (VCMPo computes both a CR6 and 2425 // a normal output). 2426 // 2427 if (!N->getOperand(0).hasOneUse() && 2428 !N->getOperand(1).hasOneUse() && 2429 !N->getOperand(2).hasOneUse()) { 2430 2431 // Scan all of the users of the LHS, looking for VCMPo's that match. 2432 SDNode *VCMPoNode = 0; 2433 2434 SDNode *LHSN = N->getOperand(0).Val; 2435 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 2436 UI != E; ++UI) 2437 if ((*UI)->getOpcode() == PPCISD::VCMPo && 2438 (*UI)->getOperand(1) == N->getOperand(1) && 2439 (*UI)->getOperand(2) == N->getOperand(2) && 2440 (*UI)->getOperand(0) == N->getOperand(0)) { 2441 VCMPoNode = *UI; 2442 break; 2443 } 2444 2445 // If there is no VCMPo node, or if the flag value has a single use, don't 2446 // transform this. 2447 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 2448 break; 2449 2450 // Look at the (necessarily single) use of the flag value. If it has a 2451 // chain, this transformation is more complex. Note that multiple things 2452 // could use the value result, which we should ignore. 2453 SDNode *FlagUser = 0; 2454 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 2455 FlagUser == 0; ++UI) { 2456 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 2457 SDNode *User = *UI; 2458 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2459 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 2460 FlagUser = User; 2461 break; 2462 } 2463 } 2464 } 2465 2466 // If the user is a MFCR instruction, we know this is safe. Otherwise we 2467 // give up for right now. 2468 if (FlagUser->getOpcode() == PPCISD::MFCR) 2469 return SDOperand(VCMPoNode, 0); 2470 } 2471 break; 2472 } 2473 case ISD::BR_CC: { 2474 // If this is a branch on an altivec predicate comparison, lower this so 2475 // that we don't have to do a MFCR: instead, branch directly on CR6. This 2476 // lowering is done pre-legalize, because the legalizer lowers the predicate 2477 // compare down to code that is difficult to reassemble. 2478 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2479 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 2480 int CompareOpc; 2481 bool isDot; 2482 2483 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 2484 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 2485 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 2486 assert(isDot && "Can't compare against a vector result!"); 2487 2488 // If this is a comparison against something other than 0/1, then we know 2489 // that the condition is never/always true. 2490 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 2491 if (Val != 0 && Val != 1) { 2492 if (CC == ISD::SETEQ) // Cond never true, remove branch. 2493 return N->getOperand(0); 2494 // Always !=, turn it into an unconditional branch. 2495 return DAG.getNode(ISD::BR, MVT::Other, 2496 N->getOperand(0), N->getOperand(4)); 2497 } 2498 2499 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 2500 2501 // Create the PPCISD altivec 'dot' comparison node. 2502 std::vector<MVT::ValueType> VTs; 2503 SDOperand Ops[] = { 2504 LHS.getOperand(2), // LHS of compare 2505 LHS.getOperand(3), // RHS of compare 2506 DAG.getConstant(CompareOpc, MVT::i32) 2507 }; 2508 VTs.push_back(LHS.getOperand(2).getValueType()); 2509 VTs.push_back(MVT::Flag); 2510 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2511 2512 // Unpack the result based on how the target uses it. 2513 unsigned CompOpc; 2514 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 2515 default: // Can't happen, don't crash on invalid number though. 2516 case 0: // Branch on the value of the EQ bit of CR6. 2517 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE; 2518 break; 2519 case 1: // Branch on the inverted value of the EQ bit of CR6. 2520 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ; 2521 break; 2522 case 2: // Branch on the value of the LT bit of CR6. 2523 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE; 2524 break; 2525 case 3: // Branch on the inverted value of the LT bit of CR6. 2526 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT; 2527 break; 2528 } 2529 2530 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 2531 DAG.getRegister(PPC::CR6, MVT::i32), 2532 DAG.getConstant(CompOpc, MVT::i32), 2533 N->getOperand(4), CompNode.getValue(1)); 2534 } 2535 break; 2536 } 2537 } 2538 2539 return SDOperand(); 2540} 2541 2542//===----------------------------------------------------------------------===// 2543// Inline Assembly Support 2544//===----------------------------------------------------------------------===// 2545 2546void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 2547 uint64_t Mask, 2548 uint64_t &KnownZero, 2549 uint64_t &KnownOne, 2550 unsigned Depth) const { 2551 KnownZero = 0; 2552 KnownOne = 0; 2553 switch (Op.getOpcode()) { 2554 default: break; 2555 case PPCISD::LBRX: { 2556 // lhbrx is known to have the top bits cleared out. 2557 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 2558 KnownZero = 0xFFFF0000; 2559 break; 2560 } 2561 case ISD::INTRINSIC_WO_CHAIN: { 2562 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 2563 default: break; 2564 case Intrinsic::ppc_altivec_vcmpbfp_p: 2565 case Intrinsic::ppc_altivec_vcmpeqfp_p: 2566 case Intrinsic::ppc_altivec_vcmpequb_p: 2567 case Intrinsic::ppc_altivec_vcmpequh_p: 2568 case Intrinsic::ppc_altivec_vcmpequw_p: 2569 case Intrinsic::ppc_altivec_vcmpgefp_p: 2570 case Intrinsic::ppc_altivec_vcmpgtfp_p: 2571 case Intrinsic::ppc_altivec_vcmpgtsb_p: 2572 case Intrinsic::ppc_altivec_vcmpgtsh_p: 2573 case Intrinsic::ppc_altivec_vcmpgtsw_p: 2574 case Intrinsic::ppc_altivec_vcmpgtub_p: 2575 case Intrinsic::ppc_altivec_vcmpgtuh_p: 2576 case Intrinsic::ppc_altivec_vcmpgtuw_p: 2577 KnownZero = ~1U; // All bits but the low one are known to be zero. 2578 break; 2579 } 2580 } 2581 } 2582} 2583 2584 2585/// getConstraintType - Given a constraint letter, return the type of 2586/// constraint it is for this target. 2587PPCTargetLowering::ConstraintType 2588PPCTargetLowering::getConstraintType(char ConstraintLetter) const { 2589 switch (ConstraintLetter) { 2590 default: break; 2591 case 'b': 2592 case 'r': 2593 case 'f': 2594 case 'v': 2595 case 'y': 2596 return C_RegisterClass; 2597 } 2598 return TargetLowering::getConstraintType(ConstraintLetter); 2599} 2600 2601 2602std::vector<unsigned> PPCTargetLowering:: 2603getRegClassForInlineAsmConstraint(const std::string &Constraint, 2604 MVT::ValueType VT) const { 2605 if (Constraint.size() == 1) { 2606 switch (Constraint[0]) { // GCC RS6000 Constraint Letters 2607 default: break; // Unknown constriant letter 2608 case 'b': 2609 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 , 2610 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , 2611 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 2612 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 2613 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 2614 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 2615 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 2616 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 2617 0); 2618 case 'r': 2619 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 , 2620 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , 2621 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 2622 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 2623 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 2624 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 2625 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 2626 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 2627 0); 2628 case 'f': 2629 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 , 2630 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 , 2631 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11, 2632 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 2633 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 2634 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 2635 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 2636 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 2637 0); 2638 case 'v': 2639 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , 2640 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 2641 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, 2642 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 2643 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 2644 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 2645 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 2646 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 2647 0); 2648 case 'y': 2649 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 2650 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 2651 0); 2652 } 2653 } 2654 2655 return std::vector<unsigned>(); 2656} 2657 2658// isOperandValidForConstraint 2659bool PPCTargetLowering:: 2660isOperandValidForConstraint(SDOperand Op, char Letter) { 2661 switch (Letter) { 2662 default: break; 2663 case 'I': 2664 case 'J': 2665 case 'K': 2666 case 'L': 2667 case 'M': 2668 case 'N': 2669 case 'O': 2670 case 'P': { 2671 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate. 2672 unsigned Value = cast<ConstantSDNode>(Op)->getValue(); 2673 switch (Letter) { 2674 default: assert(0 && "Unknown constraint letter!"); 2675 case 'I': // "I" is a signed 16-bit constant. 2676 return (short)Value == (int)Value; 2677 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 2678 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 2679 return (short)Value == 0; 2680 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 2681 return (Value >> 16) == 0; 2682 case 'M': // "M" is a constant that is greater than 31. 2683 return Value > 31; 2684 case 'N': // "N" is a positive constant that is an exact power of two. 2685 return (int)Value > 0 && isPowerOf2_32(Value); 2686 case 'O': // "O" is the constant zero. 2687 return Value == 0; 2688 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 2689 return (short)-Value == (int)-Value; 2690 } 2691 break; 2692 } 2693 } 2694 2695 // Handle standard constraint letters. 2696 return TargetLowering::isOperandValidForConstraint(Op, Letter); 2697} 2698 2699/// isLegalAddressImmediate - Return true if the integer value can be used 2700/// as the offset of the target addressing mode. 2701bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const { 2702 // PPC allows a sign-extended 16-bit immediate field. 2703 return (V > -(1 << 16) && V < (1 << 16)-1); 2704} 2705 2706bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 2707 return TargetLowering::isLegalAddressImmediate(GV); 2708} 2709