PPCISelLowering.cpp revision 63f8fb1993bf2b4286c5a6763e2eee414a751699
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/VectorExtras.h" 20#include "llvm/Analysis/ScalarEvolutionExpressions.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/SSARegMap.h" 26#include "llvm/Constants.h" 27#include "llvm/Function.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Support/CommandLine.h" 32using namespace llvm; 33 34static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc"); 35 36PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 37 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 38 39 setPow2DivIsCheap(); 40 41 // Use _setjmp/_longjmp instead of setjmp/longjmp. 42 setUseUnderscoreSetJmp(true); 43 setUseUnderscoreLongJmp(true); 44 45 // Set up the register classes. 46 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 47 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 48 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 49 50 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 51 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 52 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 53 54 // PowerPC does not have truncstore for i1. 55 setStoreXAction(MVT::i1, Promote); 56 57 // PowerPC has pre-inc load and store's. 58 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 59 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 60 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 61 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 63 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 64 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 65 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 66 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 68 69 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 70 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 71 72 // PowerPC has no intrinsics for these particular operations 73 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 74 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 75 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 76 77 // PowerPC has no SREM/UREM instructions 78 setOperationAction(ISD::SREM, MVT::i32, Expand); 79 setOperationAction(ISD::UREM, MVT::i32, Expand); 80 setOperationAction(ISD::SREM, MVT::i64, Expand); 81 setOperationAction(ISD::UREM, MVT::i64, Expand); 82 83 // We don't support sin/cos/sqrt/fmod 84 setOperationAction(ISD::FSIN , MVT::f64, Expand); 85 setOperationAction(ISD::FCOS , MVT::f64, Expand); 86 setOperationAction(ISD::FREM , MVT::f64, Expand); 87 setOperationAction(ISD::FSIN , MVT::f32, Expand); 88 setOperationAction(ISD::FCOS , MVT::f32, Expand); 89 setOperationAction(ISD::FREM , MVT::f32, Expand); 90 91 // If we're enabling GP optimizations, use hardware square root 92 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 93 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 94 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 95 } 96 97 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 98 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 99 100 // PowerPC does not have BSWAP, CTPOP or CTTZ 101 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 102 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 103 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 104 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 105 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 106 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 107 108 // PowerPC does not have ROTR 109 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 110 111 // PowerPC does not have Select 112 setOperationAction(ISD::SELECT, MVT::i32, Expand); 113 setOperationAction(ISD::SELECT, MVT::i64, Expand); 114 setOperationAction(ISD::SELECT, MVT::f32, Expand); 115 setOperationAction(ISD::SELECT, MVT::f64, Expand); 116 117 // PowerPC wants to turn select_cc of FP into fsel when possible. 118 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 119 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 120 121 // PowerPC wants to optimize integer setcc a bit 122 setOperationAction(ISD::SETCC, MVT::i32, Custom); 123 124 // PowerPC does not have BRCOND which requires SetCC 125 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 126 127 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 128 129 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 130 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 131 132 // PowerPC does not have [U|S]INT_TO_FP 133 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 134 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 135 136 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 137 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 138 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 139 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 140 141 // We cannot sextinreg(i1). Expand to shifts. 142 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 143 144 // Support label based line numbers. 145 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 146 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 147 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) { 148 setOperationAction(ISD::LABEL, MVT::Other, Expand); 149 } else { 150 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 151 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 152 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 153 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 154 } 155 156 // We want to legalize GlobalAddress and ConstantPool nodes into the 157 // appropriate instructions to materialize the address. 158 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 159 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 160 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 161 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 162 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 163 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 164 165 // RET must be custom lowered, to meet ABI requirements 166 setOperationAction(ISD::RET , MVT::Other, Custom); 167 168 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 169 setOperationAction(ISD::VASTART , MVT::Other, Custom); 170 171 // Use the default implementation. 172 setOperationAction(ISD::VAARG , MVT::Other, Expand); 173 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 174 setOperationAction(ISD::VAEND , MVT::Other, Expand); 175 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 176 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 177 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 178 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 179 180 // We want to custom lower some of our intrinsics. 181 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 182 183 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 184 // They also have instructions for converting between i64 and fp. 185 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 186 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 187 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 188 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 190 191 // FIXME: disable this lowered code. This generates 64-bit register values, 192 // and we don't model the fact that the top part is clobbered by calls. We 193 // need to flag these together so that the value isn't live across a call. 194 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 195 196 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 197 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 198 } else { 199 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 200 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 201 } 202 203 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 204 // 64 bit PowerPC implementations can support i64 types directly 205 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 206 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 207 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 208 } else { 209 // 32 bit PowerPC wants to expand i64 shifts itself. 210 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 211 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 212 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 213 } 214 215 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 216 // First set operation action for all vector types to expand. Then we 217 // will selectively turn on ones that can be effectively codegen'd. 218 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 219 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 220 // add/sub are legal for all supported vector VT's. 221 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 222 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 223 224 // We promote all shuffles to v16i8. 225 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 226 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 227 228 // We promote all non-typed operations to v4i32. 229 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 230 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 231 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 232 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 233 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 234 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 235 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 236 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 237 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 238 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 239 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 240 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 241 242 // No other operations are legal. 243 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 244 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 245 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 246 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 247 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 248 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 249 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 250 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 251 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 252 253 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 254 } 255 256 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 257 // with merges, splats, etc. 258 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 259 260 setOperationAction(ISD::AND , MVT::v4i32, Legal); 261 setOperationAction(ISD::OR , MVT::v4i32, Legal); 262 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 263 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 264 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 265 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 266 267 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 268 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 269 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 270 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 271 272 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 273 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 274 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 275 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 276 277 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 278 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 279 280 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 281 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 282 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 283 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 284 } 285 286 setSetCCResultType(MVT::i32); 287 setShiftAmountType(MVT::i32); 288 setSetCCResultContents(ZeroOrOneSetCCResult); 289 290 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 291 setStackPointerRegisterToSaveRestore(PPC::X1); 292 setExceptionPointerRegister(PPC::X3); 293 setExceptionSelectorRegister(PPC::X4); 294 } else { 295 setStackPointerRegisterToSaveRestore(PPC::R1); 296 setExceptionPointerRegister(PPC::R3); 297 setExceptionSelectorRegister(PPC::R4); 298 } 299 300 // We have target-specific dag combine patterns for the following nodes: 301 setTargetDAGCombine(ISD::SINT_TO_FP); 302 setTargetDAGCombine(ISD::STORE); 303 setTargetDAGCombine(ISD::BR_CC); 304 setTargetDAGCombine(ISD::BSWAP); 305 306 computeRegisterProperties(); 307} 308 309const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 310 switch (Opcode) { 311 default: return 0; 312 case PPCISD::FSEL: return "PPCISD::FSEL"; 313 case PPCISD::FCFID: return "PPCISD::FCFID"; 314 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 315 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 316 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 317 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 318 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 319 case PPCISD::VPERM: return "PPCISD::VPERM"; 320 case PPCISD::Hi: return "PPCISD::Hi"; 321 case PPCISD::Lo: return "PPCISD::Lo"; 322 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 323 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 324 case PPCISD::SRL: return "PPCISD::SRL"; 325 case PPCISD::SRA: return "PPCISD::SRA"; 326 case PPCISD::SHL: return "PPCISD::SHL"; 327 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 328 case PPCISD::STD_32: return "PPCISD::STD_32"; 329 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 330 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 331 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 332 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 333 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 334 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 335 case PPCISD::MFCR: return "PPCISD::MFCR"; 336 case PPCISD::VCMP: return "PPCISD::VCMP"; 337 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 338 case PPCISD::LBRX: return "PPCISD::LBRX"; 339 case PPCISD::STBRX: return "PPCISD::STBRX"; 340 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 341 } 342} 343 344//===----------------------------------------------------------------------===// 345// Node matching predicates, for use by the tblgen matching code. 346//===----------------------------------------------------------------------===// 347 348/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 349static bool isFloatingPointZero(SDOperand Op) { 350 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 351 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 352 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 353 // Maybe this has already been legalized into the constant pool? 354 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 355 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 356 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 357 } 358 return false; 359} 360 361/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 362/// true if Op is undef or if it matches the specified value. 363static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 364 return Op.getOpcode() == ISD::UNDEF || 365 cast<ConstantSDNode>(Op)->getValue() == Val; 366} 367 368/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 369/// VPKUHUM instruction. 370bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 371 if (!isUnary) { 372 for (unsigned i = 0; i != 16; ++i) 373 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 374 return false; 375 } else { 376 for (unsigned i = 0; i != 8; ++i) 377 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 378 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 379 return false; 380 } 381 return true; 382} 383 384/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 385/// VPKUWUM instruction. 386bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 387 if (!isUnary) { 388 for (unsigned i = 0; i != 16; i += 2) 389 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 390 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 391 return false; 392 } else { 393 for (unsigned i = 0; i != 8; i += 2) 394 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 395 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 396 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 397 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 398 return false; 399 } 400 return true; 401} 402 403/// isVMerge - Common function, used to match vmrg* shuffles. 404/// 405static bool isVMerge(SDNode *N, unsigned UnitSize, 406 unsigned LHSStart, unsigned RHSStart) { 407 assert(N->getOpcode() == ISD::BUILD_VECTOR && 408 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 409 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 410 "Unsupported merge size!"); 411 412 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 413 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 414 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 415 LHSStart+j+i*UnitSize) || 416 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 417 RHSStart+j+i*UnitSize)) 418 return false; 419 } 420 return true; 421} 422 423/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 424/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 425bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 426 if (!isUnary) 427 return isVMerge(N, UnitSize, 8, 24); 428 return isVMerge(N, UnitSize, 8, 8); 429} 430 431/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 432/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 433bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 434 if (!isUnary) 435 return isVMerge(N, UnitSize, 0, 16); 436 return isVMerge(N, UnitSize, 0, 0); 437} 438 439 440/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 441/// amount, otherwise return -1. 442int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 443 assert(N->getOpcode() == ISD::BUILD_VECTOR && 444 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 445 // Find the first non-undef value in the shuffle mask. 446 unsigned i; 447 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 448 /*search*/; 449 450 if (i == 16) return -1; // all undef. 451 452 // Otherwise, check to see if the rest of the elements are consequtively 453 // numbered from this value. 454 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 455 if (ShiftAmt < i) return -1; 456 ShiftAmt -= i; 457 458 if (!isUnary) { 459 // Check the rest of the elements to see if they are consequtive. 460 for (++i; i != 16; ++i) 461 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 462 return -1; 463 } else { 464 // Check the rest of the elements to see if they are consequtive. 465 for (++i; i != 16; ++i) 466 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 467 return -1; 468 } 469 470 return ShiftAmt; 471} 472 473/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 474/// specifies a splat of a single element that is suitable for input to 475/// VSPLTB/VSPLTH/VSPLTW. 476bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 477 assert(N->getOpcode() == ISD::BUILD_VECTOR && 478 N->getNumOperands() == 16 && 479 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 480 481 // This is a splat operation if each element of the permute is the same, and 482 // if the value doesn't reference the second vector. 483 unsigned ElementBase = 0; 484 SDOperand Elt = N->getOperand(0); 485 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 486 ElementBase = EltV->getValue(); 487 else 488 return false; // FIXME: Handle UNDEF elements too! 489 490 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 491 return false; 492 493 // Check that they are consequtive. 494 for (unsigned i = 1; i != EltSize; ++i) { 495 if (!isa<ConstantSDNode>(N->getOperand(i)) || 496 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 497 return false; 498 } 499 500 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 501 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 502 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 503 assert(isa<ConstantSDNode>(N->getOperand(i)) && 504 "Invalid VECTOR_SHUFFLE mask!"); 505 for (unsigned j = 0; j != EltSize; ++j) 506 if (N->getOperand(i+j) != N->getOperand(j)) 507 return false; 508 } 509 510 return true; 511} 512 513/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 514/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 515unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 516 assert(isSplatShuffleMask(N, EltSize)); 517 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 518} 519 520/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 521/// by using a vspltis[bhw] instruction of the specified element size, return 522/// the constant being splatted. The ByteSize field indicates the number of 523/// bytes of each element [124] -> [bhw]. 524SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 525 SDOperand OpVal(0, 0); 526 527 // If ByteSize of the splat is bigger than the element size of the 528 // build_vector, then we have a case where we are checking for a splat where 529 // multiple elements of the buildvector are folded together into a single 530 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 531 unsigned EltSize = 16/N->getNumOperands(); 532 if (EltSize < ByteSize) { 533 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 534 SDOperand UniquedVals[4]; 535 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 536 537 // See if all of the elements in the buildvector agree across. 538 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 539 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 540 // If the element isn't a constant, bail fully out. 541 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 542 543 544 if (UniquedVals[i&(Multiple-1)].Val == 0) 545 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 546 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 547 return SDOperand(); // no match. 548 } 549 550 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 551 // either constant or undef values that are identical for each chunk. See 552 // if these chunks can form into a larger vspltis*. 553 554 // Check to see if all of the leading entries are either 0 or -1. If 555 // neither, then this won't fit into the immediate field. 556 bool LeadingZero = true; 557 bool LeadingOnes = true; 558 for (unsigned i = 0; i != Multiple-1; ++i) { 559 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 560 561 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 562 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 563 } 564 // Finally, check the least significant entry. 565 if (LeadingZero) { 566 if (UniquedVals[Multiple-1].Val == 0) 567 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 568 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 569 if (Val < 16) 570 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 571 } 572 if (LeadingOnes) { 573 if (UniquedVals[Multiple-1].Val == 0) 574 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 575 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 576 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 577 return DAG.getTargetConstant(Val, MVT::i32); 578 } 579 580 return SDOperand(); 581 } 582 583 // Check to see if this buildvec has a single non-undef value in its elements. 584 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 585 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 586 if (OpVal.Val == 0) 587 OpVal = N->getOperand(i); 588 else if (OpVal != N->getOperand(i)) 589 return SDOperand(); 590 } 591 592 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 593 594 unsigned ValSizeInBytes = 0; 595 uint64_t Value = 0; 596 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 597 Value = CN->getValue(); 598 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 599 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 600 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 601 Value = FloatToBits(CN->getValue()); 602 ValSizeInBytes = 4; 603 } 604 605 // If the splat value is larger than the element value, then we can never do 606 // this splat. The only case that we could fit the replicated bits into our 607 // immediate field for would be zero, and we prefer to use vxor for it. 608 if (ValSizeInBytes < ByteSize) return SDOperand(); 609 610 // If the element value is larger than the splat value, cut it in half and 611 // check to see if the two halves are equal. Continue doing this until we 612 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 613 while (ValSizeInBytes > ByteSize) { 614 ValSizeInBytes >>= 1; 615 616 // If the top half equals the bottom half, we're still ok. 617 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 618 (Value & ((1 << (8*ValSizeInBytes))-1))) 619 return SDOperand(); 620 } 621 622 // Properly sign extend the value. 623 int ShAmt = (4-ByteSize)*8; 624 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 625 626 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 627 if (MaskVal == 0) return SDOperand(); 628 629 // Finally, if this value fits in a 5 bit sext field, return it 630 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 631 return DAG.getTargetConstant(MaskVal, MVT::i32); 632 return SDOperand(); 633} 634 635//===----------------------------------------------------------------------===// 636// Addressing Mode Selection 637//===----------------------------------------------------------------------===// 638 639/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 640/// or 64-bit immediate, and if the value can be accurately represented as a 641/// sign extension from a 16-bit value. If so, this returns true and the 642/// immediate. 643static bool isIntS16Immediate(SDNode *N, short &Imm) { 644 if (N->getOpcode() != ISD::Constant) 645 return false; 646 647 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 648 if (N->getValueType(0) == MVT::i32) 649 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 650 else 651 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 652} 653static bool isIntS16Immediate(SDOperand Op, short &Imm) { 654 return isIntS16Immediate(Op.Val, Imm); 655} 656 657 658/// SelectAddressRegReg - Given the specified addressed, check to see if it 659/// can be represented as an indexed [r+r] operation. Returns false if it 660/// can be more efficiently represented with [r+imm]. 661bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, 662 SDOperand &Index, 663 SelectionDAG &DAG) { 664 short imm = 0; 665 if (N.getOpcode() == ISD::ADD) { 666 if (isIntS16Immediate(N.getOperand(1), imm)) 667 return false; // r+i 668 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 669 return false; // r+i 670 671 Base = N.getOperand(0); 672 Index = N.getOperand(1); 673 return true; 674 } else if (N.getOpcode() == ISD::OR) { 675 if (isIntS16Immediate(N.getOperand(1), imm)) 676 return false; // r+i can fold it if we can. 677 678 // If this is an or of disjoint bitfields, we can codegen this as an add 679 // (for better address arithmetic) if the LHS and RHS of the OR are provably 680 // disjoint. 681 uint64_t LHSKnownZero, LHSKnownOne; 682 uint64_t RHSKnownZero, RHSKnownOne; 683 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 684 685 if (LHSKnownZero) { 686 ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); 687 // If all of the bits are known zero on the LHS or RHS, the add won't 688 // carry. 689 if ((LHSKnownZero | RHSKnownZero) == ~0U) { 690 Base = N.getOperand(0); 691 Index = N.getOperand(1); 692 return true; 693 } 694 } 695 } 696 697 return false; 698} 699 700/// Returns true if the address N can be represented by a base register plus 701/// a signed 16-bit displacement [r+imm], and if it is not better 702/// represented as reg+reg. 703bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, 704 SDOperand &Base, SelectionDAG &DAG){ 705 // If this can be more profitably realized as r+r, fail. 706 if (SelectAddressRegReg(N, Disp, Base, DAG)) 707 return false; 708 709 if (N.getOpcode() == ISD::ADD) { 710 short imm = 0; 711 if (isIntS16Immediate(N.getOperand(1), imm)) { 712 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 713 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 714 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 715 } else { 716 Base = N.getOperand(0); 717 } 718 return true; // [r+i] 719 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 720 // Match LOAD (ADD (X, Lo(G))). 721 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 722 && "Cannot handle constant offsets yet!"); 723 Disp = N.getOperand(1).getOperand(0); // The global address. 724 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 725 Disp.getOpcode() == ISD::TargetConstantPool || 726 Disp.getOpcode() == ISD::TargetJumpTable); 727 Base = N.getOperand(0); 728 return true; // [&g+r] 729 } 730 } else if (N.getOpcode() == ISD::OR) { 731 short imm = 0; 732 if (isIntS16Immediate(N.getOperand(1), imm)) { 733 // If this is an or of disjoint bitfields, we can codegen this as an add 734 // (for better address arithmetic) if the LHS and RHS of the OR are 735 // provably disjoint. 736 uint64_t LHSKnownZero, LHSKnownOne; 737 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 738 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 739 // If all of the bits are known zero on the LHS or RHS, the add won't 740 // carry. 741 Base = N.getOperand(0); 742 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 743 return true; 744 } 745 } 746 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 747 // Loading from a constant address. 748 749 // If this address fits entirely in a 16-bit sext immediate field, codegen 750 // this as "d, 0" 751 short Imm; 752 if (isIntS16Immediate(CN, Imm)) { 753 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 754 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 755 return true; 756 } 757 758 // Handle 32-bit sext immediates with LIS + addr mode. 759 if (CN->getValueType(0) == MVT::i32 || 760 (int64_t)CN->getValue() == (int)CN->getValue()) { 761 int Addr = (int)CN->getValue(); 762 763 // Otherwise, break this down into an LIS + disp. 764 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 765 766 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 767 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 768 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 769 return true; 770 } 771 } 772 773 Disp = DAG.getTargetConstant(0, getPointerTy()); 774 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 775 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 776 else 777 Base = N; 778 return true; // [r+0] 779} 780 781/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 782/// represented as an indexed [r+r] operation. 783bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, 784 SDOperand &Index, 785 SelectionDAG &DAG) { 786 // Check to see if we can easily represent this as an [r+r] address. This 787 // will fail if it thinks that the address is more profitably represented as 788 // reg+imm, e.g. where imm = 0. 789 if (SelectAddressRegReg(N, Base, Index, DAG)) 790 return true; 791 792 // If the operand is an addition, always emit this as [r+r], since this is 793 // better (for code size, and execution, as the memop does the add for free) 794 // than emitting an explicit add. 795 if (N.getOpcode() == ISD::ADD) { 796 Base = N.getOperand(0); 797 Index = N.getOperand(1); 798 return true; 799 } 800 801 // Otherwise, do it the hard way, using R0 as the base register. 802 Base = DAG.getRegister(PPC::R0, N.getValueType()); 803 Index = N; 804 return true; 805} 806 807/// SelectAddressRegImmShift - Returns true if the address N can be 808/// represented by a base register plus a signed 14-bit displacement 809/// [r+imm*4]. Suitable for use by STD and friends. 810bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, 811 SDOperand &Base, 812 SelectionDAG &DAG) { 813 // If this can be more profitably realized as r+r, fail. 814 if (SelectAddressRegReg(N, Disp, Base, DAG)) 815 return false; 816 817 if (N.getOpcode() == ISD::ADD) { 818 short imm = 0; 819 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 820 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 821 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 822 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 823 } else { 824 Base = N.getOperand(0); 825 } 826 return true; // [r+i] 827 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 828 // Match LOAD (ADD (X, Lo(G))). 829 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 830 && "Cannot handle constant offsets yet!"); 831 Disp = N.getOperand(1).getOperand(0); // The global address. 832 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 833 Disp.getOpcode() == ISD::TargetConstantPool || 834 Disp.getOpcode() == ISD::TargetJumpTable); 835 Base = N.getOperand(0); 836 return true; // [&g+r] 837 } 838 } else if (N.getOpcode() == ISD::OR) { 839 short imm = 0; 840 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 841 // If this is an or of disjoint bitfields, we can codegen this as an add 842 // (for better address arithmetic) if the LHS and RHS of the OR are 843 // provably disjoint. 844 uint64_t LHSKnownZero, LHSKnownOne; 845 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 846 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 847 // If all of the bits are known zero on the LHS or RHS, the add won't 848 // carry. 849 Base = N.getOperand(0); 850 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 851 return true; 852 } 853 } 854 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 855 // Loading from a constant address. Verify low two bits are clear. 856 if ((CN->getValue() & 3) == 0) { 857 // If this address fits entirely in a 14-bit sext immediate field, codegen 858 // this as "d, 0" 859 short Imm; 860 if (isIntS16Immediate(CN, Imm)) { 861 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 862 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 863 return true; 864 } 865 866 // Fold the low-part of 32-bit absolute addresses into addr mode. 867 if (CN->getValueType(0) == MVT::i32 || 868 (int64_t)CN->getValue() == (int)CN->getValue()) { 869 int Addr = (int)CN->getValue(); 870 871 // Otherwise, break this down into an LIS + disp. 872 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 873 874 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 875 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 876 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 877 return true; 878 } 879 } 880 } 881 882 Disp = DAG.getTargetConstant(0, getPointerTy()); 883 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 884 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 885 else 886 Base = N; 887 return true; // [r+0] 888} 889 890 891/// getPreIndexedAddressParts - returns true by value, base pointer and 892/// offset pointer and addressing mode by reference if the node's address 893/// can be legally represented as pre-indexed load / store address. 894bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 895 SDOperand &Offset, 896 ISD::MemIndexedMode &AM, 897 SelectionDAG &DAG) { 898 // Disabled by default for now. 899 if (!EnablePPCPreinc) return false; 900 901 SDOperand Ptr; 902 MVT::ValueType VT; 903 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 904 Ptr = LD->getBasePtr(); 905 VT = LD->getLoadedVT(); 906 907 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 908 ST = ST; 909 Ptr = ST->getBasePtr(); 910 VT = ST->getStoredVT(); 911 } else 912 return false; 913 914 // PowerPC doesn't have preinc load/store instructions for vectors. 915 if (MVT::isVector(VT)) 916 return false; 917 918 // TODO: Check reg+reg first. 919 920 // LDU/STU use reg+imm*4, others use reg+imm. 921 if (VT != MVT::i64) { 922 // reg + imm 923 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 924 return false; 925 } else { 926 // reg + imm * 4. 927 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 928 return false; 929 } 930 931 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 932 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 933 // sext i32 to i64 when addr mode is r+i. 934 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 && 935 LD->getExtensionType() == ISD::SEXTLOAD && 936 isa<ConstantSDNode>(Offset)) 937 return false; 938 } 939 940 AM = ISD::PRE_INC; 941 return true; 942} 943 944//===----------------------------------------------------------------------===// 945// LowerOperation implementation 946//===----------------------------------------------------------------------===// 947 948static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 949 MVT::ValueType PtrVT = Op.getValueType(); 950 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 951 Constant *C = CP->getConstVal(); 952 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 953 SDOperand Zero = DAG.getConstant(0, PtrVT); 954 955 const TargetMachine &TM = DAG.getTarget(); 956 957 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 958 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 959 960 // If this is a non-darwin platform, we don't support non-static relo models 961 // yet. 962 if (TM.getRelocationModel() == Reloc::Static || 963 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 964 // Generate non-pic code that has direct accesses to the constant pool. 965 // The address of the global is just (hi(&g)+lo(&g)). 966 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 967 } 968 969 if (TM.getRelocationModel() == Reloc::PIC_) { 970 // With PIC, the first instruction is actually "GR+hi(&G)". 971 Hi = DAG.getNode(ISD::ADD, PtrVT, 972 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 973 } 974 975 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 976 return Lo; 977} 978 979static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 980 MVT::ValueType PtrVT = Op.getValueType(); 981 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 982 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 983 SDOperand Zero = DAG.getConstant(0, PtrVT); 984 985 const TargetMachine &TM = DAG.getTarget(); 986 987 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 988 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 989 990 // If this is a non-darwin platform, we don't support non-static relo models 991 // yet. 992 if (TM.getRelocationModel() == Reloc::Static || 993 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 994 // Generate non-pic code that has direct accesses to the constant pool. 995 // The address of the global is just (hi(&g)+lo(&g)). 996 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 997 } 998 999 if (TM.getRelocationModel() == Reloc::PIC_) { 1000 // With PIC, the first instruction is actually "GR+hi(&G)". 1001 Hi = DAG.getNode(ISD::ADD, PtrVT, 1002 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1003 } 1004 1005 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1006 return Lo; 1007} 1008 1009static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 1010 MVT::ValueType PtrVT = Op.getValueType(); 1011 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1012 GlobalValue *GV = GSDN->getGlobal(); 1013 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1014 SDOperand Zero = DAG.getConstant(0, PtrVT); 1015 1016 const TargetMachine &TM = DAG.getTarget(); 1017 1018 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 1019 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1020 1021 // If this is a non-darwin platform, we don't support non-static relo models 1022 // yet. 1023 if (TM.getRelocationModel() == Reloc::Static || 1024 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1025 // Generate non-pic code that has direct accesses to globals. 1026 // The address of the global is just (hi(&g)+lo(&g)). 1027 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1028 } 1029 1030 if (TM.getRelocationModel() == Reloc::PIC_) { 1031 // With PIC, the first instruction is actually "GR+hi(&G)". 1032 Hi = DAG.getNode(ISD::ADD, PtrVT, 1033 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1034 } 1035 1036 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1037 1038 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1039 return Lo; 1040 1041 // If the global is weak or external, we have to go through the lazy 1042 // resolution stub. 1043 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1044} 1045 1046static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 1047 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1048 1049 // If we're comparing for equality to zero, expose the fact that this is 1050 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1051 // fold the new nodes. 1052 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1053 if (C->isNullValue() && CC == ISD::SETEQ) { 1054 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1055 SDOperand Zext = Op.getOperand(0); 1056 if (VT < MVT::i32) { 1057 VT = MVT::i32; 1058 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1059 } 1060 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1061 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1062 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1063 DAG.getConstant(Log2b, MVT::i32)); 1064 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1065 } 1066 // Leave comparisons against 0 and -1 alone for now, since they're usually 1067 // optimized. FIXME: revisit this when we can custom lower all setcc 1068 // optimizations. 1069 if (C->isAllOnesValue() || C->isNullValue()) 1070 return SDOperand(); 1071 } 1072 1073 // If we have an integer seteq/setne, turn it into a compare against zero 1074 // by xor'ing the rhs with the lhs, which is faster than setting a 1075 // condition register, reading it back out, and masking the correct bit. The 1076 // normal approach here uses sub to do this instead of xor. Using xor exposes 1077 // the result to other bit-twiddling opportunities. 1078 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1079 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1080 MVT::ValueType VT = Op.getValueType(); 1081 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1082 Op.getOperand(1)); 1083 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1084 } 1085 return SDOperand(); 1086} 1087 1088static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 1089 unsigned VarArgsFrameIndex) { 1090 // vastart just stores the address of the VarArgsFrameIndex slot into the 1091 // memory location argument. 1092 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1093 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1094 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1095 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 1096 SV->getOffset()); 1097} 1098 1099/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1100/// depending on which subtarget is selected. 1101static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1102 if (Subtarget.isMachoABI()) { 1103 static const unsigned FPR[] = { 1104 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1105 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1106 }; 1107 return FPR; 1108 } 1109 1110 1111 static const unsigned FPR[] = { 1112 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1113 PPC::F8, PPC::F9, PPC::F10 1114 }; 1115 return FPR; 1116} 1117 1118static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 1119 int &VarArgsFrameIndex, 1120 const PPCSubtarget &Subtarget) { 1121 // TODO: add description of PPC stack frame format, or at least some docs. 1122 // 1123 MachineFunction &MF = DAG.getMachineFunction(); 1124 MachineFrameInfo *MFI = MF.getFrameInfo(); 1125 SSARegMap *RegMap = MF.getSSARegMap(); 1126 SmallVector<SDOperand, 8> ArgValues; 1127 SDOperand Root = Op.getOperand(0); 1128 1129 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1130 bool isPPC64 = PtrVT == MVT::i64; 1131 bool isMachoABI = Subtarget.isMachoABI(); 1132 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1133 1134 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1135 1136 static const unsigned GPR_32[] = { // 32-bit registers. 1137 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1138 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1139 }; 1140 static const unsigned GPR_64[] = { // 64-bit registers. 1141 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1142 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1143 }; 1144 1145 static const unsigned *FPR = GetFPR(Subtarget); 1146 1147 static const unsigned VR[] = { 1148 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1149 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1150 }; 1151 1152 const unsigned Num_GPR_Regs = sizeof(GPR_32)/sizeof(GPR_32[0]); 1153 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 10; 1154 const unsigned Num_VR_Regs = sizeof( VR)/sizeof( VR[0]); 1155 1156 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1157 1158 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1159 1160 // Add DAG nodes to load the arguments or copy them out of registers. On 1161 // entry to a function on PPC, the arguments start after the linkage area, 1162 // although the first ones are often in registers. 1163 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1164 SDOperand ArgVal; 1165 bool needsLoad = false; 1166 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 1167 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 1168 unsigned ArgSize = ObjSize; 1169 1170 unsigned CurArgOffset = ArgOffset; 1171 switch (ObjectVT) { 1172 default: assert(0 && "Unhandled argument type!"); 1173 case MVT::i32: 1174 if (GPR_idx != Num_GPR_Regs) { 1175 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1176 MF.addLiveIn(GPR[GPR_idx], VReg); 1177 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1178 ++GPR_idx; 1179 } else { 1180 needsLoad = true; 1181 ArgSize = PtrByteSize; 1182 } 1183 // All int arguments reserve stack space in Macho ABI. 1184 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1185 break; 1186 1187 case MVT::i64: // PPC64 1188 if (GPR_idx != Num_GPR_Regs) { 1189 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1190 MF.addLiveIn(GPR[GPR_idx], VReg); 1191 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1192 ++GPR_idx; 1193 } else { 1194 needsLoad = true; 1195 } 1196 // All int arguments reserve stack space in Macho ABI. 1197 if (isMachoABI || needsLoad) ArgOffset += 8; 1198 break; 1199 1200 case MVT::f32: 1201 case MVT::f64: 1202 // Every 4 bytes of argument space consumes one of the GPRs available for 1203 // argument passing. 1204 if (GPR_idx != Num_GPR_Regs) { 1205 ++GPR_idx; 1206 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1207 ++GPR_idx; 1208 } 1209 if (FPR_idx != Num_FPR_Regs) { 1210 unsigned VReg; 1211 if (ObjectVT == MVT::f32) 1212 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 1213 else 1214 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1215 MF.addLiveIn(FPR[FPR_idx], VReg); 1216 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1217 ++FPR_idx; 1218 } else { 1219 needsLoad = true; 1220 } 1221 1222 // All FP arguments reserve stack space in Macho ABI. 1223 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1224 break; 1225 case MVT::v4f32: 1226 case MVT::v4i32: 1227 case MVT::v8i16: 1228 case MVT::v16i8: 1229 // Note that vector arguments in registers don't reserve stack space. 1230 if (VR_idx != Num_VR_Regs) { 1231 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); 1232 MF.addLiveIn(VR[VR_idx], VReg); 1233 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1234 ++VR_idx; 1235 } else { 1236 // This should be simple, but requires getting 16-byte aligned stack 1237 // values. 1238 assert(0 && "Loading VR argument not implemented yet!"); 1239 needsLoad = true; 1240 } 1241 break; 1242 } 1243 1244 // We need to load the argument to a virtual register if we determined above 1245 // that we ran out of physical registers of the appropriate type 1246 if (needsLoad) { 1247 // If the argument is actually used, emit a load from the right stack 1248 // slot. 1249 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 1250 int FI = MFI->CreateFixedObject(ObjSize, 1251 CurArgOffset + (ArgSize - ObjSize)); 1252 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1253 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1254 } else { 1255 // Don't emit a dead load. 1256 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); 1257 } 1258 } 1259 1260 ArgValues.push_back(ArgVal); 1261 } 1262 1263 // If the function takes variable number of arguments, make a frame index for 1264 // the start of the first vararg value... for expansion of llvm.va_start. 1265 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1266 if (isVarArg) { 1267 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1268 ArgOffset); 1269 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1270 // If this function is vararg, store any remaining integer argument regs 1271 // to their spots on the stack so that they may be loaded by deferencing the 1272 // result of va_next. 1273 SmallVector<SDOperand, 8> MemOps; 1274 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1275 unsigned VReg; 1276 if (isPPC64) 1277 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1278 else 1279 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1280 1281 MF.addLiveIn(GPR[GPR_idx], VReg); 1282 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1283 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1284 MemOps.push_back(Store); 1285 // Increment the address by four for the next argument to store 1286 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1287 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1288 } 1289 if (!MemOps.empty()) 1290 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1291 } 1292 1293 ArgValues.push_back(Root); 1294 1295 // Return the new list of results. 1296 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1297 Op.Val->value_end()); 1298 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1299} 1300 1301/// isCallCompatibleAddress - Return the immediate to use if the specified 1302/// 32-bit value is representable in the immediate field of a BxA instruction. 1303static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 1304 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1305 if (!C) return 0; 1306 1307 int Addr = C->getValue(); 1308 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1309 (Addr << 6 >> 6) != Addr) 1310 return 0; // Top 6 bits have to be sext of immediate. 1311 1312 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val; 1313} 1314 1315 1316static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, 1317 const PPCSubtarget &Subtarget) { 1318 SDOperand Chain = Op.getOperand(0); 1319 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1320 SDOperand Callee = Op.getOperand(4); 1321 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1322 1323 bool isMachoABI = Subtarget.isMachoABI(); 1324 1325 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1326 bool isPPC64 = PtrVT == MVT::i64; 1327 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1328 1329 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1330 // SelectExpr to use to put the arguments in the appropriate registers. 1331 std::vector<SDOperand> args_to_use; 1332 1333 // Count how many bytes are to be pushed on the stack, including the linkage 1334 // area, and parameter passing area. We start with 24/48 bytes, which is 1335 // prereserved space for [SP][CR][LR][3 x unused]. 1336 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1337 1338 // Add up all the space actually used. 1339 for (unsigned i = 0; i != NumOps; ++i) { 1340 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 1341 ArgSize = std::max(ArgSize, PtrByteSize); 1342 NumBytes += ArgSize; 1343 } 1344 1345 // The prolog code of the callee may store up to 8 GPR argument registers to 1346 // the stack, allowing va_start to index over them in memory if its varargs. 1347 // Because we cannot tell if this is needed on the caller side, we have to 1348 // conservatively assume that it is needed. As such, make sure we have at 1349 // least enough stack space for the caller to store the 8 GPRs. 1350 NumBytes = std::max(NumBytes, 1351 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1352 1353 // Adjust the stack pointer for the new arguments... 1354 // These operations are automatically eliminated by the prolog/epilog pass 1355 Chain = DAG.getCALLSEQ_START(Chain, 1356 DAG.getConstant(NumBytes, PtrVT)); 1357 1358 // Set up a copy of the stack pointer for use loading and storing any 1359 // arguments that may not fit in the registers available for argument 1360 // passing. 1361 SDOperand StackPtr; 1362 if (isPPC64) 1363 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 1364 else 1365 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1366 1367 // Figure out which arguments are going to go in registers, and which in 1368 // memory. Also, if this is a vararg function, floating point operations 1369 // must be stored to our stack, and loaded into integer regs as well, if 1370 // any integer regs are available for argument passing. 1371 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1372 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1373 1374 static const unsigned GPR_32[] = { // 32-bit registers. 1375 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1376 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1377 }; 1378 static const unsigned GPR_64[] = { // 64-bit registers. 1379 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1380 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1381 }; 1382 static const unsigned *FPR = GetFPR(Subtarget); 1383 1384 static const unsigned VR[] = { 1385 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1386 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1387 }; 1388 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]); 1389 const unsigned NumFPRs = isMachoABI ? 13 : 10; 1390 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]); 1391 1392 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1393 1394 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1395 SmallVector<SDOperand, 8> MemOpChains; 1396 for (unsigned i = 0; i != NumOps; ++i) { 1397 bool inMem = false; 1398 SDOperand Arg = Op.getOperand(5+2*i); 1399 1400 // PtrOff will be used to store the current argument to the stack if a 1401 // register cannot be found for it. 1402 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1403 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1404 1405 // On PPC64, promote integers to 64-bit values. 1406 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1407 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1408 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1409 1410 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1411 } 1412 1413 switch (Arg.getValueType()) { 1414 default: assert(0 && "Unexpected ValueType for argument!"); 1415 case MVT::i32: 1416 case MVT::i64: 1417 if (GPR_idx != NumGPRs) { 1418 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1419 } else { 1420 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1421 inMem = true; 1422 } 1423 if (inMem || isMachoABI) ArgOffset += PtrByteSize; 1424 break; 1425 case MVT::f32: 1426 case MVT::f64: 1427 if (isVarArg) { 1428 // Float varargs need to be promoted to double. 1429 if (Arg.getValueType() == MVT::f32) 1430 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); 1431 } 1432 1433 if (FPR_idx != NumFPRs) { 1434 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1435 1436 if (isVarArg) { 1437 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1438 MemOpChains.push_back(Store); 1439 1440 // Float varargs are always shadowed in available integer registers 1441 if (GPR_idx != NumGPRs) { 1442 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1443 MemOpChains.push_back(Load.getValue(1)); 1444 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1445 Load)); 1446 } 1447 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 1448 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1449 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1450 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1451 MemOpChains.push_back(Load.getValue(1)); 1452 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1453 Load)); 1454 } 1455 } else { 1456 // If we have any FPRs remaining, we may also have GPRs remaining. 1457 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1458 // GPRs. 1459 if (isMachoABI) { 1460 if (GPR_idx != NumGPRs) 1461 ++GPR_idx; 1462 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 1463 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 1464 ++GPR_idx; 1465 } 1466 } 1467 } else { 1468 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1469 inMem = true; 1470 } 1471 if (inMem || isMachoABI) { 1472 if (isPPC64) 1473 ArgOffset += 8; 1474 else 1475 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1476 } 1477 break; 1478 case MVT::v4f32: 1479 case MVT::v4i32: 1480 case MVT::v8i16: 1481 case MVT::v16i8: 1482 assert(!isVarArg && "Don't support passing vectors to varargs yet!"); 1483 assert(VR_idx != NumVRs && 1484 "Don't support passing more than 12 vector args yet!"); 1485 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 1486 break; 1487 } 1488 } 1489 if (!MemOpChains.empty()) 1490 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1491 &MemOpChains[0], MemOpChains.size()); 1492 1493 // Build a sequence of copy-to-reg nodes chained together with token chain 1494 // and flag operands which copy the outgoing args into the appropriate regs. 1495 SDOperand InFlag; 1496 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1497 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1498 InFlag); 1499 InFlag = Chain.getValue(1); 1500 } 1501 1502 // With the ELF ABI, set CR6 to true if this is a vararg call. 1503 if (isVarArg && !isMachoABI) { 1504 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0); 1505 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag); 1506 InFlag = Chain.getValue(1); 1507 } 1508 1509 std::vector<MVT::ValueType> NodeTys; 1510 NodeTys.push_back(MVT::Other); // Returns a chain 1511 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1512 1513 SmallVector<SDOperand, 8> Ops; 1514 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 1515 1516 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1517 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1518 // node so that legalize doesn't hack it. 1519 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1520 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 1521 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1522 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 1523 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 1524 // If this is an absolute destination address, use the munged value. 1525 Callee = SDOperand(Dest, 0); 1526 else { 1527 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 1528 // to do the call, we can't use PPCISD::CALL. 1529 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 1530 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 1531 InFlag = Chain.getValue(1); 1532 1533 // Copy the callee address into R12 on darwin. 1534 if (isMachoABI) { 1535 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); 1536 InFlag = Chain.getValue(1); 1537 } 1538 1539 NodeTys.clear(); 1540 NodeTys.push_back(MVT::Other); 1541 NodeTys.push_back(MVT::Flag); 1542 Ops.push_back(Chain); 1543 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 1544 Callee.Val = 0; 1545 } 1546 1547 // If this is a direct call, pass the chain and the callee. 1548 if (Callee.Val) { 1549 Ops.push_back(Chain); 1550 Ops.push_back(Callee); 1551 } 1552 1553 // Add argument registers to the end of the list so that they are known live 1554 // into the call. 1555 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1556 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1557 RegsToPass[i].second.getValueType())); 1558 1559 if (InFlag.Val) 1560 Ops.push_back(InFlag); 1561 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 1562 InFlag = Chain.getValue(1); 1563 1564 SDOperand ResultVals[3]; 1565 unsigned NumResults = 0; 1566 NodeTys.clear(); 1567 1568 // If the call has results, copy the values out of the ret val registers. 1569 switch (Op.Val->getValueType(0)) { 1570 default: assert(0 && "Unexpected ret value!"); 1571 case MVT::Other: break; 1572 case MVT::i32: 1573 if (Op.Val->getValueType(1) == MVT::i32) { 1574 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1); 1575 ResultVals[0] = Chain.getValue(0); 1576 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, 1577 Chain.getValue(2)).getValue(1); 1578 ResultVals[1] = Chain.getValue(0); 1579 NumResults = 2; 1580 NodeTys.push_back(MVT::i32); 1581 } else { 1582 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1583 ResultVals[0] = Chain.getValue(0); 1584 NumResults = 1; 1585 } 1586 NodeTys.push_back(MVT::i32); 1587 break; 1588 case MVT::i64: 1589 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 1590 ResultVals[0] = Chain.getValue(0); 1591 NumResults = 1; 1592 NodeTys.push_back(MVT::i64); 1593 break; 1594 case MVT::f32: 1595 case MVT::f64: 1596 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 1597 InFlag).getValue(1); 1598 ResultVals[0] = Chain.getValue(0); 1599 NumResults = 1; 1600 NodeTys.push_back(Op.Val->getValueType(0)); 1601 break; 1602 case MVT::v4f32: 1603 case MVT::v4i32: 1604 case MVT::v8i16: 1605 case MVT::v16i8: 1606 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 1607 InFlag).getValue(1); 1608 ResultVals[0] = Chain.getValue(0); 1609 NumResults = 1; 1610 NodeTys.push_back(Op.Val->getValueType(0)); 1611 break; 1612 } 1613 1614 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 1615 DAG.getConstant(NumBytes, PtrVT)); 1616 NodeTys.push_back(MVT::Other); 1617 1618 // If the function returns void, just return the chain. 1619 if (NumResults == 0) 1620 return Chain; 1621 1622 // Otherwise, merge everything together with a MERGE_VALUES node. 1623 ResultVals[NumResults++] = Chain; 1624 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1625 ResultVals, NumResults); 1626 return Res.getValue(Op.ResNo); 1627} 1628 1629static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 1630 SDOperand Chain = Op.getOperand(0); 1631 switch(Op.getNumOperands()) { 1632 default: 1633 assert(0 && "Do not know how to return this many arguments!"); 1634 abort(); 1635 case 1: 1636 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); 1637 case 3: { 1638 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 1639 unsigned ArgReg; 1640 if (ArgVT == MVT::i32) { 1641 ArgReg = PPC::R3; 1642 } else if (ArgVT == MVT::i64) { 1643 ArgReg = PPC::X3; 1644 } else if (MVT::isVector(ArgVT)) { 1645 ArgReg = PPC::V2; 1646 } else { 1647 assert(MVT::isFloatingPoint(ArgVT)); 1648 ArgReg = PPC::F1; 1649 } 1650 1651 Chain = DAG.getCopyToReg(Chain, ArgReg, Op.getOperand(1), SDOperand()); 1652 1653 // If we haven't noted the R3/F1 are live out, do so now. 1654 if (DAG.getMachineFunction().liveout_empty()) 1655 DAG.getMachineFunction().addLiveOut(ArgReg); 1656 break; 1657 } 1658 case 5: 1659 Chain = DAG.getCopyToReg(Chain, PPC::R3, Op.getOperand(3), SDOperand()); 1660 Chain = DAG.getCopyToReg(Chain, PPC::R4, Op.getOperand(1), 1661 Chain.getValue(1)); 1662 // If we haven't noted the R3+R4 are live out, do so now. 1663 if (DAG.getMachineFunction().liveout_empty()) { 1664 DAG.getMachineFunction().addLiveOut(PPC::R3); 1665 DAG.getMachineFunction().addLiveOut(PPC::R4); 1666 } 1667 break; 1668 } 1669 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Chain.getValue(1)); 1670} 1671 1672static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, 1673 const PPCSubtarget &Subtarget) { 1674 // When we pop the dynamic allocation we need to restore the SP link. 1675 1676 // Get the corect type for pointers. 1677 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1678 1679 // Construct the stack pointer operand. 1680 bool IsPPC64 = Subtarget.isPPC64(); 1681 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 1682 SDOperand StackPtr = DAG.getRegister(SP, PtrVT); 1683 1684 // Get the operands for the STACKRESTORE. 1685 SDOperand Chain = Op.getOperand(0); 1686 SDOperand SaveSP = Op.getOperand(1); 1687 1688 // Load the old link SP. 1689 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 1690 1691 // Restore the stack pointer. 1692 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 1693 1694 // Store the old link SP. 1695 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 1696} 1697 1698static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, 1699 const PPCSubtarget &Subtarget) { 1700 MachineFunction &MF = DAG.getMachineFunction(); 1701 bool IsPPC64 = Subtarget.isPPC64(); 1702 bool isMachoABI = Subtarget.isMachoABI(); 1703 1704 // Get current frame pointer save index. The users of this index will be 1705 // primarily DYNALLOC instructions. 1706 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1707 int FPSI = FI->getFramePointerSaveIndex(); 1708 1709 // If the frame pointer save index hasn't been defined yet. 1710 if (!FPSI) { 1711 // Find out what the fix offset of the frame pointer save area. 1712 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 1713 1714 // Allocate the frame index for frame pointer save area. 1715 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 1716 // Save the result. 1717 FI->setFramePointerSaveIndex(FPSI); 1718 } 1719 1720 // Get the inputs. 1721 SDOperand Chain = Op.getOperand(0); 1722 SDOperand Size = Op.getOperand(1); 1723 1724 // Get the corect type for pointers. 1725 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1726 // Negate the size. 1727 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, 1728 DAG.getConstant(0, PtrVT), Size); 1729 // Construct a node for the frame pointer save index. 1730 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); 1731 // Build a DYNALLOC node. 1732 SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; 1733 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 1734 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 1735} 1736 1737 1738/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 1739/// possible. 1740static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 1741 // Not FP? Not a fsel. 1742 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 1743 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 1744 return SDOperand(); 1745 1746 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1747 1748 // Cannot handle SETEQ/SETNE. 1749 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 1750 1751 MVT::ValueType ResVT = Op.getValueType(); 1752 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 1753 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 1754 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 1755 1756 // If the RHS of the comparison is a 0.0, we don't need to do the 1757 // subtraction at all. 1758 if (isFloatingPointZero(RHS)) 1759 switch (CC) { 1760 default: break; // SETUO etc aren't handled by fsel. 1761 case ISD::SETULT: 1762 case ISD::SETOLT: 1763 case ISD::SETLT: 1764 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 1765 case ISD::SETUGE: 1766 case ISD::SETOGE: 1767 case ISD::SETGE: 1768 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 1769 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 1770 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 1771 case ISD::SETUGT: 1772 case ISD::SETOGT: 1773 case ISD::SETGT: 1774 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 1775 case ISD::SETULE: 1776 case ISD::SETOLE: 1777 case ISD::SETLE: 1778 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 1779 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 1780 return DAG.getNode(PPCISD::FSEL, ResVT, 1781 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 1782 } 1783 1784 SDOperand Cmp; 1785 switch (CC) { 1786 default: break; // SETUO etc aren't handled by fsel. 1787 case ISD::SETULT: 1788 case ISD::SETOLT: 1789 case ISD::SETLT: 1790 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 1791 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1792 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1793 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 1794 case ISD::SETUGE: 1795 case ISD::SETOGE: 1796 case ISD::SETGE: 1797 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 1798 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1799 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1800 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 1801 case ISD::SETUGT: 1802 case ISD::SETOGT: 1803 case ISD::SETGT: 1804 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 1805 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1806 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1807 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 1808 case ISD::SETULE: 1809 case ISD::SETOLE: 1810 case ISD::SETLE: 1811 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 1812 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1813 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1814 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 1815 } 1816 return SDOperand(); 1817} 1818 1819static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 1820 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 1821 SDOperand Src = Op.getOperand(0); 1822 if (Src.getValueType() == MVT::f32) 1823 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 1824 1825 SDOperand Tmp; 1826 switch (Op.getValueType()) { 1827 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 1828 case MVT::i32: 1829 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 1830 break; 1831 case MVT::i64: 1832 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 1833 break; 1834 } 1835 1836 // Convert the FP value to an int value through memory. 1837 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 1838 if (Op.getValueType() == MVT::i32) 1839 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 1840 return Bits; 1841} 1842 1843static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 1844 if (Op.getOperand(0).getValueType() == MVT::i64) { 1845 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 1846 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 1847 if (Op.getValueType() == MVT::f32) 1848 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 1849 return FP; 1850 } 1851 1852 assert(Op.getOperand(0).getValueType() == MVT::i32 && 1853 "Unhandled SINT_TO_FP type in custom expander!"); 1854 // Since we only generate this in 64-bit mode, we can take advantage of 1855 // 64-bit registers. In particular, sign extend the input value into the 1856 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 1857 // then lfd it and fcfid it. 1858 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 1859 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 1860 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1861 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 1862 1863 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 1864 Op.getOperand(0)); 1865 1866 // STD the extended value into the stack slot. 1867 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 1868 DAG.getEntryNode(), Ext64, FIdx, 1869 DAG.getSrcValue(NULL)); 1870 // Load the value as a double. 1871 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 1872 1873 // FCFID it and return it. 1874 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 1875 if (Op.getValueType() == MVT::f32) 1876 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 1877 return FP; 1878} 1879 1880static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 1881 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1882 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 1883 1884 // Expand into a bunch of logical ops. Note that these ops 1885 // depend on the PPC behavior for oversized shift amounts. 1886 SDOperand Lo = Op.getOperand(0); 1887 SDOperand Hi = Op.getOperand(1); 1888 SDOperand Amt = Op.getOperand(2); 1889 1890 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1891 DAG.getConstant(32, MVT::i32), Amt); 1892 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 1893 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 1894 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1895 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1896 DAG.getConstant(-32U, MVT::i32)); 1897 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 1898 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 1899 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 1900 SDOperand OutOps[] = { OutLo, OutHi }; 1901 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1902 OutOps, 2); 1903} 1904 1905static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 1906 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1907 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); 1908 1909 // Otherwise, expand into a bunch of logical ops. Note that these ops 1910 // depend on the PPC behavior for oversized shift amounts. 1911 SDOperand Lo = Op.getOperand(0); 1912 SDOperand Hi = Op.getOperand(1); 1913 SDOperand Amt = Op.getOperand(2); 1914 1915 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1916 DAG.getConstant(32, MVT::i32), Amt); 1917 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 1918 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 1919 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1920 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1921 DAG.getConstant(-32U, MVT::i32)); 1922 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 1923 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 1924 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 1925 SDOperand OutOps[] = { OutLo, OutHi }; 1926 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1927 OutOps, 2); 1928} 1929 1930static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 1931 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1932 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 1933 1934 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 1935 SDOperand Lo = Op.getOperand(0); 1936 SDOperand Hi = Op.getOperand(1); 1937 SDOperand Amt = Op.getOperand(2); 1938 1939 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1940 DAG.getConstant(32, MVT::i32), Amt); 1941 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 1942 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 1943 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1944 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1945 DAG.getConstant(-32U, MVT::i32)); 1946 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 1947 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 1948 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 1949 Tmp4, Tmp6, ISD::SETLE); 1950 SDOperand OutOps[] = { OutLo, OutHi }; 1951 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1952 OutOps, 2); 1953} 1954 1955//===----------------------------------------------------------------------===// 1956// Vector related lowering. 1957// 1958 1959// If this is a vector of constants or undefs, get the bits. A bit in 1960// UndefBits is set if the corresponding element of the vector is an 1961// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 1962// zero. Return true if this is not an array of constants, false if it is. 1963// 1964static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 1965 uint64_t UndefBits[2]) { 1966 // Start with zero'd results. 1967 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 1968 1969 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 1970 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 1971 SDOperand OpVal = BV->getOperand(i); 1972 1973 unsigned PartNo = i >= e/2; // In the upper 128 bits? 1974 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 1975 1976 uint64_t EltBits = 0; 1977 if (OpVal.getOpcode() == ISD::UNDEF) { 1978 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 1979 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 1980 continue; 1981 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 1982 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 1983 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 1984 assert(CN->getValueType(0) == MVT::f32 && 1985 "Only one legal FP vector type!"); 1986 EltBits = FloatToBits(CN->getValue()); 1987 } else { 1988 // Nonconstant element. 1989 return true; 1990 } 1991 1992 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 1993 } 1994 1995 //printf("%llx %llx %llx %llx\n", 1996 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 1997 return false; 1998} 1999 2000// If this is a splat (repetition) of a value across the whole vector, return 2001// the smallest size that splats it. For example, "0x01010101010101..." is a 2002// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2003// SplatSize = 1 byte. 2004static bool isConstantSplat(const uint64_t Bits128[2], 2005 const uint64_t Undef128[2], 2006 unsigned &SplatBits, unsigned &SplatUndef, 2007 unsigned &SplatSize) { 2008 2009 // Don't let undefs prevent splats from matching. See if the top 64-bits are 2010 // the same as the lower 64-bits, ignoring undefs. 2011 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 2012 return false; // Can't be a splat if two pieces don't match. 2013 2014 uint64_t Bits64 = Bits128[0] | Bits128[1]; 2015 uint64_t Undef64 = Undef128[0] & Undef128[1]; 2016 2017 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 2018 // undefs. 2019 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 2020 return false; // Can't be a splat if two pieces don't match. 2021 2022 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 2023 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 2024 2025 // If the top 16-bits are different than the lower 16-bits, ignoring 2026 // undefs, we have an i32 splat. 2027 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 2028 SplatBits = Bits32; 2029 SplatUndef = Undef32; 2030 SplatSize = 4; 2031 return true; 2032 } 2033 2034 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 2035 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 2036 2037 // If the top 8-bits are different than the lower 8-bits, ignoring 2038 // undefs, we have an i16 splat. 2039 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 2040 SplatBits = Bits16; 2041 SplatUndef = Undef16; 2042 SplatSize = 2; 2043 return true; 2044 } 2045 2046 // Otherwise, we have an 8-bit splat. 2047 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 2048 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 2049 SplatSize = 1; 2050 return true; 2051} 2052 2053/// BuildSplatI - Build a canonical splati of Val with an element size of 2054/// SplatSize. Cast the result to VT. 2055static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 2056 SelectionDAG &DAG) { 2057 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 2058 2059 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 2060 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 2061 }; 2062 2063 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 2064 2065 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 2066 if (Val == -1) 2067 SplatSize = 1; 2068 2069 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 2070 2071 // Build a canonical splat for this value. 2072 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT)); 2073 SmallVector<SDOperand, 8> Ops; 2074 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 2075 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 2076 &Ops[0], Ops.size()); 2077 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 2078} 2079 2080/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 2081/// specified intrinsic ID. 2082static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 2083 SelectionDAG &DAG, 2084 MVT::ValueType DestVT = MVT::Other) { 2085 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 2086 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2087 DAG.getConstant(IID, MVT::i32), LHS, RHS); 2088} 2089 2090/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 2091/// specified intrinsic ID. 2092static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 2093 SDOperand Op2, SelectionDAG &DAG, 2094 MVT::ValueType DestVT = MVT::Other) { 2095 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 2096 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2097 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 2098} 2099 2100 2101/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 2102/// amount. The result has the specified value type. 2103static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 2104 MVT::ValueType VT, SelectionDAG &DAG) { 2105 // Force LHS/RHS to be the right type. 2106 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 2107 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 2108 2109 SDOperand Ops[16]; 2110 for (unsigned i = 0; i != 16; ++i) 2111 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 2112 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 2113 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 2114 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 2115} 2116 2117// If this is a case we can't handle, return null and let the default 2118// expansion code take care of it. If we CAN select this case, and if it 2119// selects to a single instruction, return Op. Otherwise, if we can codegen 2120// this case more efficiently than a constant pool load, lower it to the 2121// sequence of ops that should be used. 2122static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2123 // If this is a vector of constants or undefs, get the bits. A bit in 2124 // UndefBits is set if the corresponding element of the vector is an 2125 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2126 // zero. 2127 uint64_t VectorBits[2]; 2128 uint64_t UndefBits[2]; 2129 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 2130 return SDOperand(); // Not a constant vector. 2131 2132 // If this is a splat (repetition) of a value across the whole vector, return 2133 // the smallest size that splats it. For example, "0x01010101010101..." is a 2134 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2135 // SplatSize = 1 byte. 2136 unsigned SplatBits, SplatUndef, SplatSize; 2137 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 2138 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 2139 2140 // First, handle single instruction cases. 2141 2142 // All zeros? 2143 if (SplatBits == 0) { 2144 // Canonicalize all zero vectors to be v4i32. 2145 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 2146 SDOperand Z = DAG.getConstant(0, MVT::i32); 2147 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 2148 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 2149 } 2150 return Op; 2151 } 2152 2153 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 2154 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 2155 if (SextVal >= -16 && SextVal <= 15) 2156 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 2157 2158 2159 // Two instruction sequences. 2160 2161 // If this value is in the range [-32,30] and is even, use: 2162 // tmp = VSPLTI[bhw], result = add tmp, tmp 2163 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 2164 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 2165 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 2166 } 2167 2168 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 2169 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 2170 // for fneg/fabs. 2171 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 2172 // Make -1 and vspltisw -1: 2173 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 2174 2175 // Make the VSLW intrinsic, computing 0x8000_0000. 2176 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 2177 OnesV, DAG); 2178 2179 // xor by OnesV to invert it. 2180 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 2181 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2182 } 2183 2184 // Check to see if this is a wide variety of vsplti*, binop self cases. 2185 unsigned SplatBitSize = SplatSize*8; 2186 static const char SplatCsts[] = { 2187 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 2188 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 2189 }; 2190 2191 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){ 2192 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 2193 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 2194 int i = SplatCsts[idx]; 2195 2196 // Figure out what shift amount will be used by altivec if shifted by i in 2197 // this splat size. 2198 unsigned TypeShiftAmt = i & (SplatBitSize-1); 2199 2200 // vsplti + shl self. 2201 if (SextVal == (i << (int)TypeShiftAmt)) { 2202 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2203 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2204 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 2205 Intrinsic::ppc_altivec_vslw 2206 }; 2207 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2208 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2209 } 2210 2211 // vsplti + srl self. 2212 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2213 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2214 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2215 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 2216 Intrinsic::ppc_altivec_vsrw 2217 }; 2218 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2219 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2220 } 2221 2222 // vsplti + sra self. 2223 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2224 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2225 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2226 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 2227 Intrinsic::ppc_altivec_vsraw 2228 }; 2229 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2230 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2231 } 2232 2233 // vsplti + rol self. 2234 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 2235 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 2236 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2237 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2238 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 2239 Intrinsic::ppc_altivec_vrlw 2240 }; 2241 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2242 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2243 } 2244 2245 // t = vsplti c, result = vsldoi t, t, 1 2246 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 2247 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2248 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 2249 } 2250 // t = vsplti c, result = vsldoi t, t, 2 2251 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 2252 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2253 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 2254 } 2255 // t = vsplti c, result = vsldoi t, t, 3 2256 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 2257 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2258 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 2259 } 2260 } 2261 2262 // Three instruction sequences. 2263 2264 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 2265 if (SextVal >= 0 && SextVal <= 31) { 2266 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 2267 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2268 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS); 2269 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2270 } 2271 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 2272 if (SextVal >= -31 && SextVal <= 0) { 2273 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 2274 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2275 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS); 2276 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2277 } 2278 } 2279 2280 return SDOperand(); 2281} 2282 2283/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2284/// the specified operations to build the shuffle. 2285static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 2286 SDOperand RHS, SelectionDAG &DAG) { 2287 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2288 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2289 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2290 2291 enum { 2292 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2293 OP_VMRGHW, 2294 OP_VMRGLW, 2295 OP_VSPLTISW0, 2296 OP_VSPLTISW1, 2297 OP_VSPLTISW2, 2298 OP_VSPLTISW3, 2299 OP_VSLDOI4, 2300 OP_VSLDOI8, 2301 OP_VSLDOI12 2302 }; 2303 2304 if (OpNum == OP_COPY) { 2305 if (LHSID == (1*9+2)*9+3) return LHS; 2306 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2307 return RHS; 2308 } 2309 2310 SDOperand OpLHS, OpRHS; 2311 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 2312 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 2313 2314 unsigned ShufIdxs[16]; 2315 switch (OpNum) { 2316 default: assert(0 && "Unknown i32 permute!"); 2317 case OP_VMRGHW: 2318 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 2319 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 2320 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 2321 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 2322 break; 2323 case OP_VMRGLW: 2324 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 2325 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 2326 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 2327 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 2328 break; 2329 case OP_VSPLTISW0: 2330 for (unsigned i = 0; i != 16; ++i) 2331 ShufIdxs[i] = (i&3)+0; 2332 break; 2333 case OP_VSPLTISW1: 2334 for (unsigned i = 0; i != 16; ++i) 2335 ShufIdxs[i] = (i&3)+4; 2336 break; 2337 case OP_VSPLTISW2: 2338 for (unsigned i = 0; i != 16; ++i) 2339 ShufIdxs[i] = (i&3)+8; 2340 break; 2341 case OP_VSPLTISW3: 2342 for (unsigned i = 0; i != 16; ++i) 2343 ShufIdxs[i] = (i&3)+12; 2344 break; 2345 case OP_VSLDOI4: 2346 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 2347 case OP_VSLDOI8: 2348 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 2349 case OP_VSLDOI12: 2350 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 2351 } 2352 SDOperand Ops[16]; 2353 for (unsigned i = 0; i != 16; ++i) 2354 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 2355 2356 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 2357 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2358} 2359 2360/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 2361/// is a shuffle we can handle in a single instruction, return it. Otherwise, 2362/// return the code it can be lowered into. Worst case, it can always be 2363/// lowered into a vperm. 2364static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 2365 SDOperand V1 = Op.getOperand(0); 2366 SDOperand V2 = Op.getOperand(1); 2367 SDOperand PermMask = Op.getOperand(2); 2368 2369 // Cases that are handled by instructions that take permute immediates 2370 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 2371 // selected by the instruction selector. 2372 if (V2.getOpcode() == ISD::UNDEF) { 2373 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 2374 PPC::isSplatShuffleMask(PermMask.Val, 2) || 2375 PPC::isSplatShuffleMask(PermMask.Val, 4) || 2376 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 2377 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 2378 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 2379 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 2380 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 2381 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 2382 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 2383 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 2384 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 2385 return Op; 2386 } 2387 } 2388 2389 // Altivec has a variety of "shuffle immediates" that take two vector inputs 2390 // and produce a fixed permutation. If any of these match, do not lower to 2391 // VPERM. 2392 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 2393 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 2394 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 2395 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 2396 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 2397 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 2398 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 2399 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 2400 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 2401 return Op; 2402 2403 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 2404 // perfect shuffle table to emit an optimal matching sequence. 2405 unsigned PFIndexes[4]; 2406 bool isFourElementShuffle = true; 2407 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 2408 unsigned EltNo = 8; // Start out undef. 2409 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 2410 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 2411 continue; // Undef, ignore it. 2412 2413 unsigned ByteSource = 2414 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 2415 if ((ByteSource & 3) != j) { 2416 isFourElementShuffle = false; 2417 break; 2418 } 2419 2420 if (EltNo == 8) { 2421 EltNo = ByteSource/4; 2422 } else if (EltNo != ByteSource/4) { 2423 isFourElementShuffle = false; 2424 break; 2425 } 2426 } 2427 PFIndexes[i] = EltNo; 2428 } 2429 2430 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 2431 // perfect shuffle vector to determine if it is cost effective to do this as 2432 // discrete instructions, or whether we should use a vperm. 2433 if (isFourElementShuffle) { 2434 // Compute the index in the perfect shuffle table. 2435 unsigned PFTableIndex = 2436 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2437 2438 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2439 unsigned Cost = (PFEntry >> 30); 2440 2441 // Determining when to avoid vperm is tricky. Many things affect the cost 2442 // of vperm, particularly how many times the perm mask needs to be computed. 2443 // For example, if the perm mask can be hoisted out of a loop or is already 2444 // used (perhaps because there are multiple permutes with the same shuffle 2445 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 2446 // the loop requires an extra register. 2447 // 2448 // As a compromise, we only emit discrete instructions if the shuffle can be 2449 // generated in 3 or fewer operations. When we have loop information 2450 // available, if this block is within a loop, we should avoid using vperm 2451 // for 3-operation perms and use a constant pool load instead. 2452 if (Cost < 3) 2453 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 2454 } 2455 2456 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 2457 // vector that will get spilled to the constant pool. 2458 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 2459 2460 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 2461 // that it is in input element units, not in bytes. Convert now. 2462 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType()); 2463 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 2464 2465 SmallVector<SDOperand, 16> ResultMask; 2466 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 2467 unsigned SrcElt; 2468 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 2469 SrcElt = 0; 2470 else 2471 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 2472 2473 for (unsigned j = 0; j != BytesPerElement; ++j) 2474 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 2475 MVT::i8)); 2476 } 2477 2478 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 2479 &ResultMask[0], ResultMask.size()); 2480 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 2481} 2482 2483/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 2484/// altivec comparison. If it is, return true and fill in Opc/isDot with 2485/// information about the intrinsic. 2486static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 2487 bool &isDot) { 2488 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 2489 CompareOpc = -1; 2490 isDot = false; 2491 switch (IntrinsicID) { 2492 default: return false; 2493 // Comparison predicates. 2494 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 2495 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 2496 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 2497 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 2498 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 2499 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 2500 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 2501 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 2502 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 2503 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 2504 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 2505 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 2506 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 2507 2508 // Normal Comparisons. 2509 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 2510 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 2511 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 2512 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 2513 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 2514 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 2515 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 2516 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 2517 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 2518 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 2519 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 2520 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 2521 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 2522 } 2523 return true; 2524} 2525 2526/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 2527/// lower, do it, otherwise return null. 2528static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 2529 // If this is a lowered altivec predicate compare, CompareOpc is set to the 2530 // opcode number of the comparison. 2531 int CompareOpc; 2532 bool isDot; 2533 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 2534 return SDOperand(); // Don't custom lower most intrinsics. 2535 2536 // If this is a non-dot comparison, make the VCMP node and we are done. 2537 if (!isDot) { 2538 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 2539 Op.getOperand(1), Op.getOperand(2), 2540 DAG.getConstant(CompareOpc, MVT::i32)); 2541 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 2542 } 2543 2544 // Create the PPCISD altivec 'dot' comparison node. 2545 SDOperand Ops[] = { 2546 Op.getOperand(2), // LHS 2547 Op.getOperand(3), // RHS 2548 DAG.getConstant(CompareOpc, MVT::i32) 2549 }; 2550 std::vector<MVT::ValueType> VTs; 2551 VTs.push_back(Op.getOperand(2).getValueType()); 2552 VTs.push_back(MVT::Flag); 2553 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2554 2555 // Now that we have the comparison, emit a copy from the CR to a GPR. 2556 // This is flagged to the above dot comparison. 2557 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 2558 DAG.getRegister(PPC::CR6, MVT::i32), 2559 CompNode.getValue(1)); 2560 2561 // Unpack the result based on how the target uses it. 2562 unsigned BitNo; // Bit # of CR6. 2563 bool InvertBit; // Invert result? 2564 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 2565 default: // Can't happen, don't crash on invalid number though. 2566 case 0: // Return the value of the EQ bit of CR6. 2567 BitNo = 0; InvertBit = false; 2568 break; 2569 case 1: // Return the inverted value of the EQ bit of CR6. 2570 BitNo = 0; InvertBit = true; 2571 break; 2572 case 2: // Return the value of the LT bit of CR6. 2573 BitNo = 2; InvertBit = false; 2574 break; 2575 case 3: // Return the inverted value of the LT bit of CR6. 2576 BitNo = 2; InvertBit = true; 2577 break; 2578 } 2579 2580 // Shift the bit into the low position. 2581 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 2582 DAG.getConstant(8-(3-BitNo), MVT::i32)); 2583 // Isolate the bit. 2584 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 2585 DAG.getConstant(1, MVT::i32)); 2586 2587 // If we are supposed to, toggle the bit. 2588 if (InvertBit) 2589 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 2590 DAG.getConstant(1, MVT::i32)); 2591 return Flags; 2592} 2593 2594static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2595 // Create a stack slot that is 16-byte aligned. 2596 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2597 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 2598 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2599 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2600 2601 // Store the input value into Value#0 of the stack slot. 2602 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 2603 Op.getOperand(0), FIdx, NULL, 0); 2604 // Load it out. 2605 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 2606} 2607 2608static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 2609 if (Op.getValueType() == MVT::v4i32) { 2610 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2611 2612 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 2613 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 2614 2615 SDOperand RHSSwap = // = vrlw RHS, 16 2616 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 2617 2618 // Shrinkify inputs to v8i16. 2619 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 2620 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 2621 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 2622 2623 // Low parts multiplied together, generating 32-bit results (we ignore the 2624 // top parts). 2625 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 2626 LHS, RHS, DAG, MVT::v4i32); 2627 2628 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 2629 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 2630 // Shift the high parts up 16 bits. 2631 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 2632 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 2633 } else if (Op.getValueType() == MVT::v8i16) { 2634 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2635 2636 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 2637 2638 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 2639 LHS, RHS, Zero, DAG); 2640 } else if (Op.getValueType() == MVT::v16i8) { 2641 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2642 2643 // Multiply the even 8-bit parts, producing 16-bit sums. 2644 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 2645 LHS, RHS, DAG, MVT::v8i16); 2646 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 2647 2648 // Multiply the odd 8-bit parts, producing 16-bit sums. 2649 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 2650 LHS, RHS, DAG, MVT::v8i16); 2651 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 2652 2653 // Merge the results together. 2654 SDOperand Ops[16]; 2655 for (unsigned i = 0; i != 8; ++i) { 2656 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 2657 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 2658 } 2659 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 2660 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2661 } else { 2662 assert(0 && "Unknown mul to lower!"); 2663 abort(); 2664 } 2665} 2666 2667/// LowerOperation - Provide custom lowering hooks for some operations. 2668/// 2669SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2670 switch (Op.getOpcode()) { 2671 default: assert(0 && "Wasn't expecting to be able to lower this!"); 2672 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2673 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2674 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 2675 case ISD::SETCC: return LowerSETCC(Op, DAG); 2676 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 2677 case ISD::FORMAL_ARGUMENTS: 2678 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, PPCSubTarget); 2679 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget); 2680 case ISD::RET: return LowerRET(Op, DAG); 2681 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 2682 case ISD::DYNAMIC_STACKALLOC: 2683 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 2684 2685 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 2686 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 2687 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 2688 2689 // Lower 64-bit shifts. 2690 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 2691 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 2692 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 2693 2694 // Vector-related lowering. 2695 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 2696 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 2697 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 2698 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 2699 case ISD::MUL: return LowerMUL(Op, DAG); 2700 2701 // Frame & Return address. Currently unimplemented 2702 case ISD::RETURNADDR: break; 2703 case ISD::FRAMEADDR: break; 2704 } 2705 return SDOperand(); 2706} 2707 2708//===----------------------------------------------------------------------===// 2709// Other Lowering Code 2710//===----------------------------------------------------------------------===// 2711 2712MachineBasicBlock * 2713PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2714 MachineBasicBlock *BB) { 2715 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2716 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 2717 MI->getOpcode() == PPC::SELECT_CC_I8 || 2718 MI->getOpcode() == PPC::SELECT_CC_F4 || 2719 MI->getOpcode() == PPC::SELECT_CC_F8 || 2720 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 2721 "Unexpected instr type to insert"); 2722 2723 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 2724 // control-flow pattern. The incoming instruction knows the destination vreg 2725 // to set, the condition code register to branch on, the true/false values to 2726 // select between, and a branch opcode to use. 2727 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2728 ilist<MachineBasicBlock>::iterator It = BB; 2729 ++It; 2730 2731 // thisMBB: 2732 // ... 2733 // TrueVal = ... 2734 // cmpTY ccX, r1, r2 2735 // bCC copy1MBB 2736 // fallthrough --> copy0MBB 2737 MachineBasicBlock *thisMBB = BB; 2738 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 2739 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 2740 unsigned SelectPred = MI->getOperand(4).getImm(); 2741 BuildMI(BB, TII->get(PPC::BCC)) 2742 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 2743 MachineFunction *F = BB->getParent(); 2744 F->getBasicBlockList().insert(It, copy0MBB); 2745 F->getBasicBlockList().insert(It, sinkMBB); 2746 // Update machine-CFG edges by first adding all successors of the current 2747 // block to the new block which will contain the Phi node for the select. 2748 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 2749 e = BB->succ_end(); i != e; ++i) 2750 sinkMBB->addSuccessor(*i); 2751 // Next, remove all successors of the current block, and add the true 2752 // and fallthrough blocks as its successors. 2753 while(!BB->succ_empty()) 2754 BB->removeSuccessor(BB->succ_begin()); 2755 BB->addSuccessor(copy0MBB); 2756 BB->addSuccessor(sinkMBB); 2757 2758 // copy0MBB: 2759 // %FalseValue = ... 2760 // # fallthrough to sinkMBB 2761 BB = copy0MBB; 2762 2763 // Update machine-CFG edges 2764 BB->addSuccessor(sinkMBB); 2765 2766 // sinkMBB: 2767 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 2768 // ... 2769 BB = sinkMBB; 2770 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 2771 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 2772 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 2773 2774 delete MI; // The pseudo instruction is gone now. 2775 return BB; 2776} 2777 2778//===----------------------------------------------------------------------===// 2779// Target Optimization Hooks 2780//===----------------------------------------------------------------------===// 2781 2782SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 2783 DAGCombinerInfo &DCI) const { 2784 TargetMachine &TM = getTargetMachine(); 2785 SelectionDAG &DAG = DCI.DAG; 2786 switch (N->getOpcode()) { 2787 default: break; 2788 case PPCISD::SHL: 2789 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2790 if (C->getValue() == 0) // 0 << V -> 0. 2791 return N->getOperand(0); 2792 } 2793 break; 2794 case PPCISD::SRL: 2795 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2796 if (C->getValue() == 0) // 0 >>u V -> 0. 2797 return N->getOperand(0); 2798 } 2799 break; 2800 case PPCISD::SRA: 2801 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2802 if (C->getValue() == 0 || // 0 >>s V -> 0. 2803 C->isAllOnesValue()) // -1 >>s V -> -1. 2804 return N->getOperand(0); 2805 } 2806 break; 2807 2808 case ISD::SINT_TO_FP: 2809 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 2810 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 2811 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 2812 // We allow the src/dst to be either f32/f64, but the intermediate 2813 // type must be i64. 2814 if (N->getOperand(0).getValueType() == MVT::i64) { 2815 SDOperand Val = N->getOperand(0).getOperand(0); 2816 if (Val.getValueType() == MVT::f32) { 2817 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 2818 DCI.AddToWorklist(Val.Val); 2819 } 2820 2821 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 2822 DCI.AddToWorklist(Val.Val); 2823 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 2824 DCI.AddToWorklist(Val.Val); 2825 if (N->getValueType(0) == MVT::f32) { 2826 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 2827 DCI.AddToWorklist(Val.Val); 2828 } 2829 return Val; 2830 } else if (N->getOperand(0).getValueType() == MVT::i32) { 2831 // If the intermediate type is i32, we can avoid the load/store here 2832 // too. 2833 } 2834 } 2835 } 2836 break; 2837 case ISD::STORE: 2838 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 2839 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 2840 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 2841 N->getOperand(1).getValueType() == MVT::i32) { 2842 SDOperand Val = N->getOperand(1).getOperand(0); 2843 if (Val.getValueType() == MVT::f32) { 2844 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 2845 DCI.AddToWorklist(Val.Val); 2846 } 2847 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 2848 DCI.AddToWorklist(Val.Val); 2849 2850 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 2851 N->getOperand(2), N->getOperand(3)); 2852 DCI.AddToWorklist(Val.Val); 2853 return Val; 2854 } 2855 2856 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 2857 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 2858 N->getOperand(1).Val->hasOneUse() && 2859 (N->getOperand(1).getValueType() == MVT::i32 || 2860 N->getOperand(1).getValueType() == MVT::i16)) { 2861 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 2862 // Do an any-extend to 32-bits if this is a half-word input. 2863 if (BSwapOp.getValueType() == MVT::i16) 2864 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 2865 2866 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 2867 N->getOperand(2), N->getOperand(3), 2868 DAG.getValueType(N->getOperand(1).getValueType())); 2869 } 2870 break; 2871 case ISD::BSWAP: 2872 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 2873 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 2874 N->getOperand(0).hasOneUse() && 2875 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 2876 SDOperand Load = N->getOperand(0); 2877 LoadSDNode *LD = cast<LoadSDNode>(Load); 2878 // Create the byte-swapping load. 2879 std::vector<MVT::ValueType> VTs; 2880 VTs.push_back(MVT::i32); 2881 VTs.push_back(MVT::Other); 2882 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); 2883 SDOperand Ops[] = { 2884 LD->getChain(), // Chain 2885 LD->getBasePtr(), // Ptr 2886 SV, // SrcValue 2887 DAG.getValueType(N->getValueType(0)) // VT 2888 }; 2889 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 2890 2891 // If this is an i16 load, insert the truncate. 2892 SDOperand ResVal = BSLoad; 2893 if (N->getValueType(0) == MVT::i16) 2894 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 2895 2896 // First, combine the bswap away. This makes the value produced by the 2897 // load dead. 2898 DCI.CombineTo(N, ResVal); 2899 2900 // Next, combine the load away, we give it a bogus result value but a real 2901 // chain result. The result value is dead because the bswap is dead. 2902 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 2903 2904 // Return N so it doesn't get rechecked! 2905 return SDOperand(N, 0); 2906 } 2907 2908 break; 2909 case PPCISD::VCMP: { 2910 // If a VCMPo node already exists with exactly the same operands as this 2911 // node, use its result instead of this node (VCMPo computes both a CR6 and 2912 // a normal output). 2913 // 2914 if (!N->getOperand(0).hasOneUse() && 2915 !N->getOperand(1).hasOneUse() && 2916 !N->getOperand(2).hasOneUse()) { 2917 2918 // Scan all of the users of the LHS, looking for VCMPo's that match. 2919 SDNode *VCMPoNode = 0; 2920 2921 SDNode *LHSN = N->getOperand(0).Val; 2922 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 2923 UI != E; ++UI) 2924 if ((*UI)->getOpcode() == PPCISD::VCMPo && 2925 (*UI)->getOperand(1) == N->getOperand(1) && 2926 (*UI)->getOperand(2) == N->getOperand(2) && 2927 (*UI)->getOperand(0) == N->getOperand(0)) { 2928 VCMPoNode = *UI; 2929 break; 2930 } 2931 2932 // If there is no VCMPo node, or if the flag value has a single use, don't 2933 // transform this. 2934 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 2935 break; 2936 2937 // Look at the (necessarily single) use of the flag value. If it has a 2938 // chain, this transformation is more complex. Note that multiple things 2939 // could use the value result, which we should ignore. 2940 SDNode *FlagUser = 0; 2941 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 2942 FlagUser == 0; ++UI) { 2943 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 2944 SDNode *User = *UI; 2945 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2946 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 2947 FlagUser = User; 2948 break; 2949 } 2950 } 2951 } 2952 2953 // If the user is a MFCR instruction, we know this is safe. Otherwise we 2954 // give up for right now. 2955 if (FlagUser->getOpcode() == PPCISD::MFCR) 2956 return SDOperand(VCMPoNode, 0); 2957 } 2958 break; 2959 } 2960 case ISD::BR_CC: { 2961 // If this is a branch on an altivec predicate comparison, lower this so 2962 // that we don't have to do a MFCR: instead, branch directly on CR6. This 2963 // lowering is done pre-legalize, because the legalizer lowers the predicate 2964 // compare down to code that is difficult to reassemble. 2965 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2966 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 2967 int CompareOpc; 2968 bool isDot; 2969 2970 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 2971 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 2972 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 2973 assert(isDot && "Can't compare against a vector result!"); 2974 2975 // If this is a comparison against something other than 0/1, then we know 2976 // that the condition is never/always true. 2977 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 2978 if (Val != 0 && Val != 1) { 2979 if (CC == ISD::SETEQ) // Cond never true, remove branch. 2980 return N->getOperand(0); 2981 // Always !=, turn it into an unconditional branch. 2982 return DAG.getNode(ISD::BR, MVT::Other, 2983 N->getOperand(0), N->getOperand(4)); 2984 } 2985 2986 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 2987 2988 // Create the PPCISD altivec 'dot' comparison node. 2989 std::vector<MVT::ValueType> VTs; 2990 SDOperand Ops[] = { 2991 LHS.getOperand(2), // LHS of compare 2992 LHS.getOperand(3), // RHS of compare 2993 DAG.getConstant(CompareOpc, MVT::i32) 2994 }; 2995 VTs.push_back(LHS.getOperand(2).getValueType()); 2996 VTs.push_back(MVT::Flag); 2997 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2998 2999 // Unpack the result based on how the target uses it. 3000 PPC::Predicate CompOpc; 3001 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 3002 default: // Can't happen, don't crash on invalid number though. 3003 case 0: // Branch on the value of the EQ bit of CR6. 3004 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 3005 break; 3006 case 1: // Branch on the inverted value of the EQ bit of CR6. 3007 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 3008 break; 3009 case 2: // Branch on the value of the LT bit of CR6. 3010 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 3011 break; 3012 case 3: // Branch on the inverted value of the LT bit of CR6. 3013 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 3014 break; 3015 } 3016 3017 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 3018 DAG.getConstant(CompOpc, MVT::i32), 3019 DAG.getRegister(PPC::CR6, MVT::i32), 3020 N->getOperand(4), CompNode.getValue(1)); 3021 } 3022 break; 3023 } 3024 } 3025 3026 return SDOperand(); 3027} 3028 3029//===----------------------------------------------------------------------===// 3030// Inline Assembly Support 3031//===----------------------------------------------------------------------===// 3032 3033void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 3034 uint64_t Mask, 3035 uint64_t &KnownZero, 3036 uint64_t &KnownOne, 3037 unsigned Depth) const { 3038 KnownZero = 0; 3039 KnownOne = 0; 3040 switch (Op.getOpcode()) { 3041 default: break; 3042 case PPCISD::LBRX: { 3043 // lhbrx is known to have the top bits cleared out. 3044 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 3045 KnownZero = 0xFFFF0000; 3046 break; 3047 } 3048 case ISD::INTRINSIC_WO_CHAIN: { 3049 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 3050 default: break; 3051 case Intrinsic::ppc_altivec_vcmpbfp_p: 3052 case Intrinsic::ppc_altivec_vcmpeqfp_p: 3053 case Intrinsic::ppc_altivec_vcmpequb_p: 3054 case Intrinsic::ppc_altivec_vcmpequh_p: 3055 case Intrinsic::ppc_altivec_vcmpequw_p: 3056 case Intrinsic::ppc_altivec_vcmpgefp_p: 3057 case Intrinsic::ppc_altivec_vcmpgtfp_p: 3058 case Intrinsic::ppc_altivec_vcmpgtsb_p: 3059 case Intrinsic::ppc_altivec_vcmpgtsh_p: 3060 case Intrinsic::ppc_altivec_vcmpgtsw_p: 3061 case Intrinsic::ppc_altivec_vcmpgtub_p: 3062 case Intrinsic::ppc_altivec_vcmpgtuh_p: 3063 case Intrinsic::ppc_altivec_vcmpgtuw_p: 3064 KnownZero = ~1U; // All bits but the low one are known to be zero. 3065 break; 3066 } 3067 } 3068 } 3069} 3070 3071 3072/// getConstraintType - Given a constraint letter, return the type of 3073/// constraint it is for this target. 3074PPCTargetLowering::ConstraintType 3075PPCTargetLowering::getConstraintType(char ConstraintLetter) const { 3076 switch (ConstraintLetter) { 3077 default: break; 3078 case 'b': 3079 case 'r': 3080 case 'f': 3081 case 'v': 3082 case 'y': 3083 return C_RegisterClass; 3084 } 3085 return TargetLowering::getConstraintType(ConstraintLetter); 3086} 3087 3088std::pair<unsigned, const TargetRegisterClass*> 3089PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3090 MVT::ValueType VT) const { 3091 if (Constraint.size() == 1) { 3092 // GCC RS6000 Constraint Letters 3093 switch (Constraint[0]) { 3094 case 'b': // R1-R31 3095 case 'r': // R0-R31 3096 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 3097 return std::make_pair(0U, PPC::G8RCRegisterClass); 3098 return std::make_pair(0U, PPC::GPRCRegisterClass); 3099 case 'f': 3100 if (VT == MVT::f32) 3101 return std::make_pair(0U, PPC::F4RCRegisterClass); 3102 else if (VT == MVT::f64) 3103 return std::make_pair(0U, PPC::F8RCRegisterClass); 3104 break; 3105 case 'v': 3106 return std::make_pair(0U, PPC::VRRCRegisterClass); 3107 case 'y': // crrc 3108 return std::make_pair(0U, PPC::CRRCRegisterClass); 3109 } 3110 } 3111 3112 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3113} 3114 3115 3116// isOperandValidForConstraint 3117SDOperand PPCTargetLowering:: 3118isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) { 3119 switch (Letter) { 3120 default: break; 3121 case 'I': 3122 case 'J': 3123 case 'K': 3124 case 'L': 3125 case 'M': 3126 case 'N': 3127 case 'O': 3128 case 'P': { 3129 if (!isa<ConstantSDNode>(Op)) return SDOperand(0,0);// Must be an immediate. 3130 unsigned Value = cast<ConstantSDNode>(Op)->getValue(); 3131 switch (Letter) { 3132 default: assert(0 && "Unknown constraint letter!"); 3133 case 'I': // "I" is a signed 16-bit constant. 3134 if ((short)Value == (int)Value) return Op; 3135 break; 3136 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 3137 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 3138 if ((short)Value == 0) return Op; 3139 break; 3140 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 3141 if ((Value >> 16) == 0) return Op; 3142 break; 3143 case 'M': // "M" is a constant that is greater than 31. 3144 if (Value > 31) return Op; 3145 break; 3146 case 'N': // "N" is a positive constant that is an exact power of two. 3147 if ((int)Value > 0 && isPowerOf2_32(Value)) return Op; 3148 break; 3149 case 'O': // "O" is the constant zero. 3150 if (Value == 0) return Op; 3151 break; 3152 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 3153 if ((short)-Value == (int)-Value) return Op; 3154 break; 3155 } 3156 break; 3157 } 3158 } 3159 3160 // Handle standard constraint letters. 3161 return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG); 3162} 3163 3164/// isLegalAddressImmediate - Return true if the integer value can be used 3165/// as the offset of the target addressing mode. 3166bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const { 3167 // PPC allows a sign-extended 16-bit immediate field. 3168 return (V > -(1 << 16) && V < (1 << 16)-1); 3169} 3170 3171bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 3172 return TargetLowering::isLegalAddressImmediate(GV); 3173} 3174