PPCISelLowering.cpp revision ef97c676f97d33312eb5009522a9d51f2c25ccb1
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/Analysis/ScalarEvolutionExpressions.h" 22#include "llvm/CodeGen/CallingConvLower.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineRegisterInfo.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/Constants.h" 29#include "llvm/Function.h" 30#include "llvm/Intrinsics.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/Target/TargetOptions.h" 33#include "llvm/Support/CommandLine.h" 34using namespace llvm; 35 36static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 37cl::desc("enable preincrement load/store generation on PPC (experimental)"), 38 cl::Hidden); 39 40PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 41 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 42 43 setPow2DivIsCheap(); 44 45 // Use _setjmp/_longjmp instead of setjmp/longjmp. 46 setUseUnderscoreSetJmp(true); 47 setUseUnderscoreLongJmp(true); 48 49 // Set up the register classes. 50 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 51 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 52 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 53 54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 55 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 56 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 57 58 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 59 60 // PowerPC has pre-inc load and store's. 61 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 63 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 64 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 65 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 66 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 68 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 69 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 70 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 71 72 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 73 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 74 75 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) 76 setConvertAction(MVT::ppcf128, MVT::f64, Expand); 77 setConvertAction(MVT::ppcf128, MVT::f32, Expand); 78 // This is used in the ppcf128->int sequence. Note it has different semantics 79 // from FP_ROUND: that rounds to nearest, this rounds to zero. 80 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 81 82 // PowerPC has no intrinsics for these particular operations 83 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 84 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 85 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 86 87 // PowerPC has no SREM/UREM instructions 88 setOperationAction(ISD::SREM, MVT::i32, Expand); 89 setOperationAction(ISD::UREM, MVT::i32, Expand); 90 setOperationAction(ISD::SREM, MVT::i64, Expand); 91 setOperationAction(ISD::UREM, MVT::i64, Expand); 92 93 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 94 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 95 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 96 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 97 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 98 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 99 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 100 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 101 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 102 103 // We don't support sin/cos/sqrt/fmod/pow 104 setOperationAction(ISD::FSIN , MVT::f64, Expand); 105 setOperationAction(ISD::FCOS , MVT::f64, Expand); 106 setOperationAction(ISD::FREM , MVT::f64, Expand); 107 setOperationAction(ISD::FPOW , MVT::f64, Expand); 108 setOperationAction(ISD::FSIN , MVT::f32, Expand); 109 setOperationAction(ISD::FCOS , MVT::f32, Expand); 110 setOperationAction(ISD::FREM , MVT::f32, Expand); 111 setOperationAction(ISD::FPOW , MVT::f32, Expand); 112 113 // If we're enabling GP optimizations, use hardware square root 114 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 115 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 116 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 117 } 118 119 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 120 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 121 122 // PowerPC does not have BSWAP, CTPOP or CTTZ 123 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 124 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 125 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 126 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 127 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 128 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 129 130 // PowerPC does not have ROTR 131 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 132 133 // PowerPC does not have Select 134 setOperationAction(ISD::SELECT, MVT::i32, Expand); 135 setOperationAction(ISD::SELECT, MVT::i64, Expand); 136 setOperationAction(ISD::SELECT, MVT::f32, Expand); 137 setOperationAction(ISD::SELECT, MVT::f64, Expand); 138 139 // PowerPC wants to turn select_cc of FP into fsel when possible. 140 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 141 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 142 143 // PowerPC wants to optimize integer setcc a bit 144 setOperationAction(ISD::SETCC, MVT::i32, Custom); 145 146 // PowerPC does not have BRCOND which requires SetCC 147 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 148 149 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 150 151 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 152 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 153 154 // PowerPC does not have [U|S]INT_TO_FP 155 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 156 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 157 158 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 159 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 160 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 161 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 162 163 // We cannot sextinreg(i1). Expand to shifts. 164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 165 166 // Support label based line numbers. 167 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 168 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 169 170 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 171 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 172 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 173 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 174 175 176 // We want to legalize GlobalAddress and ConstantPool nodes into the 177 // appropriate instructions to materialize the address. 178 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 179 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 180 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 181 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 182 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 183 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 184 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 185 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 186 187 // RET must be custom lowered, to meet ABI requirements 188 setOperationAction(ISD::RET , MVT::Other, Custom); 189 190 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 191 setOperationAction(ISD::VASTART , MVT::Other, Custom); 192 193 // VAARG is custom lowered with ELF 32 ABI 194 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) 195 setOperationAction(ISD::VAARG, MVT::Other, Custom); 196 else 197 setOperationAction(ISD::VAARG, MVT::Other, Expand); 198 199 // Use the default implementation. 200 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 201 setOperationAction(ISD::VAEND , MVT::Other, Expand); 202 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 203 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 204 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 206 207 // We want to custom lower some of our intrinsics. 208 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 209 210 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 211 // They also have instructions for converting between i64 and fp. 212 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 213 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 214 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 215 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 216 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 217 218 // FIXME: disable this lowered code. This generates 64-bit register values, 219 // and we don't model the fact that the top part is clobbered by calls. We 220 // need to flag these together so that the value isn't live across a call. 221 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 222 223 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 224 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 225 } else { 226 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 227 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 228 } 229 230 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 231 // 64-bit PowerPC implementations can support i64 types directly 232 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 233 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 234 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 235 } else { 236 // 32-bit PowerPC wants to expand i64 shifts itself. 237 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 238 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 239 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 240 } 241 242 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 243 // First set operation action for all vector types to expand. Then we 244 // will selectively turn on ones that can be effectively codegen'd. 245 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 246 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 247 // add/sub are legal for all supported vector VT's. 248 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 249 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 250 251 // We promote all shuffles to v16i8. 252 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 253 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 254 255 // We promote all non-typed operations to v4i32. 256 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 257 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 258 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 259 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 260 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 261 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 262 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 263 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 264 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 265 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 266 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 267 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 268 269 // No other operations are legal. 270 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 271 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 272 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 273 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 274 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 275 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 276 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); 277 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 278 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 279 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 280 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); 281 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); 282 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); 283 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); 284 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 285 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); 286 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); 287 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); 288 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); 289 } 290 291 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 292 // with merges, splats, etc. 293 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 294 295 setOperationAction(ISD::AND , MVT::v4i32, Legal); 296 setOperationAction(ISD::OR , MVT::v4i32, Legal); 297 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 298 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 299 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 300 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 301 302 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 303 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 304 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 305 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 306 307 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 308 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 309 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 310 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 311 312 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 313 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 314 315 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 316 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 317 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 318 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 319 } 320 321 setSetCCResultType(MVT::i32); 322 setShiftAmountType(MVT::i32); 323 setSetCCResultContents(ZeroOrOneSetCCResult); 324 325 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 326 setStackPointerRegisterToSaveRestore(PPC::X1); 327 setExceptionPointerRegister(PPC::X3); 328 setExceptionSelectorRegister(PPC::X4); 329 } else { 330 setStackPointerRegisterToSaveRestore(PPC::R1); 331 setExceptionPointerRegister(PPC::R3); 332 setExceptionSelectorRegister(PPC::R4); 333 } 334 335 // We have target-specific dag combine patterns for the following nodes: 336 setTargetDAGCombine(ISD::SINT_TO_FP); 337 setTargetDAGCombine(ISD::STORE); 338 setTargetDAGCombine(ISD::BR_CC); 339 setTargetDAGCombine(ISD::BSWAP); 340 341 // Darwin long double math library functions have $LDBL128 appended. 342 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 343 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 344 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 345 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 346 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 347 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 348 } 349 350 computeRegisterProperties(); 351} 352 353const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 354 switch (Opcode) { 355 default: return 0; 356 case PPCISD::FSEL: return "PPCISD::FSEL"; 357 case PPCISD::FCFID: return "PPCISD::FCFID"; 358 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 359 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 360 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 361 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 362 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 363 case PPCISD::VPERM: return "PPCISD::VPERM"; 364 case PPCISD::Hi: return "PPCISD::Hi"; 365 case PPCISD::Lo: return "PPCISD::Lo"; 366 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 367 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 368 case PPCISD::SRL: return "PPCISD::SRL"; 369 case PPCISD::SRA: return "PPCISD::SRA"; 370 case PPCISD::SHL: return "PPCISD::SHL"; 371 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 372 case PPCISD::STD_32: return "PPCISD::STD_32"; 373 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 374 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 375 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 376 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 377 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 378 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 379 case PPCISD::MFCR: return "PPCISD::MFCR"; 380 case PPCISD::VCMP: return "PPCISD::VCMP"; 381 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 382 case PPCISD::LBRX: return "PPCISD::LBRX"; 383 case PPCISD::STBRX: return "PPCISD::STBRX"; 384 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 385 case PPCISD::MFFS: return "PPCISD::MFFS"; 386 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 387 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 388 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 389 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 390 } 391} 392 393//===----------------------------------------------------------------------===// 394// Node matching predicates, for use by the tblgen matching code. 395//===----------------------------------------------------------------------===// 396 397/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 398static bool isFloatingPointZero(SDOperand Op) { 399 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 400 return CFP->getValueAPF().isZero(); 401 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 402 // Maybe this has already been legalized into the constant pool? 403 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 404 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 405 return CFP->getValueAPF().isZero(); 406 } 407 return false; 408} 409 410/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 411/// true if Op is undef or if it matches the specified value. 412static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 413 return Op.getOpcode() == ISD::UNDEF || 414 cast<ConstantSDNode>(Op)->getValue() == Val; 415} 416 417/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 418/// VPKUHUM instruction. 419bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 420 if (!isUnary) { 421 for (unsigned i = 0; i != 16; ++i) 422 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 423 return false; 424 } else { 425 for (unsigned i = 0; i != 8; ++i) 426 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 427 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 428 return false; 429 } 430 return true; 431} 432 433/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 434/// VPKUWUM instruction. 435bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 436 if (!isUnary) { 437 for (unsigned i = 0; i != 16; i += 2) 438 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 439 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 440 return false; 441 } else { 442 for (unsigned i = 0; i != 8; i += 2) 443 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 444 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 445 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 446 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 447 return false; 448 } 449 return true; 450} 451 452/// isVMerge - Common function, used to match vmrg* shuffles. 453/// 454static bool isVMerge(SDNode *N, unsigned UnitSize, 455 unsigned LHSStart, unsigned RHSStart) { 456 assert(N->getOpcode() == ISD::BUILD_VECTOR && 457 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 458 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 459 "Unsupported merge size!"); 460 461 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 462 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 463 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 464 LHSStart+j+i*UnitSize) || 465 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 466 RHSStart+j+i*UnitSize)) 467 return false; 468 } 469 return true; 470} 471 472/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 473/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 474bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 475 if (!isUnary) 476 return isVMerge(N, UnitSize, 8, 24); 477 return isVMerge(N, UnitSize, 8, 8); 478} 479 480/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 481/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 482bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 483 if (!isUnary) 484 return isVMerge(N, UnitSize, 0, 16); 485 return isVMerge(N, UnitSize, 0, 0); 486} 487 488 489/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 490/// amount, otherwise return -1. 491int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 492 assert(N->getOpcode() == ISD::BUILD_VECTOR && 493 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 494 // Find the first non-undef value in the shuffle mask. 495 unsigned i; 496 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 497 /*search*/; 498 499 if (i == 16) return -1; // all undef. 500 501 // Otherwise, check to see if the rest of the elements are consequtively 502 // numbered from this value. 503 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 504 if (ShiftAmt < i) return -1; 505 ShiftAmt -= i; 506 507 if (!isUnary) { 508 // Check the rest of the elements to see if they are consequtive. 509 for (++i; i != 16; ++i) 510 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 511 return -1; 512 } else { 513 // Check the rest of the elements to see if they are consequtive. 514 for (++i; i != 16; ++i) 515 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 516 return -1; 517 } 518 519 return ShiftAmt; 520} 521 522/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 523/// specifies a splat of a single element that is suitable for input to 524/// VSPLTB/VSPLTH/VSPLTW. 525bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 526 assert(N->getOpcode() == ISD::BUILD_VECTOR && 527 N->getNumOperands() == 16 && 528 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 529 530 // This is a splat operation if each element of the permute is the same, and 531 // if the value doesn't reference the second vector. 532 unsigned ElementBase = 0; 533 SDOperand Elt = N->getOperand(0); 534 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 535 ElementBase = EltV->getValue(); 536 else 537 return false; // FIXME: Handle UNDEF elements too! 538 539 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 540 return false; 541 542 // Check that they are consequtive. 543 for (unsigned i = 1; i != EltSize; ++i) { 544 if (!isa<ConstantSDNode>(N->getOperand(i)) || 545 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 546 return false; 547 } 548 549 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 550 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 551 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 552 assert(isa<ConstantSDNode>(N->getOperand(i)) && 553 "Invalid VECTOR_SHUFFLE mask!"); 554 for (unsigned j = 0; j != EltSize; ++j) 555 if (N->getOperand(i+j) != N->getOperand(j)) 556 return false; 557 } 558 559 return true; 560} 561 562/// isAllNegativeZeroVector - Returns true if all elements of build_vector 563/// are -0.0. 564bool PPC::isAllNegativeZeroVector(SDNode *N) { 565 assert(N->getOpcode() == ISD::BUILD_VECTOR); 566 if (PPC::isSplatShuffleMask(N, N->getNumOperands())) 567 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) 568 return CFP->getValueAPF().isNegZero(); 569 return false; 570} 571 572/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 573/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 574unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 575 assert(isSplatShuffleMask(N, EltSize)); 576 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 577} 578 579/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 580/// by using a vspltis[bhw] instruction of the specified element size, return 581/// the constant being splatted. The ByteSize field indicates the number of 582/// bytes of each element [124] -> [bhw]. 583SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 584 SDOperand OpVal(0, 0); 585 586 // If ByteSize of the splat is bigger than the element size of the 587 // build_vector, then we have a case where we are checking for a splat where 588 // multiple elements of the buildvector are folded together into a single 589 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 590 unsigned EltSize = 16/N->getNumOperands(); 591 if (EltSize < ByteSize) { 592 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 593 SDOperand UniquedVals[4]; 594 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 595 596 // See if all of the elements in the buildvector agree across. 597 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 598 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 599 // If the element isn't a constant, bail fully out. 600 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 601 602 603 if (UniquedVals[i&(Multiple-1)].Val == 0) 604 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 605 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 606 return SDOperand(); // no match. 607 } 608 609 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 610 // either constant or undef values that are identical for each chunk. See 611 // if these chunks can form into a larger vspltis*. 612 613 // Check to see if all of the leading entries are either 0 or -1. If 614 // neither, then this won't fit into the immediate field. 615 bool LeadingZero = true; 616 bool LeadingOnes = true; 617 for (unsigned i = 0; i != Multiple-1; ++i) { 618 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 619 620 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 621 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 622 } 623 // Finally, check the least significant entry. 624 if (LeadingZero) { 625 if (UniquedVals[Multiple-1].Val == 0) 626 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 627 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 628 if (Val < 16) 629 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 630 } 631 if (LeadingOnes) { 632 if (UniquedVals[Multiple-1].Val == 0) 633 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 634 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 635 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 636 return DAG.getTargetConstant(Val, MVT::i32); 637 } 638 639 return SDOperand(); 640 } 641 642 // Check to see if this buildvec has a single non-undef value in its elements. 643 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 644 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 645 if (OpVal.Val == 0) 646 OpVal = N->getOperand(i); 647 else if (OpVal != N->getOperand(i)) 648 return SDOperand(); 649 } 650 651 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 652 653 unsigned ValSizeInBytes = 0; 654 uint64_t Value = 0; 655 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 656 Value = CN->getValue(); 657 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 658 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 659 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 660 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 661 ValSizeInBytes = 4; 662 } 663 664 // If the splat value is larger than the element value, then we can never do 665 // this splat. The only case that we could fit the replicated bits into our 666 // immediate field for would be zero, and we prefer to use vxor for it. 667 if (ValSizeInBytes < ByteSize) return SDOperand(); 668 669 // If the element value is larger than the splat value, cut it in half and 670 // check to see if the two halves are equal. Continue doing this until we 671 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 672 while (ValSizeInBytes > ByteSize) { 673 ValSizeInBytes >>= 1; 674 675 // If the top half equals the bottom half, we're still ok. 676 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 677 (Value & ((1 << (8*ValSizeInBytes))-1))) 678 return SDOperand(); 679 } 680 681 // Properly sign extend the value. 682 int ShAmt = (4-ByteSize)*8; 683 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 684 685 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 686 if (MaskVal == 0) return SDOperand(); 687 688 // Finally, if this value fits in a 5 bit sext field, return it 689 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 690 return DAG.getTargetConstant(MaskVal, MVT::i32); 691 return SDOperand(); 692} 693 694//===----------------------------------------------------------------------===// 695// Addressing Mode Selection 696//===----------------------------------------------------------------------===// 697 698/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 699/// or 64-bit immediate, and if the value can be accurately represented as a 700/// sign extension from a 16-bit value. If so, this returns true and the 701/// immediate. 702static bool isIntS16Immediate(SDNode *N, short &Imm) { 703 if (N->getOpcode() != ISD::Constant) 704 return false; 705 706 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 707 if (N->getValueType(0) == MVT::i32) 708 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 709 else 710 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 711} 712static bool isIntS16Immediate(SDOperand Op, short &Imm) { 713 return isIntS16Immediate(Op.Val, Imm); 714} 715 716 717/// SelectAddressRegReg - Given the specified addressed, check to see if it 718/// can be represented as an indexed [r+r] operation. Returns false if it 719/// can be more efficiently represented with [r+imm]. 720bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, 721 SDOperand &Index, 722 SelectionDAG &DAG) { 723 short imm = 0; 724 if (N.getOpcode() == ISD::ADD) { 725 if (isIntS16Immediate(N.getOperand(1), imm)) 726 return false; // r+i 727 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 728 return false; // r+i 729 730 Base = N.getOperand(0); 731 Index = N.getOperand(1); 732 return true; 733 } else if (N.getOpcode() == ISD::OR) { 734 if (isIntS16Immediate(N.getOperand(1), imm)) 735 return false; // r+i can fold it if we can. 736 737 // If this is an or of disjoint bitfields, we can codegen this as an add 738 // (for better address arithmetic) if the LHS and RHS of the OR are provably 739 // disjoint. 740 uint64_t LHSKnownZero, LHSKnownOne; 741 uint64_t RHSKnownZero, RHSKnownOne; 742 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 743 744 if (LHSKnownZero) { 745 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); 746 // If all of the bits are known zero on the LHS or RHS, the add won't 747 // carry. 748 if ((LHSKnownZero | RHSKnownZero) == ~0U) { 749 Base = N.getOperand(0); 750 Index = N.getOperand(1); 751 return true; 752 } 753 } 754 } 755 756 return false; 757} 758 759/// Returns true if the address N can be represented by a base register plus 760/// a signed 16-bit displacement [r+imm], and if it is not better 761/// represented as reg+reg. 762bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, 763 SDOperand &Base, SelectionDAG &DAG){ 764 // If this can be more profitably realized as r+r, fail. 765 if (SelectAddressRegReg(N, Disp, Base, DAG)) 766 return false; 767 768 if (N.getOpcode() == ISD::ADD) { 769 short imm = 0; 770 if (isIntS16Immediate(N.getOperand(1), imm)) { 771 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 772 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 773 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 774 } else { 775 Base = N.getOperand(0); 776 } 777 return true; // [r+i] 778 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 779 // Match LOAD (ADD (X, Lo(G))). 780 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 781 && "Cannot handle constant offsets yet!"); 782 Disp = N.getOperand(1).getOperand(0); // The global address. 783 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 784 Disp.getOpcode() == ISD::TargetConstantPool || 785 Disp.getOpcode() == ISD::TargetJumpTable); 786 Base = N.getOperand(0); 787 return true; // [&g+r] 788 } 789 } else if (N.getOpcode() == ISD::OR) { 790 short imm = 0; 791 if (isIntS16Immediate(N.getOperand(1), imm)) { 792 // If this is an or of disjoint bitfields, we can codegen this as an add 793 // (for better address arithmetic) if the LHS and RHS of the OR are 794 // provably disjoint. 795 uint64_t LHSKnownZero, LHSKnownOne; 796 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 797 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 798 // If all of the bits are known zero on the LHS or RHS, the add won't 799 // carry. 800 Base = N.getOperand(0); 801 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 802 return true; 803 } 804 } 805 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 806 // Loading from a constant address. 807 808 // If this address fits entirely in a 16-bit sext immediate field, codegen 809 // this as "d, 0" 810 short Imm; 811 if (isIntS16Immediate(CN, Imm)) { 812 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 813 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 814 return true; 815 } 816 817 // Handle 32-bit sext immediates with LIS + addr mode. 818 if (CN->getValueType(0) == MVT::i32 || 819 (int64_t)CN->getValue() == (int)CN->getValue()) { 820 int Addr = (int)CN->getValue(); 821 822 // Otherwise, break this down into an LIS + disp. 823 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 824 825 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 826 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 827 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 828 return true; 829 } 830 } 831 832 Disp = DAG.getTargetConstant(0, getPointerTy()); 833 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 834 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 835 else 836 Base = N; 837 return true; // [r+0] 838} 839 840/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 841/// represented as an indexed [r+r] operation. 842bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, 843 SDOperand &Index, 844 SelectionDAG &DAG) { 845 // Check to see if we can easily represent this as an [r+r] address. This 846 // will fail if it thinks that the address is more profitably represented as 847 // reg+imm, e.g. where imm = 0. 848 if (SelectAddressRegReg(N, Base, Index, DAG)) 849 return true; 850 851 // If the operand is an addition, always emit this as [r+r], since this is 852 // better (for code size, and execution, as the memop does the add for free) 853 // than emitting an explicit add. 854 if (N.getOpcode() == ISD::ADD) { 855 Base = N.getOperand(0); 856 Index = N.getOperand(1); 857 return true; 858 } 859 860 // Otherwise, do it the hard way, using R0 as the base register. 861 Base = DAG.getRegister(PPC::R0, N.getValueType()); 862 Index = N; 863 return true; 864} 865 866/// SelectAddressRegImmShift - Returns true if the address N can be 867/// represented by a base register plus a signed 14-bit displacement 868/// [r+imm*4]. Suitable for use by STD and friends. 869bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, 870 SDOperand &Base, 871 SelectionDAG &DAG) { 872 // If this can be more profitably realized as r+r, fail. 873 if (SelectAddressRegReg(N, Disp, Base, DAG)) 874 return false; 875 876 if (N.getOpcode() == ISD::ADD) { 877 short imm = 0; 878 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 879 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 880 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 881 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 882 } else { 883 Base = N.getOperand(0); 884 } 885 return true; // [r+i] 886 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 887 // Match LOAD (ADD (X, Lo(G))). 888 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 889 && "Cannot handle constant offsets yet!"); 890 Disp = N.getOperand(1).getOperand(0); // The global address. 891 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 892 Disp.getOpcode() == ISD::TargetConstantPool || 893 Disp.getOpcode() == ISD::TargetJumpTable); 894 Base = N.getOperand(0); 895 return true; // [&g+r] 896 } 897 } else if (N.getOpcode() == ISD::OR) { 898 short imm = 0; 899 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 900 // If this is an or of disjoint bitfields, we can codegen this as an add 901 // (for better address arithmetic) if the LHS and RHS of the OR are 902 // provably disjoint. 903 uint64_t LHSKnownZero, LHSKnownOne; 904 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 905 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 906 // If all of the bits are known zero on the LHS or RHS, the add won't 907 // carry. 908 Base = N.getOperand(0); 909 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 910 return true; 911 } 912 } 913 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 914 // Loading from a constant address. Verify low two bits are clear. 915 if ((CN->getValue() & 3) == 0) { 916 // If this address fits entirely in a 14-bit sext immediate field, codegen 917 // this as "d, 0" 918 short Imm; 919 if (isIntS16Immediate(CN, Imm)) { 920 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 921 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 922 return true; 923 } 924 925 // Fold the low-part of 32-bit absolute addresses into addr mode. 926 if (CN->getValueType(0) == MVT::i32 || 927 (int64_t)CN->getValue() == (int)CN->getValue()) { 928 int Addr = (int)CN->getValue(); 929 930 // Otherwise, break this down into an LIS + disp. 931 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 932 933 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 934 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 935 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 936 return true; 937 } 938 } 939 } 940 941 Disp = DAG.getTargetConstant(0, getPointerTy()); 942 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 943 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 944 else 945 Base = N; 946 return true; // [r+0] 947} 948 949 950/// getPreIndexedAddressParts - returns true by value, base pointer and 951/// offset pointer and addressing mode by reference if the node's address 952/// can be legally represented as pre-indexed load / store address. 953bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 954 SDOperand &Offset, 955 ISD::MemIndexedMode &AM, 956 SelectionDAG &DAG) { 957 // Disabled by default for now. 958 if (!EnablePPCPreinc) return false; 959 960 SDOperand Ptr; 961 MVT::ValueType VT; 962 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 963 Ptr = LD->getBasePtr(); 964 VT = LD->getLoadedVT(); 965 966 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 967 ST = ST; 968 Ptr = ST->getBasePtr(); 969 VT = ST->getStoredVT(); 970 } else 971 return false; 972 973 // PowerPC doesn't have preinc load/store instructions for vectors. 974 if (MVT::isVector(VT)) 975 return false; 976 977 // TODO: Check reg+reg first. 978 979 // LDU/STU use reg+imm*4, others use reg+imm. 980 if (VT != MVT::i64) { 981 // reg + imm 982 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 983 return false; 984 } else { 985 // reg + imm * 4. 986 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 987 return false; 988 } 989 990 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 991 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 992 // sext i32 to i64 when addr mode is r+i. 993 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 && 994 LD->getExtensionType() == ISD::SEXTLOAD && 995 isa<ConstantSDNode>(Offset)) 996 return false; 997 } 998 999 AM = ISD::PRE_INC; 1000 return true; 1001} 1002 1003//===----------------------------------------------------------------------===// 1004// LowerOperation implementation 1005//===----------------------------------------------------------------------===// 1006 1007static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 1008 MVT::ValueType PtrVT = Op.getValueType(); 1009 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1010 Constant *C = CP->getConstVal(); 1011 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1012 SDOperand Zero = DAG.getConstant(0, PtrVT); 1013 1014 const TargetMachine &TM = DAG.getTarget(); 1015 1016 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 1017 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 1018 1019 // If this is a non-darwin platform, we don't support non-static relo models 1020 // yet. 1021 if (TM.getRelocationModel() == Reloc::Static || 1022 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1023 // Generate non-pic code that has direct accesses to the constant pool. 1024 // The address of the global is just (hi(&g)+lo(&g)). 1025 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1026 } 1027 1028 if (TM.getRelocationModel() == Reloc::PIC_) { 1029 // With PIC, the first instruction is actually "GR+hi(&G)". 1030 Hi = DAG.getNode(ISD::ADD, PtrVT, 1031 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1032 } 1033 1034 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1035 return Lo; 1036} 1037 1038static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 1039 MVT::ValueType PtrVT = Op.getValueType(); 1040 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1041 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1042 SDOperand Zero = DAG.getConstant(0, PtrVT); 1043 1044 const TargetMachine &TM = DAG.getTarget(); 1045 1046 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 1047 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 1048 1049 // If this is a non-darwin platform, we don't support non-static relo models 1050 // yet. 1051 if (TM.getRelocationModel() == Reloc::Static || 1052 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1053 // Generate non-pic code that has direct accesses to the constant pool. 1054 // The address of the global is just (hi(&g)+lo(&g)). 1055 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1056 } 1057 1058 if (TM.getRelocationModel() == Reloc::PIC_) { 1059 // With PIC, the first instruction is actually "GR+hi(&G)". 1060 Hi = DAG.getNode(ISD::ADD, PtrVT, 1061 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1062 } 1063 1064 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1065 return Lo; 1066} 1067 1068static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 1069 assert(0 && "TLS not implemented for PPC."); 1070} 1071 1072static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 1073 MVT::ValueType PtrVT = Op.getValueType(); 1074 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1075 GlobalValue *GV = GSDN->getGlobal(); 1076 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1077 SDOperand Zero = DAG.getConstant(0, PtrVT); 1078 1079 const TargetMachine &TM = DAG.getTarget(); 1080 1081 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 1082 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1083 1084 // If this is a non-darwin platform, we don't support non-static relo models 1085 // yet. 1086 if (TM.getRelocationModel() == Reloc::Static || 1087 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1088 // Generate non-pic code that has direct accesses to globals. 1089 // The address of the global is just (hi(&g)+lo(&g)). 1090 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1091 } 1092 1093 if (TM.getRelocationModel() == Reloc::PIC_) { 1094 // With PIC, the first instruction is actually "GR+hi(&G)". 1095 Hi = DAG.getNode(ISD::ADD, PtrVT, 1096 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1097 } 1098 1099 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1100 1101 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1102 return Lo; 1103 1104 // If the global is weak or external, we have to go through the lazy 1105 // resolution stub. 1106 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1107} 1108 1109static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 1110 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1111 1112 // If we're comparing for equality to zero, expose the fact that this is 1113 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1114 // fold the new nodes. 1115 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1116 if (C->isNullValue() && CC == ISD::SETEQ) { 1117 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1118 SDOperand Zext = Op.getOperand(0); 1119 if (VT < MVT::i32) { 1120 VT = MVT::i32; 1121 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1122 } 1123 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1124 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1125 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1126 DAG.getConstant(Log2b, MVT::i32)); 1127 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1128 } 1129 // Leave comparisons against 0 and -1 alone for now, since they're usually 1130 // optimized. FIXME: revisit this when we can custom lower all setcc 1131 // optimizations. 1132 if (C->isAllOnesValue() || C->isNullValue()) 1133 return SDOperand(); 1134 } 1135 1136 // If we have an integer seteq/setne, turn it into a compare against zero 1137 // by xor'ing the rhs with the lhs, which is faster than setting a 1138 // condition register, reading it back out, and masking the correct bit. The 1139 // normal approach here uses sub to do this instead of xor. Using xor exposes 1140 // the result to other bit-twiddling opportunities. 1141 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1142 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1143 MVT::ValueType VT = Op.getValueType(); 1144 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1145 Op.getOperand(1)); 1146 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1147 } 1148 return SDOperand(); 1149} 1150 1151static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, 1152 int VarArgsFrameIndex, 1153 int VarArgsStackOffset, 1154 unsigned VarArgsNumGPR, 1155 unsigned VarArgsNumFPR, 1156 const PPCSubtarget &Subtarget) { 1157 1158 assert(0 && "VAARG in ELF32 ABI not implemented yet!"); 1159} 1160 1161static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 1162 int VarArgsFrameIndex, 1163 int VarArgsStackOffset, 1164 unsigned VarArgsNumGPR, 1165 unsigned VarArgsNumFPR, 1166 const PPCSubtarget &Subtarget) { 1167 1168 if (Subtarget.isMachoABI()) { 1169 // vastart just stores the address of the VarArgsFrameIndex slot into the 1170 // memory location argument. 1171 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1172 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1173 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1174 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 1175 SV->getOffset()); 1176 } 1177 1178 // For ELF 32 ABI we follow the layout of the va_list struct. 1179 // We suppose the given va_list is already allocated. 1180 // 1181 // typedef struct { 1182 // char gpr; /* index into the array of 8 GPRs 1183 // * stored in the register save area 1184 // * gpr=0 corresponds to r3, 1185 // * gpr=1 to r4, etc. 1186 // */ 1187 // char fpr; /* index into the array of 8 FPRs 1188 // * stored in the register save area 1189 // * fpr=0 corresponds to f1, 1190 // * fpr=1 to f2, etc. 1191 // */ 1192 // char *overflow_arg_area; 1193 // /* location on stack that holds 1194 // * the next overflow argument 1195 // */ 1196 // char *reg_save_area; 1197 // /* where r3:r10 and f1:f8 (if saved) 1198 // * are stored 1199 // */ 1200 // } va_list[1]; 1201 1202 1203 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); 1204 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); 1205 1206 1207 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1208 1209 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1210 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1211 1212 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, 1213 PtrVT); 1214 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1, 1215 PtrVT); 1216 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT); 1217 1218 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1219 1220 // Store first byte : number of int regs 1221 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, 1222 Op.getOperand(1), SV->getValue(), 1223 SV->getOffset()); 1224 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), 1225 ConstFPROffset); 1226 1227 // Store second byte : number of float regs 1228 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, 1229 SV->getValue(), SV->getOffset()); 1230 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); 1231 1232 // Store second word : arguments given on stack 1233 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr, 1234 SV->getValue(), SV->getOffset()); 1235 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); 1236 1237 // Store third word : arguments given in registers 1238 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(), 1239 SV->getOffset()); 1240 1241} 1242 1243#include "PPCGenCallingConv.inc" 1244 1245/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1246/// depending on which subtarget is selected. 1247static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1248 if (Subtarget.isMachoABI()) { 1249 static const unsigned FPR[] = { 1250 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1251 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1252 }; 1253 return FPR; 1254 } 1255 1256 1257 static const unsigned FPR[] = { 1258 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1259 PPC::F8 1260 }; 1261 return FPR; 1262} 1263 1264static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 1265 int &VarArgsFrameIndex, 1266 int &VarArgsStackOffset, 1267 unsigned &VarArgsNumGPR, 1268 unsigned &VarArgsNumFPR, 1269 const PPCSubtarget &Subtarget) { 1270 // TODO: add description of PPC stack frame format, or at least some docs. 1271 // 1272 MachineFunction &MF = DAG.getMachineFunction(); 1273 MachineFrameInfo *MFI = MF.getFrameInfo(); 1274 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1275 SmallVector<SDOperand, 8> ArgValues; 1276 SDOperand Root = Op.getOperand(0); 1277 1278 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1279 bool isPPC64 = PtrVT == MVT::i64; 1280 bool isMachoABI = Subtarget.isMachoABI(); 1281 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1282 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1283 1284 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1285 1286 static const unsigned GPR_32[] = { // 32-bit registers. 1287 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1288 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1289 }; 1290 static const unsigned GPR_64[] = { // 64-bit registers. 1291 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1292 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1293 }; 1294 1295 static const unsigned *FPR = GetFPR(Subtarget); 1296 1297 static const unsigned VR[] = { 1298 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1299 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1300 }; 1301 1302 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1303 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; 1304 const unsigned Num_VR_Regs = array_lengthof( VR); 1305 1306 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1307 1308 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1309 1310 // Add DAG nodes to load the arguments or copy them out of registers. On 1311 // entry to a function on PPC, the arguments start after the linkage area, 1312 // although the first ones are often in registers. 1313 // 1314 // In the ELF 32 ABI, GPRs and stack are double word align: an argument 1315 // represented with two words (long long or double) must be copied to an 1316 // even GPR_idx value or to an even ArgOffset value. 1317 1318 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1319 SDOperand ArgVal; 1320 bool needsLoad = false; 1321 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 1322 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 1323 unsigned ArgSize = ObjSize; 1324 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue(); 1325 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1326 // See if next argument requires stack alignment in ELF 1327 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) && 1328 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) && 1329 (!(Flags & AlignFlag))); 1330 1331 unsigned CurArgOffset = ArgOffset; 1332 switch (ObjectVT) { 1333 default: assert(0 && "Unhandled argument type!"); 1334 case MVT::i32: 1335 // Double word align in ELF 1336 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1337 if (GPR_idx != Num_GPR_Regs) { 1338 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1339 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1340 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1341 ++GPR_idx; 1342 } else { 1343 needsLoad = true; 1344 ArgSize = PtrByteSize; 1345 } 1346 // Stack align in ELF 1347 if (needsLoad && Expand && isELF32_ABI) 1348 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1349 // All int arguments reserve stack space in Macho ABI. 1350 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1351 break; 1352 1353 case MVT::i64: // PPC64 1354 if (GPR_idx != Num_GPR_Regs) { 1355 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1356 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1357 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1358 ++GPR_idx; 1359 } else { 1360 needsLoad = true; 1361 } 1362 // All int arguments reserve stack space in Macho ABI. 1363 if (isMachoABI || needsLoad) ArgOffset += 8; 1364 break; 1365 1366 case MVT::f32: 1367 case MVT::f64: 1368 // Every 4 bytes of argument space consumes one of the GPRs available for 1369 // argument passing. 1370 if (GPR_idx != Num_GPR_Regs && isMachoABI) { 1371 ++GPR_idx; 1372 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1373 ++GPR_idx; 1374 } 1375 if (FPR_idx != Num_FPR_Regs) { 1376 unsigned VReg; 1377 if (ObjectVT == MVT::f32) 1378 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass); 1379 else 1380 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1381 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1382 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1383 ++FPR_idx; 1384 } else { 1385 needsLoad = true; 1386 } 1387 1388 // Stack align in ELF 1389 if (needsLoad && Expand && isELF32_ABI) 1390 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1391 // All FP arguments reserve stack space in Macho ABI. 1392 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1393 break; 1394 case MVT::v4f32: 1395 case MVT::v4i32: 1396 case MVT::v8i16: 1397 case MVT::v16i8: 1398 // Note that vector arguments in registers don't reserve stack space. 1399 if (VR_idx != Num_VR_Regs) { 1400 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); 1401 RegInfo.addLiveIn(VR[VR_idx], VReg); 1402 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1403 ++VR_idx; 1404 } else { 1405 // This should be simple, but requires getting 16-byte aligned stack 1406 // values. 1407 assert(0 && "Loading VR argument not implemented yet!"); 1408 needsLoad = true; 1409 } 1410 break; 1411 } 1412 1413 // We need to load the argument to a virtual register if we determined above 1414 // that we ran out of physical registers of the appropriate type 1415 if (needsLoad) { 1416 // If the argument is actually used, emit a load from the right stack 1417 // slot. 1418 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 1419 int FI = MFI->CreateFixedObject(ObjSize, 1420 CurArgOffset + (ArgSize - ObjSize)); 1421 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1422 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1423 } else { 1424 // Don't emit a dead load. 1425 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); 1426 } 1427 } 1428 1429 ArgValues.push_back(ArgVal); 1430 } 1431 1432 // If the function takes variable number of arguments, make a frame index for 1433 // the start of the first vararg value... for expansion of llvm.va_start. 1434 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1435 if (isVarArg) { 1436 1437 int depth; 1438 if (isELF32_ABI) { 1439 VarArgsNumGPR = GPR_idx; 1440 VarArgsNumFPR = FPR_idx; 1441 1442 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame 1443 // pointer. 1444 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 + 1445 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 + 1446 MVT::getSizeInBits(PtrVT)/8); 1447 1448 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1449 ArgOffset); 1450 1451 } 1452 else 1453 depth = ArgOffset; 1454 1455 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1456 depth); 1457 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1458 1459 SmallVector<SDOperand, 8> MemOps; 1460 1461 // In ELF 32 ABI, the fixed integer arguments of a variadic function are 1462 // stored to the VarArgsFrameIndex on the stack. 1463 if (isELF32_ABI) { 1464 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { 1465 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT); 1466 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1467 MemOps.push_back(Store); 1468 // Increment the address by four for the next argument to store 1469 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1470 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1471 } 1472 } 1473 1474 // If this function is vararg, store any remaining integer argument regs 1475 // to their spots on the stack so that they may be loaded by deferencing the 1476 // result of va_next. 1477 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1478 unsigned VReg; 1479 if (isPPC64) 1480 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1481 else 1482 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1483 1484 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1485 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1486 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1487 MemOps.push_back(Store); 1488 // Increment the address by four for the next argument to store 1489 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1490 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1491 } 1492 1493 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex 1494 // on the stack. 1495 if (isELF32_ABI) { 1496 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { 1497 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); 1498 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1499 MemOps.push_back(Store); 1500 // Increment the address by eight for the next argument to store 1501 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1502 PtrVT); 1503 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1504 } 1505 1506 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { 1507 unsigned VReg; 1508 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1509 1510 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1511 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); 1512 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1513 MemOps.push_back(Store); 1514 // Increment the address by eight for the next argument to store 1515 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1516 PtrVT); 1517 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1518 } 1519 } 1520 1521 if (!MemOps.empty()) 1522 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1523 } 1524 1525 ArgValues.push_back(Root); 1526 1527 // Return the new list of results. 1528 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1529 Op.Val->value_end()); 1530 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1531} 1532 1533/// isCallCompatibleAddress - Return the immediate to use if the specified 1534/// 32-bit value is representable in the immediate field of a BxA instruction. 1535static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 1536 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1537 if (!C) return 0; 1538 1539 int Addr = C->getValue(); 1540 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1541 (Addr << 6 >> 6) != Addr) 1542 return 0; // Top 6 bits have to be sext of immediate. 1543 1544 return DAG.getConstant((int)C->getValue() >> 2, 1545 DAG.getTargetLoweringInfo().getPointerTy()).Val; 1546} 1547 1548 1549static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, 1550 const PPCSubtarget &Subtarget) { 1551 SDOperand Chain = Op.getOperand(0); 1552 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1553 SDOperand Callee = Op.getOperand(4); 1554 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1555 1556 bool isMachoABI = Subtarget.isMachoABI(); 1557 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1558 1559 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1560 bool isPPC64 = PtrVT == MVT::i64; 1561 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1562 1563 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1564 // SelectExpr to use to put the arguments in the appropriate registers. 1565 std::vector<SDOperand> args_to_use; 1566 1567 // Count how many bytes are to be pushed on the stack, including the linkage 1568 // area, and parameter passing area. We start with 24/48 bytes, which is 1569 // prereserved space for [SP][CR][LR][3 x unused]. 1570 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1571 1572 // Add up all the space actually used. 1573 for (unsigned i = 0; i != NumOps; ++i) { 1574 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 1575 ArgSize = std::max(ArgSize, PtrByteSize); 1576 NumBytes += ArgSize; 1577 } 1578 1579 // The prolog code of the callee may store up to 8 GPR argument registers to 1580 // the stack, allowing va_start to index over them in memory if its varargs. 1581 // Because we cannot tell if this is needed on the caller side, we have to 1582 // conservatively assume that it is needed. As such, make sure we have at 1583 // least enough stack space for the caller to store the 8 GPRs. 1584 NumBytes = std::max(NumBytes, 1585 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1586 1587 // Adjust the stack pointer for the new arguments... 1588 // These operations are automatically eliminated by the prolog/epilog pass 1589 Chain = DAG.getCALLSEQ_START(Chain, 1590 DAG.getConstant(NumBytes, PtrVT)); 1591 1592 // Set up a copy of the stack pointer for use loading and storing any 1593 // arguments that may not fit in the registers available for argument 1594 // passing. 1595 SDOperand StackPtr; 1596 if (isPPC64) 1597 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 1598 else 1599 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1600 1601 // Figure out which arguments are going to go in registers, and which in 1602 // memory. Also, if this is a vararg function, floating point operations 1603 // must be stored to our stack, and loaded into integer regs as well, if 1604 // any integer regs are available for argument passing. 1605 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1606 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1607 1608 static const unsigned GPR_32[] = { // 32-bit registers. 1609 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1610 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1611 }; 1612 static const unsigned GPR_64[] = { // 64-bit registers. 1613 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1614 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1615 }; 1616 static const unsigned *FPR = GetFPR(Subtarget); 1617 1618 static const unsigned VR[] = { 1619 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1620 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1621 }; 1622 const unsigned NumGPRs = array_lengthof(GPR_32); 1623 const unsigned NumFPRs = isMachoABI ? 13 : 8; 1624 const unsigned NumVRs = array_lengthof( VR); 1625 1626 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1627 1628 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1629 SmallVector<SDOperand, 8> MemOpChains; 1630 for (unsigned i = 0; i != NumOps; ++i) { 1631 bool inMem = false; 1632 SDOperand Arg = Op.getOperand(5+2*i); 1633 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1634 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1635 // See if next argument requires stack alignment in ELF 1636 unsigned next = 5+2*(i+1)+1; 1637 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) && 1638 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) && 1639 (!(Flags & AlignFlag))); 1640 1641 // PtrOff will be used to store the current argument to the stack if a 1642 // register cannot be found for it. 1643 SDOperand PtrOff; 1644 1645 // Stack align in ELF 32 1646 if (isELF32_ABI && Expand) 1647 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, 1648 StackPtr.getValueType()); 1649 else 1650 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1651 1652 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1653 1654 // On PPC64, promote integers to 64-bit values. 1655 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1656 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1657 1658 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1659 } 1660 1661 switch (Arg.getValueType()) { 1662 default: assert(0 && "Unexpected ValueType for argument!"); 1663 case MVT::i32: 1664 case MVT::i64: 1665 // Double word align in ELF 1666 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2); 1667 if (GPR_idx != NumGPRs) { 1668 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1669 } else { 1670 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1671 inMem = true; 1672 } 1673 if (inMem || isMachoABI) { 1674 // Stack align in ELF 1675 if (isELF32_ABI && Expand) 1676 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1677 1678 ArgOffset += PtrByteSize; 1679 } 1680 break; 1681 case MVT::f32: 1682 case MVT::f64: 1683 if (isVarArg) { 1684 // Float varargs need to be promoted to double. 1685 if (Arg.getValueType() == MVT::f32) 1686 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); 1687 } 1688 1689 if (FPR_idx != NumFPRs) { 1690 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1691 1692 if (isVarArg) { 1693 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1694 MemOpChains.push_back(Store); 1695 1696 // Float varargs are always shadowed in available integer registers 1697 if (GPR_idx != NumGPRs) { 1698 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1699 MemOpChains.push_back(Load.getValue(1)); 1700 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1701 Load)); 1702 } 1703 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 1704 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1705 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1706 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1707 MemOpChains.push_back(Load.getValue(1)); 1708 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1709 Load)); 1710 } 1711 } else { 1712 // If we have any FPRs remaining, we may also have GPRs remaining. 1713 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1714 // GPRs. 1715 if (isMachoABI) { 1716 if (GPR_idx != NumGPRs) 1717 ++GPR_idx; 1718 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 1719 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 1720 ++GPR_idx; 1721 } 1722 } 1723 } else { 1724 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1725 inMem = true; 1726 } 1727 if (inMem || isMachoABI) { 1728 // Stack align in ELF 1729 if (isELF32_ABI && Expand) 1730 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1731 if (isPPC64) 1732 ArgOffset += 8; 1733 else 1734 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1735 } 1736 break; 1737 case MVT::v4f32: 1738 case MVT::v4i32: 1739 case MVT::v8i16: 1740 case MVT::v16i8: 1741 assert(!isVarArg && "Don't support passing vectors to varargs yet!"); 1742 assert(VR_idx != NumVRs && 1743 "Don't support passing more than 12 vector args yet!"); 1744 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 1745 break; 1746 } 1747 } 1748 if (!MemOpChains.empty()) 1749 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1750 &MemOpChains[0], MemOpChains.size()); 1751 1752 // Build a sequence of copy-to-reg nodes chained together with token chain 1753 // and flag operands which copy the outgoing args into the appropriate regs. 1754 SDOperand InFlag; 1755 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1756 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1757 InFlag); 1758 InFlag = Chain.getValue(1); 1759 } 1760 1761 // With the ELF 32 ABI, set CR6 to true if this is a vararg call. 1762 if (isVarArg && isELF32_ABI) { 1763 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0); 1764 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag); 1765 InFlag = Chain.getValue(1); 1766 } 1767 1768 std::vector<MVT::ValueType> NodeTys; 1769 NodeTys.push_back(MVT::Other); // Returns a chain 1770 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1771 1772 SmallVector<SDOperand, 8> Ops; 1773 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 1774 1775 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1776 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1777 // node so that legalize doesn't hack it. 1778 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1779 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 1780 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1781 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 1782 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 1783 // If this is an absolute destination address, use the munged value. 1784 Callee = SDOperand(Dest, 0); 1785 else { 1786 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 1787 // to do the call, we can't use PPCISD::CALL. 1788 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 1789 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 1790 InFlag = Chain.getValue(1); 1791 1792 // Copy the callee address into R12 on darwin. 1793 if (isMachoABI) { 1794 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); 1795 InFlag = Chain.getValue(1); 1796 } 1797 1798 NodeTys.clear(); 1799 NodeTys.push_back(MVT::Other); 1800 NodeTys.push_back(MVT::Flag); 1801 Ops.push_back(Chain); 1802 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 1803 Callee.Val = 0; 1804 } 1805 1806 // If this is a direct call, pass the chain and the callee. 1807 if (Callee.Val) { 1808 Ops.push_back(Chain); 1809 Ops.push_back(Callee); 1810 } 1811 1812 // Add argument registers to the end of the list so that they are known live 1813 // into the call. 1814 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1815 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1816 RegsToPass[i].second.getValueType())); 1817 1818 if (InFlag.Val) 1819 Ops.push_back(InFlag); 1820 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 1821 InFlag = Chain.getValue(1); 1822 1823 Chain = DAG.getCALLSEQ_END(Chain, 1824 DAG.getConstant(NumBytes, PtrVT), 1825 DAG.getConstant(0, PtrVT), 1826 InFlag); 1827 if (Op.Val->getValueType(0) != MVT::Other) 1828 InFlag = Chain.getValue(1); 1829 1830 SDOperand ResultVals[3]; 1831 unsigned NumResults = 0; 1832 NodeTys.clear(); 1833 1834 // If the call has results, copy the values out of the ret val registers. 1835 switch (Op.Val->getValueType(0)) { 1836 default: assert(0 && "Unexpected ret value!"); 1837 case MVT::Other: break; 1838 case MVT::i32: 1839 if (Op.Val->getValueType(1) == MVT::i32) { 1840 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1841 ResultVals[0] = Chain.getValue(0); 1842 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, 1843 Chain.getValue(2)).getValue(1); 1844 ResultVals[1] = Chain.getValue(0); 1845 NumResults = 2; 1846 NodeTys.push_back(MVT::i32); 1847 } else { 1848 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1849 ResultVals[0] = Chain.getValue(0); 1850 NumResults = 1; 1851 } 1852 NodeTys.push_back(MVT::i32); 1853 break; 1854 case MVT::i64: 1855 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 1856 ResultVals[0] = Chain.getValue(0); 1857 NumResults = 1; 1858 NodeTys.push_back(MVT::i64); 1859 break; 1860 case MVT::f64: 1861 if (Op.Val->getValueType(1) == MVT::f64) { 1862 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1); 1863 ResultVals[0] = Chain.getValue(0); 1864 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64, 1865 Chain.getValue(2)).getValue(1); 1866 ResultVals[1] = Chain.getValue(0); 1867 NumResults = 2; 1868 NodeTys.push_back(MVT::f64); 1869 NodeTys.push_back(MVT::f64); 1870 break; 1871 } 1872 // else fall through 1873 case MVT::f32: 1874 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 1875 InFlag).getValue(1); 1876 ResultVals[0] = Chain.getValue(0); 1877 NumResults = 1; 1878 NodeTys.push_back(Op.Val->getValueType(0)); 1879 break; 1880 case MVT::v4f32: 1881 case MVT::v4i32: 1882 case MVT::v8i16: 1883 case MVT::v16i8: 1884 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 1885 InFlag).getValue(1); 1886 ResultVals[0] = Chain.getValue(0); 1887 NumResults = 1; 1888 NodeTys.push_back(Op.Val->getValueType(0)); 1889 break; 1890 } 1891 1892 NodeTys.push_back(MVT::Other); 1893 1894 // If the function returns void, just return the chain. 1895 if (NumResults == 0) 1896 return Chain; 1897 1898 // Otherwise, merge everything together with a MERGE_VALUES node. 1899 ResultVals[NumResults++] = Chain; 1900 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1901 ResultVals, NumResults); 1902 return Res.getValue(Op.ResNo); 1903} 1904 1905static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { 1906 SmallVector<CCValAssign, 16> RVLocs; 1907 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 1908 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1909 CCState CCInfo(CC, isVarArg, TM, RVLocs); 1910 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC); 1911 1912 // If this is the first return lowered for this function, add the regs to the 1913 // liveout set for the function. 1914 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1915 for (unsigned i = 0; i != RVLocs.size(); ++i) 1916 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1917 } 1918 1919 SDOperand Chain = Op.getOperand(0); 1920 SDOperand Flag; 1921 1922 // Copy the result values into the output registers. 1923 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1924 CCValAssign &VA = RVLocs[i]; 1925 assert(VA.isRegLoc() && "Can only return in registers!"); 1926 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 1927 Flag = Chain.getValue(1); 1928 } 1929 1930 if (Flag.Val) 1931 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); 1932 else 1933 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); 1934} 1935 1936static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, 1937 const PPCSubtarget &Subtarget) { 1938 // When we pop the dynamic allocation we need to restore the SP link. 1939 1940 // Get the corect type for pointers. 1941 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1942 1943 // Construct the stack pointer operand. 1944 bool IsPPC64 = Subtarget.isPPC64(); 1945 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 1946 SDOperand StackPtr = DAG.getRegister(SP, PtrVT); 1947 1948 // Get the operands for the STACKRESTORE. 1949 SDOperand Chain = Op.getOperand(0); 1950 SDOperand SaveSP = Op.getOperand(1); 1951 1952 // Load the old link SP. 1953 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 1954 1955 // Restore the stack pointer. 1956 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 1957 1958 // Store the old link SP. 1959 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 1960} 1961 1962static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, 1963 const PPCSubtarget &Subtarget) { 1964 MachineFunction &MF = DAG.getMachineFunction(); 1965 bool IsPPC64 = Subtarget.isPPC64(); 1966 bool isMachoABI = Subtarget.isMachoABI(); 1967 1968 // Get current frame pointer save index. The users of this index will be 1969 // primarily DYNALLOC instructions. 1970 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1971 int FPSI = FI->getFramePointerSaveIndex(); 1972 1973 // If the frame pointer save index hasn't been defined yet. 1974 if (!FPSI) { 1975 // Find out what the fix offset of the frame pointer save area. 1976 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 1977 1978 // Allocate the frame index for frame pointer save area. 1979 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 1980 // Save the result. 1981 FI->setFramePointerSaveIndex(FPSI); 1982 } 1983 1984 // Get the inputs. 1985 SDOperand Chain = Op.getOperand(0); 1986 SDOperand Size = Op.getOperand(1); 1987 1988 // Get the corect type for pointers. 1989 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1990 // Negate the size. 1991 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, 1992 DAG.getConstant(0, PtrVT), Size); 1993 // Construct a node for the frame pointer save index. 1994 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); 1995 // Build a DYNALLOC node. 1996 SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; 1997 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 1998 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 1999} 2000 2001 2002/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 2003/// possible. 2004static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 2005 // Not FP? Not a fsel. 2006 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 2007 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 2008 return SDOperand(); 2009 2010 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2011 2012 // Cannot handle SETEQ/SETNE. 2013 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 2014 2015 MVT::ValueType ResVT = Op.getValueType(); 2016 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 2017 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2018 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 2019 2020 // If the RHS of the comparison is a 0.0, we don't need to do the 2021 // subtraction at all. 2022 if (isFloatingPointZero(RHS)) 2023 switch (CC) { 2024 default: break; // SETUO etc aren't handled by fsel. 2025 case ISD::SETULT: 2026 case ISD::SETOLT: 2027 case ISD::SETLT: 2028 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2029 case ISD::SETUGE: 2030 case ISD::SETOGE: 2031 case ISD::SETGE: 2032 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2033 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2034 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 2035 case ISD::SETUGT: 2036 case ISD::SETOGT: 2037 case ISD::SETGT: 2038 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2039 case ISD::SETULE: 2040 case ISD::SETOLE: 2041 case ISD::SETLE: 2042 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2043 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2044 return DAG.getNode(PPCISD::FSEL, ResVT, 2045 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 2046 } 2047 2048 SDOperand Cmp; 2049 switch (CC) { 2050 default: break; // SETUO etc aren't handled by fsel. 2051 case ISD::SETULT: 2052 case ISD::SETOLT: 2053 case ISD::SETLT: 2054 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2055 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2056 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2057 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2058 case ISD::SETUGE: 2059 case ISD::SETOGE: 2060 case ISD::SETGE: 2061 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2062 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2063 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2064 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2065 case ISD::SETUGT: 2066 case ISD::SETOGT: 2067 case ISD::SETGT: 2068 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2069 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2070 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2071 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2072 case ISD::SETULE: 2073 case ISD::SETOLE: 2074 case ISD::SETLE: 2075 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2076 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2077 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2078 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2079 } 2080 return SDOperand(); 2081} 2082 2083// FIXME: Split this code up when LegalizeDAGTypes lands. 2084static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 2085 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 2086 SDOperand Src = Op.getOperand(0); 2087 if (Src.getValueType() == MVT::f32) 2088 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 2089 2090 SDOperand Tmp; 2091 switch (Op.getValueType()) { 2092 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 2093 case MVT::i32: 2094 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 2095 break; 2096 case MVT::i64: 2097 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 2098 break; 2099 } 2100 2101 // Convert the FP value to an int value through memory. 2102 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64); 2103 2104 // Emit a store to the stack slot. 2105 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); 2106 2107 // Result is a load from the stack slot. If loading 4 bytes, make sure to 2108 // add in a bias. 2109 if (Op.getValueType() == MVT::i32) 2110 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, 2111 DAG.getConstant(4, FIPtr.getValueType())); 2112 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); 2113} 2114 2115static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) { 2116 assert(Op.getValueType() == MVT::ppcf128); 2117 SDNode *Node = Op.Val; 2118 assert(Node->getOperand(0).getValueType() == MVT::ppcf128); 2119 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR); 2120 SDOperand Lo = Node->getOperand(0).Val->getOperand(0); 2121 SDOperand Hi = Node->getOperand(0).Val->getOperand(1); 2122 2123 // This sequence changes FPSCR to do round-to-zero, adds the two halves 2124 // of the long double, and puts FPSCR back the way it was. We do not 2125 // actually model FPSCR. 2126 std::vector<MVT::ValueType> NodeTys; 2127 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg; 2128 2129 NodeTys.push_back(MVT::f64); // Return register 2130 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 2131 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 2132 MFFSreg = Result.getValue(0); 2133 InFlag = Result.getValue(1); 2134 2135 NodeTys.clear(); 2136 NodeTys.push_back(MVT::Flag); // Returns a flag 2137 Ops[0] = DAG.getConstant(31, MVT::i32); 2138 Ops[1] = InFlag; 2139 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); 2140 InFlag = Result.getValue(0); 2141 2142 NodeTys.clear(); 2143 NodeTys.push_back(MVT::Flag); // Returns a flag 2144 Ops[0] = DAG.getConstant(30, MVT::i32); 2145 Ops[1] = InFlag; 2146 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); 2147 InFlag = Result.getValue(0); 2148 2149 NodeTys.clear(); 2150 NodeTys.push_back(MVT::f64); // result of add 2151 NodeTys.push_back(MVT::Flag); // Returns a flag 2152 Ops[0] = Lo; 2153 Ops[1] = Hi; 2154 Ops[2] = InFlag; 2155 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); 2156 FPreg = Result.getValue(0); 2157 InFlag = Result.getValue(1); 2158 2159 NodeTys.clear(); 2160 NodeTys.push_back(MVT::f64); 2161 Ops[0] = DAG.getConstant(1, MVT::i32); 2162 Ops[1] = MFFSreg; 2163 Ops[2] = FPreg; 2164 Ops[3] = InFlag; 2165 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); 2166 FPreg = Result.getValue(0); 2167 2168 // We know the low half is about to be thrown away, so just use something 2169 // convenient. 2170 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); 2171} 2172 2173static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 2174 if (Op.getOperand(0).getValueType() == MVT::i64) { 2175 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 2176 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 2177 if (Op.getValueType() == MVT::f32) 2178 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2179 return FP; 2180 } 2181 2182 assert(Op.getOperand(0).getValueType() == MVT::i32 && 2183 "Unhandled SINT_TO_FP type in custom expander!"); 2184 // Since we only generate this in 64-bit mode, we can take advantage of 2185 // 64-bit registers. In particular, sign extend the input value into the 2186 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 2187 // then lfd it and fcfid it. 2188 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2189 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 2190 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2191 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2192 2193 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 2194 Op.getOperand(0)); 2195 2196 // STD the extended value into the stack slot. 2197 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 2198 DAG.getEntryNode(), Ext64, FIdx, 2199 DAG.getSrcValue(NULL)); 2200 // Load the value as a double. 2201 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 2202 2203 // FCFID it and return it. 2204 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 2205 if (Op.getValueType() == MVT::f32) 2206 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2207 return FP; 2208} 2209 2210static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2211 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2212 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 2213 2214 // Expand into a bunch of logical ops. Note that these ops 2215 // depend on the PPC behavior for oversized shift amounts. 2216 SDOperand Lo = Op.getOperand(0); 2217 SDOperand Hi = Op.getOperand(1); 2218 SDOperand Amt = Op.getOperand(2); 2219 2220 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2221 DAG.getConstant(32, MVT::i32), Amt); 2222 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 2223 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 2224 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2225 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2226 DAG.getConstant(-32U, MVT::i32)); 2227 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 2228 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2229 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 2230 SDOperand OutOps[] = { OutLo, OutHi }; 2231 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2232 OutOps, 2); 2233} 2234 2235static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2236 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2237 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); 2238 2239 // Otherwise, expand into a bunch of logical ops. Note that these ops 2240 // depend on the PPC behavior for oversized shift amounts. 2241 SDOperand Lo = Op.getOperand(0); 2242 SDOperand Hi = Op.getOperand(1); 2243 SDOperand Amt = Op.getOperand(2); 2244 2245 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2246 DAG.getConstant(32, MVT::i32), Amt); 2247 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2248 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2249 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2250 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2251 DAG.getConstant(-32U, MVT::i32)); 2252 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 2253 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2254 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 2255 SDOperand OutOps[] = { OutLo, OutHi }; 2256 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2257 OutOps, 2); 2258} 2259 2260static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 2261 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2262 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 2263 2264 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 2265 SDOperand Lo = Op.getOperand(0); 2266 SDOperand Hi = Op.getOperand(1); 2267 SDOperand Amt = Op.getOperand(2); 2268 2269 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2270 DAG.getConstant(32, MVT::i32), Amt); 2271 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2272 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2273 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2274 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2275 DAG.getConstant(-32U, MVT::i32)); 2276 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 2277 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 2278 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 2279 Tmp4, Tmp6, ISD::SETLE); 2280 SDOperand OutOps[] = { OutLo, OutHi }; 2281 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2282 OutOps, 2); 2283} 2284 2285//===----------------------------------------------------------------------===// 2286// Vector related lowering. 2287// 2288 2289// If this is a vector of constants or undefs, get the bits. A bit in 2290// UndefBits is set if the corresponding element of the vector is an 2291// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2292// zero. Return true if this is not an array of constants, false if it is. 2293// 2294static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 2295 uint64_t UndefBits[2]) { 2296 // Start with zero'd results. 2297 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 2298 2299 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 2300 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 2301 SDOperand OpVal = BV->getOperand(i); 2302 2303 unsigned PartNo = i >= e/2; // In the upper 128 bits? 2304 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 2305 2306 uint64_t EltBits = 0; 2307 if (OpVal.getOpcode() == ISD::UNDEF) { 2308 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 2309 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 2310 continue; 2311 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 2312 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 2313 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 2314 assert(CN->getValueType(0) == MVT::f32 && 2315 "Only one legal FP vector type!"); 2316 EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); 2317 } else { 2318 // Nonconstant element. 2319 return true; 2320 } 2321 2322 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 2323 } 2324 2325 //printf("%llx %llx %llx %llx\n", 2326 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 2327 return false; 2328} 2329 2330// If this is a splat (repetition) of a value across the whole vector, return 2331// the smallest size that splats it. For example, "0x01010101010101..." is a 2332// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2333// SplatSize = 1 byte. 2334static bool isConstantSplat(const uint64_t Bits128[2], 2335 const uint64_t Undef128[2], 2336 unsigned &SplatBits, unsigned &SplatUndef, 2337 unsigned &SplatSize) { 2338 2339 // Don't let undefs prevent splats from matching. See if the top 64-bits are 2340 // the same as the lower 64-bits, ignoring undefs. 2341 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 2342 return false; // Can't be a splat if two pieces don't match. 2343 2344 uint64_t Bits64 = Bits128[0] | Bits128[1]; 2345 uint64_t Undef64 = Undef128[0] & Undef128[1]; 2346 2347 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 2348 // undefs. 2349 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 2350 return false; // Can't be a splat if two pieces don't match. 2351 2352 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 2353 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 2354 2355 // If the top 16-bits are different than the lower 16-bits, ignoring 2356 // undefs, we have an i32 splat. 2357 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 2358 SplatBits = Bits32; 2359 SplatUndef = Undef32; 2360 SplatSize = 4; 2361 return true; 2362 } 2363 2364 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 2365 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 2366 2367 // If the top 8-bits are different than the lower 8-bits, ignoring 2368 // undefs, we have an i16 splat. 2369 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 2370 SplatBits = Bits16; 2371 SplatUndef = Undef16; 2372 SplatSize = 2; 2373 return true; 2374 } 2375 2376 // Otherwise, we have an 8-bit splat. 2377 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 2378 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 2379 SplatSize = 1; 2380 return true; 2381} 2382 2383/// BuildSplatI - Build a canonical splati of Val with an element size of 2384/// SplatSize. Cast the result to VT. 2385static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 2386 SelectionDAG &DAG) { 2387 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 2388 2389 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 2390 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 2391 }; 2392 2393 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 2394 2395 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 2396 if (Val == -1) 2397 SplatSize = 1; 2398 2399 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 2400 2401 // Build a canonical splat for this value. 2402 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT)); 2403 SmallVector<SDOperand, 8> Ops; 2404 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 2405 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 2406 &Ops[0], Ops.size()); 2407 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 2408} 2409 2410/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 2411/// specified intrinsic ID. 2412static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 2413 SelectionDAG &DAG, 2414 MVT::ValueType DestVT = MVT::Other) { 2415 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 2416 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2417 DAG.getConstant(IID, MVT::i32), LHS, RHS); 2418} 2419 2420/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 2421/// specified intrinsic ID. 2422static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 2423 SDOperand Op2, SelectionDAG &DAG, 2424 MVT::ValueType DestVT = MVT::Other) { 2425 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 2426 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2427 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 2428} 2429 2430 2431/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 2432/// amount. The result has the specified value type. 2433static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 2434 MVT::ValueType VT, SelectionDAG &DAG) { 2435 // Force LHS/RHS to be the right type. 2436 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 2437 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 2438 2439 SDOperand Ops[16]; 2440 for (unsigned i = 0; i != 16; ++i) 2441 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 2442 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 2443 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 2444 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 2445} 2446 2447// If this is a case we can't handle, return null and let the default 2448// expansion code take care of it. If we CAN select this case, and if it 2449// selects to a single instruction, return Op. Otherwise, if we can codegen 2450// this case more efficiently than a constant pool load, lower it to the 2451// sequence of ops that should be used. 2452static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2453 // If this is a vector of constants or undefs, get the bits. A bit in 2454 // UndefBits is set if the corresponding element of the vector is an 2455 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2456 // zero. 2457 uint64_t VectorBits[2]; 2458 uint64_t UndefBits[2]; 2459 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 2460 return SDOperand(); // Not a constant vector. 2461 2462 // If this is a splat (repetition) of a value across the whole vector, return 2463 // the smallest size that splats it. For example, "0x01010101010101..." is a 2464 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2465 // SplatSize = 1 byte. 2466 unsigned SplatBits, SplatUndef, SplatSize; 2467 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 2468 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 2469 2470 // First, handle single instruction cases. 2471 2472 // All zeros? 2473 if (SplatBits == 0) { 2474 // Canonicalize all zero vectors to be v4i32. 2475 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 2476 SDOperand Z = DAG.getConstant(0, MVT::i32); 2477 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 2478 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 2479 } 2480 return Op; 2481 } 2482 2483 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 2484 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 2485 if (SextVal >= -16 && SextVal <= 15) 2486 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 2487 2488 2489 // Two instruction sequences. 2490 2491 // If this value is in the range [-32,30] and is even, use: 2492 // tmp = VSPLTI[bhw], result = add tmp, tmp 2493 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 2494 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 2495 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 2496 } 2497 2498 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 2499 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 2500 // for fneg/fabs. 2501 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 2502 // Make -1 and vspltisw -1: 2503 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 2504 2505 // Make the VSLW intrinsic, computing 0x8000_0000. 2506 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 2507 OnesV, DAG); 2508 2509 // xor by OnesV to invert it. 2510 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 2511 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2512 } 2513 2514 // Check to see if this is a wide variety of vsplti*, binop self cases. 2515 unsigned SplatBitSize = SplatSize*8; 2516 static const signed char SplatCsts[] = { 2517 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 2518 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 2519 }; 2520 2521 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 2522 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 2523 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 2524 int i = SplatCsts[idx]; 2525 2526 // Figure out what shift amount will be used by altivec if shifted by i in 2527 // this splat size. 2528 unsigned TypeShiftAmt = i & (SplatBitSize-1); 2529 2530 // vsplti + shl self. 2531 if (SextVal == (i << (int)TypeShiftAmt)) { 2532 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2533 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2534 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 2535 Intrinsic::ppc_altivec_vslw 2536 }; 2537 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2538 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2539 } 2540 2541 // vsplti + srl self. 2542 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2543 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2544 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2545 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 2546 Intrinsic::ppc_altivec_vsrw 2547 }; 2548 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2549 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2550 } 2551 2552 // vsplti + sra self. 2553 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2554 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2555 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2556 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 2557 Intrinsic::ppc_altivec_vsraw 2558 }; 2559 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2560 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2561 } 2562 2563 // vsplti + rol self. 2564 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 2565 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 2566 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2567 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2568 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 2569 Intrinsic::ppc_altivec_vrlw 2570 }; 2571 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2572 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2573 } 2574 2575 // t = vsplti c, result = vsldoi t, t, 1 2576 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 2577 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2578 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 2579 } 2580 // t = vsplti c, result = vsldoi t, t, 2 2581 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 2582 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2583 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 2584 } 2585 // t = vsplti c, result = vsldoi t, t, 3 2586 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 2587 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2588 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 2589 } 2590 } 2591 2592 // Three instruction sequences. 2593 2594 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 2595 if (SextVal >= 0 && SextVal <= 31) { 2596 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 2597 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2598 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); 2599 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2600 } 2601 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 2602 if (SextVal >= -31 && SextVal <= 0) { 2603 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 2604 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2605 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); 2606 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2607 } 2608 } 2609 2610 return SDOperand(); 2611} 2612 2613/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2614/// the specified operations to build the shuffle. 2615static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 2616 SDOperand RHS, SelectionDAG &DAG) { 2617 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2618 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2619 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2620 2621 enum { 2622 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2623 OP_VMRGHW, 2624 OP_VMRGLW, 2625 OP_VSPLTISW0, 2626 OP_VSPLTISW1, 2627 OP_VSPLTISW2, 2628 OP_VSPLTISW3, 2629 OP_VSLDOI4, 2630 OP_VSLDOI8, 2631 OP_VSLDOI12 2632 }; 2633 2634 if (OpNum == OP_COPY) { 2635 if (LHSID == (1*9+2)*9+3) return LHS; 2636 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2637 return RHS; 2638 } 2639 2640 SDOperand OpLHS, OpRHS; 2641 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 2642 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 2643 2644 unsigned ShufIdxs[16]; 2645 switch (OpNum) { 2646 default: assert(0 && "Unknown i32 permute!"); 2647 case OP_VMRGHW: 2648 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 2649 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 2650 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 2651 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 2652 break; 2653 case OP_VMRGLW: 2654 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 2655 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 2656 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 2657 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 2658 break; 2659 case OP_VSPLTISW0: 2660 for (unsigned i = 0; i != 16; ++i) 2661 ShufIdxs[i] = (i&3)+0; 2662 break; 2663 case OP_VSPLTISW1: 2664 for (unsigned i = 0; i != 16; ++i) 2665 ShufIdxs[i] = (i&3)+4; 2666 break; 2667 case OP_VSPLTISW2: 2668 for (unsigned i = 0; i != 16; ++i) 2669 ShufIdxs[i] = (i&3)+8; 2670 break; 2671 case OP_VSPLTISW3: 2672 for (unsigned i = 0; i != 16; ++i) 2673 ShufIdxs[i] = (i&3)+12; 2674 break; 2675 case OP_VSLDOI4: 2676 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 2677 case OP_VSLDOI8: 2678 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 2679 case OP_VSLDOI12: 2680 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 2681 } 2682 SDOperand Ops[16]; 2683 for (unsigned i = 0; i != 16; ++i) 2684 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 2685 2686 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 2687 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2688} 2689 2690/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 2691/// is a shuffle we can handle in a single instruction, return it. Otherwise, 2692/// return the code it can be lowered into. Worst case, it can always be 2693/// lowered into a vperm. 2694static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 2695 SDOperand V1 = Op.getOperand(0); 2696 SDOperand V2 = Op.getOperand(1); 2697 SDOperand PermMask = Op.getOperand(2); 2698 2699 // Cases that are handled by instructions that take permute immediates 2700 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 2701 // selected by the instruction selector. 2702 if (V2.getOpcode() == ISD::UNDEF) { 2703 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 2704 PPC::isSplatShuffleMask(PermMask.Val, 2) || 2705 PPC::isSplatShuffleMask(PermMask.Val, 4) || 2706 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 2707 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 2708 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 2709 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 2710 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 2711 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 2712 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 2713 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 2714 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 2715 return Op; 2716 } 2717 } 2718 2719 // Altivec has a variety of "shuffle immediates" that take two vector inputs 2720 // and produce a fixed permutation. If any of these match, do not lower to 2721 // VPERM. 2722 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 2723 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 2724 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 2725 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 2726 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 2727 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 2728 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 2729 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 2730 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 2731 return Op; 2732 2733 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 2734 // perfect shuffle table to emit an optimal matching sequence. 2735 unsigned PFIndexes[4]; 2736 bool isFourElementShuffle = true; 2737 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 2738 unsigned EltNo = 8; // Start out undef. 2739 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 2740 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 2741 continue; // Undef, ignore it. 2742 2743 unsigned ByteSource = 2744 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 2745 if ((ByteSource & 3) != j) { 2746 isFourElementShuffle = false; 2747 break; 2748 } 2749 2750 if (EltNo == 8) { 2751 EltNo = ByteSource/4; 2752 } else if (EltNo != ByteSource/4) { 2753 isFourElementShuffle = false; 2754 break; 2755 } 2756 } 2757 PFIndexes[i] = EltNo; 2758 } 2759 2760 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 2761 // perfect shuffle vector to determine if it is cost effective to do this as 2762 // discrete instructions, or whether we should use a vperm. 2763 if (isFourElementShuffle) { 2764 // Compute the index in the perfect shuffle table. 2765 unsigned PFTableIndex = 2766 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2767 2768 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2769 unsigned Cost = (PFEntry >> 30); 2770 2771 // Determining when to avoid vperm is tricky. Many things affect the cost 2772 // of vperm, particularly how many times the perm mask needs to be computed. 2773 // For example, if the perm mask can be hoisted out of a loop or is already 2774 // used (perhaps because there are multiple permutes with the same shuffle 2775 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 2776 // the loop requires an extra register. 2777 // 2778 // As a compromise, we only emit discrete instructions if the shuffle can be 2779 // generated in 3 or fewer operations. When we have loop information 2780 // available, if this block is within a loop, we should avoid using vperm 2781 // for 3-operation perms and use a constant pool load instead. 2782 if (Cost < 3) 2783 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 2784 } 2785 2786 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 2787 // vector that will get spilled to the constant pool. 2788 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 2789 2790 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 2791 // that it is in input element units, not in bytes. Convert now. 2792 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); 2793 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 2794 2795 SmallVector<SDOperand, 16> ResultMask; 2796 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 2797 unsigned SrcElt; 2798 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 2799 SrcElt = 0; 2800 else 2801 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 2802 2803 for (unsigned j = 0; j != BytesPerElement; ++j) 2804 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 2805 MVT::i8)); 2806 } 2807 2808 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 2809 &ResultMask[0], ResultMask.size()); 2810 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 2811} 2812 2813/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 2814/// altivec comparison. If it is, return true and fill in Opc/isDot with 2815/// information about the intrinsic. 2816static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 2817 bool &isDot) { 2818 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 2819 CompareOpc = -1; 2820 isDot = false; 2821 switch (IntrinsicID) { 2822 default: return false; 2823 // Comparison predicates. 2824 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 2825 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 2826 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 2827 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 2828 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 2829 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 2830 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 2831 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 2832 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 2833 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 2834 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 2835 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 2836 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 2837 2838 // Normal Comparisons. 2839 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 2840 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 2841 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 2842 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 2843 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 2844 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 2845 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 2846 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 2847 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 2848 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 2849 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 2850 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 2851 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 2852 } 2853 return true; 2854} 2855 2856/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 2857/// lower, do it, otherwise return null. 2858static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 2859 // If this is a lowered altivec predicate compare, CompareOpc is set to the 2860 // opcode number of the comparison. 2861 int CompareOpc; 2862 bool isDot; 2863 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 2864 return SDOperand(); // Don't custom lower most intrinsics. 2865 2866 // If this is a non-dot comparison, make the VCMP node and we are done. 2867 if (!isDot) { 2868 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 2869 Op.getOperand(1), Op.getOperand(2), 2870 DAG.getConstant(CompareOpc, MVT::i32)); 2871 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 2872 } 2873 2874 // Create the PPCISD altivec 'dot' comparison node. 2875 SDOperand Ops[] = { 2876 Op.getOperand(2), // LHS 2877 Op.getOperand(3), // RHS 2878 DAG.getConstant(CompareOpc, MVT::i32) 2879 }; 2880 std::vector<MVT::ValueType> VTs; 2881 VTs.push_back(Op.getOperand(2).getValueType()); 2882 VTs.push_back(MVT::Flag); 2883 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2884 2885 // Now that we have the comparison, emit a copy from the CR to a GPR. 2886 // This is flagged to the above dot comparison. 2887 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 2888 DAG.getRegister(PPC::CR6, MVT::i32), 2889 CompNode.getValue(1)); 2890 2891 // Unpack the result based on how the target uses it. 2892 unsigned BitNo; // Bit # of CR6. 2893 bool InvertBit; // Invert result? 2894 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 2895 default: // Can't happen, don't crash on invalid number though. 2896 case 0: // Return the value of the EQ bit of CR6. 2897 BitNo = 0; InvertBit = false; 2898 break; 2899 case 1: // Return the inverted value of the EQ bit of CR6. 2900 BitNo = 0; InvertBit = true; 2901 break; 2902 case 2: // Return the value of the LT bit of CR6. 2903 BitNo = 2; InvertBit = false; 2904 break; 2905 case 3: // Return the inverted value of the LT bit of CR6. 2906 BitNo = 2; InvertBit = true; 2907 break; 2908 } 2909 2910 // Shift the bit into the low position. 2911 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 2912 DAG.getConstant(8-(3-BitNo), MVT::i32)); 2913 // Isolate the bit. 2914 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 2915 DAG.getConstant(1, MVT::i32)); 2916 2917 // If we are supposed to, toggle the bit. 2918 if (InvertBit) 2919 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 2920 DAG.getConstant(1, MVT::i32)); 2921 return Flags; 2922} 2923 2924static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2925 // Create a stack slot that is 16-byte aligned. 2926 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2927 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 2928 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2929 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2930 2931 // Store the input value into Value#0 of the stack slot. 2932 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 2933 Op.getOperand(0), FIdx, NULL, 0); 2934 // Load it out. 2935 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 2936} 2937 2938static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 2939 if (Op.getValueType() == MVT::v4i32) { 2940 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2941 2942 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 2943 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 2944 2945 SDOperand RHSSwap = // = vrlw RHS, 16 2946 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 2947 2948 // Shrinkify inputs to v8i16. 2949 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 2950 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 2951 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 2952 2953 // Low parts multiplied together, generating 32-bit results (we ignore the 2954 // top parts). 2955 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 2956 LHS, RHS, DAG, MVT::v4i32); 2957 2958 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 2959 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 2960 // Shift the high parts up 16 bits. 2961 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 2962 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 2963 } else if (Op.getValueType() == MVT::v8i16) { 2964 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2965 2966 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 2967 2968 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 2969 LHS, RHS, Zero, DAG); 2970 } else if (Op.getValueType() == MVT::v16i8) { 2971 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2972 2973 // Multiply the even 8-bit parts, producing 16-bit sums. 2974 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 2975 LHS, RHS, DAG, MVT::v8i16); 2976 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 2977 2978 // Multiply the odd 8-bit parts, producing 16-bit sums. 2979 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 2980 LHS, RHS, DAG, MVT::v8i16); 2981 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 2982 2983 // Merge the results together. 2984 SDOperand Ops[16]; 2985 for (unsigned i = 0; i != 8; ++i) { 2986 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 2987 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 2988 } 2989 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 2990 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2991 } else { 2992 assert(0 && "Unknown mul to lower!"); 2993 abort(); 2994 } 2995} 2996 2997/// LowerOperation - Provide custom lowering hooks for some operations. 2998/// 2999SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 3000 switch (Op.getOpcode()) { 3001 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3002 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 3003 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 3004 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 3005 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 3006 case ISD::SETCC: return LowerSETCC(Op, DAG); 3007 case ISD::VASTART: 3008 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3009 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3010 3011 case ISD::VAARG: 3012 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3013 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3014 3015 case ISD::FORMAL_ARGUMENTS: 3016 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, 3017 VarArgsStackOffset, VarArgsNumGPR, 3018 VarArgsNumFPR, PPCSubTarget); 3019 3020 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget); 3021 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); 3022 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 3023 case ISD::DYNAMIC_STACKALLOC: 3024 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 3025 3026 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 3027 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 3028 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 3029 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG); 3030 3031 // Lower 64-bit shifts. 3032 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 3033 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 3034 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 3035 3036 // Vector-related lowering. 3037 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3038 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3039 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 3040 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 3041 case ISD::MUL: return LowerMUL(Op, DAG); 3042 3043 // Frame & Return address. 3044 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3045 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3046 } 3047 return SDOperand(); 3048} 3049 3050SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) { 3051 switch (N->getOpcode()) { 3052 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3053 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val; 3054 } 3055} 3056 3057 3058//===----------------------------------------------------------------------===// 3059// Other Lowering Code 3060//===----------------------------------------------------------------------===// 3061 3062MachineBasicBlock * 3063PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3064 MachineBasicBlock *BB) { 3065 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3066 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 3067 MI->getOpcode() == PPC::SELECT_CC_I8 || 3068 MI->getOpcode() == PPC::SELECT_CC_F4 || 3069 MI->getOpcode() == PPC::SELECT_CC_F8 || 3070 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 3071 "Unexpected instr type to insert"); 3072 3073 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 3074 // control-flow pattern. The incoming instruction knows the destination vreg 3075 // to set, the condition code register to branch on, the true/false values to 3076 // select between, and a branch opcode to use. 3077 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3078 ilist<MachineBasicBlock>::iterator It = BB; 3079 ++It; 3080 3081 // thisMBB: 3082 // ... 3083 // TrueVal = ... 3084 // cmpTY ccX, r1, r2 3085 // bCC copy1MBB 3086 // fallthrough --> copy0MBB 3087 MachineBasicBlock *thisMBB = BB; 3088 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 3089 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 3090 unsigned SelectPred = MI->getOperand(4).getImm(); 3091 BuildMI(BB, TII->get(PPC::BCC)) 3092 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 3093 MachineFunction *F = BB->getParent(); 3094 F->getBasicBlockList().insert(It, copy0MBB); 3095 F->getBasicBlockList().insert(It, sinkMBB); 3096 // Update machine-CFG edges by first adding all successors of the current 3097 // block to the new block which will contain the Phi node for the select. 3098 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 3099 e = BB->succ_end(); i != e; ++i) 3100 sinkMBB->addSuccessor(*i); 3101 // Next, remove all successors of the current block, and add the true 3102 // and fallthrough blocks as its successors. 3103 while(!BB->succ_empty()) 3104 BB->removeSuccessor(BB->succ_begin()); 3105 BB->addSuccessor(copy0MBB); 3106 BB->addSuccessor(sinkMBB); 3107 3108 // copy0MBB: 3109 // %FalseValue = ... 3110 // # fallthrough to sinkMBB 3111 BB = copy0MBB; 3112 3113 // Update machine-CFG edges 3114 BB->addSuccessor(sinkMBB); 3115 3116 // sinkMBB: 3117 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 3118 // ... 3119 BB = sinkMBB; 3120 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 3121 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 3122 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 3123 3124 delete MI; // The pseudo instruction is gone now. 3125 return BB; 3126} 3127 3128//===----------------------------------------------------------------------===// 3129// Target Optimization Hooks 3130//===----------------------------------------------------------------------===// 3131 3132SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 3133 DAGCombinerInfo &DCI) const { 3134 TargetMachine &TM = getTargetMachine(); 3135 SelectionDAG &DAG = DCI.DAG; 3136 switch (N->getOpcode()) { 3137 default: break; 3138 case PPCISD::SHL: 3139 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3140 if (C->getValue() == 0) // 0 << V -> 0. 3141 return N->getOperand(0); 3142 } 3143 break; 3144 case PPCISD::SRL: 3145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3146 if (C->getValue() == 0) // 0 >>u V -> 0. 3147 return N->getOperand(0); 3148 } 3149 break; 3150 case PPCISD::SRA: 3151 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3152 if (C->getValue() == 0 || // 0 >>s V -> 0. 3153 C->isAllOnesValue()) // -1 >>s V -> -1. 3154 return N->getOperand(0); 3155 } 3156 break; 3157 3158 case ISD::SINT_TO_FP: 3159 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 3160 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 3161 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 3162 // We allow the src/dst to be either f32/f64, but the intermediate 3163 // type must be i64. 3164 if (N->getOperand(0).getValueType() == MVT::i64 && 3165 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 3166 SDOperand Val = N->getOperand(0).getOperand(0); 3167 if (Val.getValueType() == MVT::f32) { 3168 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3169 DCI.AddToWorklist(Val.Val); 3170 } 3171 3172 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 3173 DCI.AddToWorklist(Val.Val); 3174 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 3175 DCI.AddToWorklist(Val.Val); 3176 if (N->getValueType(0) == MVT::f32) { 3177 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val, 3178 DAG.getIntPtrConstant(0)); 3179 DCI.AddToWorklist(Val.Val); 3180 } 3181 return Val; 3182 } else if (N->getOperand(0).getValueType() == MVT::i32) { 3183 // If the intermediate type is i32, we can avoid the load/store here 3184 // too. 3185 } 3186 } 3187 } 3188 break; 3189 case ISD::STORE: 3190 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 3191 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 3192 !cast<StoreSDNode>(N)->isTruncatingStore() && 3193 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 3194 N->getOperand(1).getValueType() == MVT::i32 && 3195 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 3196 SDOperand Val = N->getOperand(1).getOperand(0); 3197 if (Val.getValueType() == MVT::f32) { 3198 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3199 DCI.AddToWorklist(Val.Val); 3200 } 3201 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 3202 DCI.AddToWorklist(Val.Val); 3203 3204 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 3205 N->getOperand(2), N->getOperand(3)); 3206 DCI.AddToWorklist(Val.Val); 3207 return Val; 3208 } 3209 3210 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 3211 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 3212 N->getOperand(1).Val->hasOneUse() && 3213 (N->getOperand(1).getValueType() == MVT::i32 || 3214 N->getOperand(1).getValueType() == MVT::i16)) { 3215 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 3216 // Do an any-extend to 32-bits if this is a half-word input. 3217 if (BSwapOp.getValueType() == MVT::i16) 3218 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 3219 3220 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 3221 N->getOperand(2), N->getOperand(3), 3222 DAG.getValueType(N->getOperand(1).getValueType())); 3223 } 3224 break; 3225 case ISD::BSWAP: 3226 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 3227 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 3228 N->getOperand(0).hasOneUse() && 3229 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 3230 SDOperand Load = N->getOperand(0); 3231 LoadSDNode *LD = cast<LoadSDNode>(Load); 3232 // Create the byte-swapping load. 3233 std::vector<MVT::ValueType> VTs; 3234 VTs.push_back(MVT::i32); 3235 VTs.push_back(MVT::Other); 3236 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); 3237 SDOperand Ops[] = { 3238 LD->getChain(), // Chain 3239 LD->getBasePtr(), // Ptr 3240 SV, // SrcValue 3241 DAG.getValueType(N->getValueType(0)) // VT 3242 }; 3243 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 3244 3245 // If this is an i16 load, insert the truncate. 3246 SDOperand ResVal = BSLoad; 3247 if (N->getValueType(0) == MVT::i16) 3248 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 3249 3250 // First, combine the bswap away. This makes the value produced by the 3251 // load dead. 3252 DCI.CombineTo(N, ResVal); 3253 3254 // Next, combine the load away, we give it a bogus result value but a real 3255 // chain result. The result value is dead because the bswap is dead. 3256 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 3257 3258 // Return N so it doesn't get rechecked! 3259 return SDOperand(N, 0); 3260 } 3261 3262 break; 3263 case PPCISD::VCMP: { 3264 // If a VCMPo node already exists with exactly the same operands as this 3265 // node, use its result instead of this node (VCMPo computes both a CR6 and 3266 // a normal output). 3267 // 3268 if (!N->getOperand(0).hasOneUse() && 3269 !N->getOperand(1).hasOneUse() && 3270 !N->getOperand(2).hasOneUse()) { 3271 3272 // Scan all of the users of the LHS, looking for VCMPo's that match. 3273 SDNode *VCMPoNode = 0; 3274 3275 SDNode *LHSN = N->getOperand(0).Val; 3276 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 3277 UI != E; ++UI) 3278 if ((*UI)->getOpcode() == PPCISD::VCMPo && 3279 (*UI)->getOperand(1) == N->getOperand(1) && 3280 (*UI)->getOperand(2) == N->getOperand(2) && 3281 (*UI)->getOperand(0) == N->getOperand(0)) { 3282 VCMPoNode = *UI; 3283 break; 3284 } 3285 3286 // If there is no VCMPo node, or if the flag value has a single use, don't 3287 // transform this. 3288 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 3289 break; 3290 3291 // Look at the (necessarily single) use of the flag value. If it has a 3292 // chain, this transformation is more complex. Note that multiple things 3293 // could use the value result, which we should ignore. 3294 SDNode *FlagUser = 0; 3295 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 3296 FlagUser == 0; ++UI) { 3297 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 3298 SDNode *User = *UI; 3299 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 3300 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 3301 FlagUser = User; 3302 break; 3303 } 3304 } 3305 } 3306 3307 // If the user is a MFCR instruction, we know this is safe. Otherwise we 3308 // give up for right now. 3309 if (FlagUser->getOpcode() == PPCISD::MFCR) 3310 return SDOperand(VCMPoNode, 0); 3311 } 3312 break; 3313 } 3314 case ISD::BR_CC: { 3315 // If this is a branch on an altivec predicate comparison, lower this so 3316 // that we don't have to do a MFCR: instead, branch directly on CR6. This 3317 // lowering is done pre-legalize, because the legalizer lowers the predicate 3318 // compare down to code that is difficult to reassemble. 3319 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 3320 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 3321 int CompareOpc; 3322 bool isDot; 3323 3324 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 3325 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 3326 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 3327 assert(isDot && "Can't compare against a vector result!"); 3328 3329 // If this is a comparison against something other than 0/1, then we know 3330 // that the condition is never/always true. 3331 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 3332 if (Val != 0 && Val != 1) { 3333 if (CC == ISD::SETEQ) // Cond never true, remove branch. 3334 return N->getOperand(0); 3335 // Always !=, turn it into an unconditional branch. 3336 return DAG.getNode(ISD::BR, MVT::Other, 3337 N->getOperand(0), N->getOperand(4)); 3338 } 3339 3340 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 3341 3342 // Create the PPCISD altivec 'dot' comparison node. 3343 std::vector<MVT::ValueType> VTs; 3344 SDOperand Ops[] = { 3345 LHS.getOperand(2), // LHS of compare 3346 LHS.getOperand(3), // RHS of compare 3347 DAG.getConstant(CompareOpc, MVT::i32) 3348 }; 3349 VTs.push_back(LHS.getOperand(2).getValueType()); 3350 VTs.push_back(MVT::Flag); 3351 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 3352 3353 // Unpack the result based on how the target uses it. 3354 PPC::Predicate CompOpc; 3355 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 3356 default: // Can't happen, don't crash on invalid number though. 3357 case 0: // Branch on the value of the EQ bit of CR6. 3358 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 3359 break; 3360 case 1: // Branch on the inverted value of the EQ bit of CR6. 3361 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 3362 break; 3363 case 2: // Branch on the value of the LT bit of CR6. 3364 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 3365 break; 3366 case 3: // Branch on the inverted value of the LT bit of CR6. 3367 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 3368 break; 3369 } 3370 3371 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 3372 DAG.getConstant(CompOpc, MVT::i32), 3373 DAG.getRegister(PPC::CR6, MVT::i32), 3374 N->getOperand(4), CompNode.getValue(1)); 3375 } 3376 break; 3377 } 3378 } 3379 3380 return SDOperand(); 3381} 3382 3383//===----------------------------------------------------------------------===// 3384// Inline Assembly Support 3385//===----------------------------------------------------------------------===// 3386 3387void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 3388 uint64_t Mask, 3389 uint64_t &KnownZero, 3390 uint64_t &KnownOne, 3391 const SelectionDAG &DAG, 3392 unsigned Depth) const { 3393 KnownZero = 0; 3394 KnownOne = 0; 3395 switch (Op.getOpcode()) { 3396 default: break; 3397 case PPCISD::LBRX: { 3398 // lhbrx is known to have the top bits cleared out. 3399 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 3400 KnownZero = 0xFFFF0000; 3401 break; 3402 } 3403 case ISD::INTRINSIC_WO_CHAIN: { 3404 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 3405 default: break; 3406 case Intrinsic::ppc_altivec_vcmpbfp_p: 3407 case Intrinsic::ppc_altivec_vcmpeqfp_p: 3408 case Intrinsic::ppc_altivec_vcmpequb_p: 3409 case Intrinsic::ppc_altivec_vcmpequh_p: 3410 case Intrinsic::ppc_altivec_vcmpequw_p: 3411 case Intrinsic::ppc_altivec_vcmpgefp_p: 3412 case Intrinsic::ppc_altivec_vcmpgtfp_p: 3413 case Intrinsic::ppc_altivec_vcmpgtsb_p: 3414 case Intrinsic::ppc_altivec_vcmpgtsh_p: 3415 case Intrinsic::ppc_altivec_vcmpgtsw_p: 3416 case Intrinsic::ppc_altivec_vcmpgtub_p: 3417 case Intrinsic::ppc_altivec_vcmpgtuh_p: 3418 case Intrinsic::ppc_altivec_vcmpgtuw_p: 3419 KnownZero = ~1U; // All bits but the low one are known to be zero. 3420 break; 3421 } 3422 } 3423 } 3424} 3425 3426 3427/// getConstraintType - Given a constraint, return the type of 3428/// constraint it is for this target. 3429PPCTargetLowering::ConstraintType 3430PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 3431 if (Constraint.size() == 1) { 3432 switch (Constraint[0]) { 3433 default: break; 3434 case 'b': 3435 case 'r': 3436 case 'f': 3437 case 'v': 3438 case 'y': 3439 return C_RegisterClass; 3440 } 3441 } 3442 return TargetLowering::getConstraintType(Constraint); 3443} 3444 3445std::pair<unsigned, const TargetRegisterClass*> 3446PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3447 MVT::ValueType VT) const { 3448 if (Constraint.size() == 1) { 3449 // GCC RS6000 Constraint Letters 3450 switch (Constraint[0]) { 3451 case 'b': // R1-R31 3452 case 'r': // R0-R31 3453 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 3454 return std::make_pair(0U, PPC::G8RCRegisterClass); 3455 return std::make_pair(0U, PPC::GPRCRegisterClass); 3456 case 'f': 3457 if (VT == MVT::f32) 3458 return std::make_pair(0U, PPC::F4RCRegisterClass); 3459 else if (VT == MVT::f64) 3460 return std::make_pair(0U, PPC::F8RCRegisterClass); 3461 break; 3462 case 'v': 3463 return std::make_pair(0U, PPC::VRRCRegisterClass); 3464 case 'y': // crrc 3465 return std::make_pair(0U, PPC::CRRCRegisterClass); 3466 } 3467 } 3468 3469 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3470} 3471 3472 3473/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3474/// vector. If it is invalid, don't add anything to Ops. 3475void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter, 3476 std::vector<SDOperand>&Ops, 3477 SelectionDAG &DAG) { 3478 SDOperand Result(0,0); 3479 switch (Letter) { 3480 default: break; 3481 case 'I': 3482 case 'J': 3483 case 'K': 3484 case 'L': 3485 case 'M': 3486 case 'N': 3487 case 'O': 3488 case 'P': { 3489 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 3490 if (!CST) return; // Must be an immediate to match. 3491 unsigned Value = CST->getValue(); 3492 switch (Letter) { 3493 default: assert(0 && "Unknown constraint letter!"); 3494 case 'I': // "I" is a signed 16-bit constant. 3495 if ((short)Value == (int)Value) 3496 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3497 break; 3498 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 3499 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 3500 if ((short)Value == 0) 3501 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3502 break; 3503 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 3504 if ((Value >> 16) == 0) 3505 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3506 break; 3507 case 'M': // "M" is a constant that is greater than 31. 3508 if (Value > 31) 3509 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3510 break; 3511 case 'N': // "N" is a positive constant that is an exact power of two. 3512 if ((int)Value > 0 && isPowerOf2_32(Value)) 3513 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3514 break; 3515 case 'O': // "O" is the constant zero. 3516 if (Value == 0) 3517 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3518 break; 3519 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 3520 if ((short)-Value == (int)-Value) 3521 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3522 break; 3523 } 3524 break; 3525 } 3526 } 3527 3528 if (Result.Val) { 3529 Ops.push_back(Result); 3530 return; 3531 } 3532 3533 // Handle standard constraint letters. 3534 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); 3535} 3536 3537// isLegalAddressingMode - Return true if the addressing mode represented 3538// by AM is legal for this target, for a load/store of the specified type. 3539bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3540 const Type *Ty) const { 3541 // FIXME: PPC does not allow r+i addressing modes for vectors! 3542 3543 // PPC allows a sign-extended 16-bit immediate field. 3544 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3545 return false; 3546 3547 // No global is ever allowed as a base. 3548 if (AM.BaseGV) 3549 return false; 3550 3551 // PPC only support r+r, 3552 switch (AM.Scale) { 3553 case 0: // "r+i" or just "i", depending on HasBaseReg. 3554 break; 3555 case 1: 3556 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3557 return false; 3558 // Otherwise we have r+r or r+i. 3559 break; 3560 case 2: 3561 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3562 return false; 3563 // Allow 2*r as r+r. 3564 break; 3565 default: 3566 // No other scales are supported. 3567 return false; 3568 } 3569 3570 return true; 3571} 3572 3573/// isLegalAddressImmediate - Return true if the integer value can be used 3574/// as the offset of the target addressing mode for load / store of the 3575/// given type. 3576bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 3577 // PPC allows a sign-extended 16-bit immediate field. 3578 return (V > -(1 << 16) && V < (1 << 16)-1); 3579} 3580 3581bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 3582 return false; 3583} 3584 3585SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { 3586 // Depths > 0 not supported yet! 3587 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3588 return SDOperand(); 3589 3590 MachineFunction &MF = DAG.getMachineFunction(); 3591 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 3592 int RAIdx = FuncInfo->getReturnAddrSaveIndex(); 3593 if (RAIdx == 0) { 3594 bool isPPC64 = PPCSubTarget.isPPC64(); 3595 int Offset = 3596 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI()); 3597 3598 // Set up a frame object for the return address. 3599 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset); 3600 3601 // Remember it for next time. 3602 FuncInfo->setReturnAddrSaveIndex(RAIdx); 3603 3604 // Make sure the function really does not optimize away the store of the RA 3605 // to the stack. 3606 FuncInfo->setLRStoreRequired(); 3607 } 3608 3609 // Just load the return address off the stack. 3610 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy()); 3611 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 3612} 3613 3614SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { 3615 // Depths > 0 not supported yet! 3616 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3617 return SDOperand(); 3618 3619 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3620 bool isPPC64 = PtrVT == MVT::i64; 3621 3622 MachineFunction &MF = DAG.getMachineFunction(); 3623 MachineFrameInfo *MFI = MF.getFrameInfo(); 3624 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 3625 && MFI->getStackSize(); 3626 3627 if (isPPC64) 3628 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, 3629 MVT::i64); 3630 else 3631 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, 3632 MVT::i32); 3633} 3634