PPCISelLowering.cpp revision 4ee451de366474b9c228b4e5fa573795a715216d
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/Analysis/ScalarEvolutionExpressions.h" 22#include "llvm/CodeGen/CallingConvLower.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Constants.h" 29#include "llvm/Function.h" 30#include "llvm/Intrinsics.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/Target/TargetOptions.h" 33#include "llvm/Support/CommandLine.h" 34using namespace llvm; 35 36static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 37cl::desc("enable preincrement load/store generation on PPC (experimental)"), 38 cl::Hidden); 39 40PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 41 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 42 43 setPow2DivIsCheap(); 44 45 // Use _setjmp/_longjmp instead of setjmp/longjmp. 46 setUseUnderscoreSetJmp(true); 47 setUseUnderscoreLongJmp(true); 48 49 // Set up the register classes. 50 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 51 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 52 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 53 54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 55 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 56 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 57 58 // PowerPC does not have truncstore for i1. 59 setStoreXAction(MVT::i1, Promote); 60 61 // PowerPC has pre-inc load and store's. 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 72 73 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 74 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 75 76 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) 77 setConvertAction(MVT::ppcf128, MVT::f64, Expand); 78 setConvertAction(MVT::ppcf128, MVT::f32, Expand); 79 // This is used in the ppcf128->int sequence. Note it has different semantics 80 // from FP_ROUND: that rounds to nearest, this rounds to zero. 81 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 82 83 // PowerPC has no intrinsics for these particular operations 84 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 85 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 86 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 87 88 // PowerPC has no SREM/UREM instructions 89 setOperationAction(ISD::SREM, MVT::i32, Expand); 90 setOperationAction(ISD::UREM, MVT::i32, Expand); 91 setOperationAction(ISD::SREM, MVT::i64, Expand); 92 setOperationAction(ISD::UREM, MVT::i64, Expand); 93 94 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 95 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 96 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 97 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 98 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 99 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 100 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 101 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 102 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 103 104 // We don't support sin/cos/sqrt/fmod/pow 105 setOperationAction(ISD::FSIN , MVT::f64, Expand); 106 setOperationAction(ISD::FCOS , MVT::f64, Expand); 107 setOperationAction(ISD::FREM , MVT::f64, Expand); 108 setOperationAction(ISD::FPOW , MVT::f64, Expand); 109 setOperationAction(ISD::FSIN , MVT::f32, Expand); 110 setOperationAction(ISD::FCOS , MVT::f32, Expand); 111 setOperationAction(ISD::FREM , MVT::f32, Expand); 112 setOperationAction(ISD::FPOW , MVT::f32, Expand); 113 114 // If we're enabling GP optimizations, use hardware square root 115 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 116 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 117 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 118 } 119 120 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 121 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 122 123 // PowerPC does not have BSWAP, CTPOP or CTTZ 124 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 125 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 126 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 127 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 128 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 129 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 130 131 // PowerPC does not have ROTR 132 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 133 134 // PowerPC does not have Select 135 setOperationAction(ISD::SELECT, MVT::i32, Expand); 136 setOperationAction(ISD::SELECT, MVT::i64, Expand); 137 setOperationAction(ISD::SELECT, MVT::f32, Expand); 138 setOperationAction(ISD::SELECT, MVT::f64, Expand); 139 140 // PowerPC wants to turn select_cc of FP into fsel when possible. 141 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 142 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 143 144 // PowerPC wants to optimize integer setcc a bit 145 setOperationAction(ISD::SETCC, MVT::i32, Custom); 146 147 // PowerPC does not have BRCOND which requires SetCC 148 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 149 150 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 151 152 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 153 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 154 155 // PowerPC does not have [U|S]INT_TO_FP 156 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 157 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 158 159 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 160 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 161 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 162 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 163 164 // We cannot sextinreg(i1). Expand to shifts. 165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 166 167 // Support label based line numbers. 168 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 169 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 170 171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 172 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 174 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 175 176 177 // We want to legalize GlobalAddress and ConstantPool nodes into the 178 // appropriate instructions to materialize the address. 179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 180 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 182 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 183 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 184 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 185 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 186 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 187 188 // RET must be custom lowered, to meet ABI requirements 189 setOperationAction(ISD::RET , MVT::Other, Custom); 190 191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 192 setOperationAction(ISD::VASTART , MVT::Other, Custom); 193 194 // VAARG is custom lowered with ELF 32 ABI 195 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) 196 setOperationAction(ISD::VAARG, MVT::Other, Custom); 197 else 198 setOperationAction(ISD::VAARG, MVT::Other, Expand); 199 200 // Use the default implementation. 201 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 202 setOperationAction(ISD::VAEND , MVT::Other, Expand); 203 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 204 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 207 208 // We want to custom lower some of our intrinsics. 209 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 210 211 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 212 // They also have instructions for converting between i64 and fp. 213 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 214 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 215 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 217 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 218 219 // FIXME: disable this lowered code. This generates 64-bit register values, 220 // and we don't model the fact that the top part is clobbered by calls. We 221 // need to flag these together so that the value isn't live across a call. 222 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 223 224 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 226 } else { 227 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 228 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 229 } 230 231 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 232 // 64-bit PowerPC implementations can support i64 types directly 233 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 234 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 235 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 236 } else { 237 // 32-bit PowerPC wants to expand i64 shifts itself. 238 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 239 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 240 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 241 } 242 243 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 244 // First set operation action for all vector types to expand. Then we 245 // will selectively turn on ones that can be effectively codegen'd. 246 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 247 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 248 // add/sub are legal for all supported vector VT's. 249 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 250 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 251 252 // We promote all shuffles to v16i8. 253 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 254 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 255 256 // We promote all non-typed operations to v4i32. 257 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 258 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 259 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 260 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 261 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 262 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 263 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 264 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 265 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 266 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 267 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 268 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 269 270 // No other operations are legal. 271 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 272 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 273 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 274 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 275 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 276 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 277 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); 278 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 279 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 280 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 281 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); 282 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); 283 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); 284 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); 285 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 286 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); 287 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); 288 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); 289 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); 290 } 291 292 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 293 // with merges, splats, etc. 294 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 295 296 setOperationAction(ISD::AND , MVT::v4i32, Legal); 297 setOperationAction(ISD::OR , MVT::v4i32, Legal); 298 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 299 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 300 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 301 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 302 303 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 304 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 305 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 306 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 307 308 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 309 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 310 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 311 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 312 313 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 314 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 315 316 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 317 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 318 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 319 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 320 } 321 322 setSetCCResultType(MVT::i32); 323 setShiftAmountType(MVT::i32); 324 setSetCCResultContents(ZeroOrOneSetCCResult); 325 326 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 327 setStackPointerRegisterToSaveRestore(PPC::X1); 328 setExceptionPointerRegister(PPC::X3); 329 setExceptionSelectorRegister(PPC::X4); 330 } else { 331 setStackPointerRegisterToSaveRestore(PPC::R1); 332 setExceptionPointerRegister(PPC::R3); 333 setExceptionSelectorRegister(PPC::R4); 334 } 335 336 // We have target-specific dag combine patterns for the following nodes: 337 setTargetDAGCombine(ISD::SINT_TO_FP); 338 setTargetDAGCombine(ISD::STORE); 339 setTargetDAGCombine(ISD::BR_CC); 340 setTargetDAGCombine(ISD::BSWAP); 341 342 // Darwin long double math library functions have $LDBL128 appended. 343 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 344 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 345 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 346 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 347 } 348 349 computeRegisterProperties(); 350} 351 352const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 353 switch (Opcode) { 354 default: return 0; 355 case PPCISD::FSEL: return "PPCISD::FSEL"; 356 case PPCISD::FCFID: return "PPCISD::FCFID"; 357 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 358 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 359 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 360 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 361 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 362 case PPCISD::VPERM: return "PPCISD::VPERM"; 363 case PPCISD::Hi: return "PPCISD::Hi"; 364 case PPCISD::Lo: return "PPCISD::Lo"; 365 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 366 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 367 case PPCISD::SRL: return "PPCISD::SRL"; 368 case PPCISD::SRA: return "PPCISD::SRA"; 369 case PPCISD::SHL: return "PPCISD::SHL"; 370 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 371 case PPCISD::STD_32: return "PPCISD::STD_32"; 372 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 373 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 374 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 375 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 376 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 377 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 378 case PPCISD::MFCR: return "PPCISD::MFCR"; 379 case PPCISD::VCMP: return "PPCISD::VCMP"; 380 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 381 case PPCISD::LBRX: return "PPCISD::LBRX"; 382 case PPCISD::STBRX: return "PPCISD::STBRX"; 383 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 384 } 385} 386 387//===----------------------------------------------------------------------===// 388// Node matching predicates, for use by the tblgen matching code. 389//===----------------------------------------------------------------------===// 390 391/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 392static bool isFloatingPointZero(SDOperand Op) { 393 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 394 return CFP->getValueAPF().isZero(); 395 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 396 // Maybe this has already been legalized into the constant pool? 397 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 398 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 399 return CFP->getValueAPF().isZero(); 400 } 401 return false; 402} 403 404/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 405/// true if Op is undef or if it matches the specified value. 406static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 407 return Op.getOpcode() == ISD::UNDEF || 408 cast<ConstantSDNode>(Op)->getValue() == Val; 409} 410 411/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 412/// VPKUHUM instruction. 413bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 414 if (!isUnary) { 415 for (unsigned i = 0; i != 16; ++i) 416 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 417 return false; 418 } else { 419 for (unsigned i = 0; i != 8; ++i) 420 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 421 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 422 return false; 423 } 424 return true; 425} 426 427/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 428/// VPKUWUM instruction. 429bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 430 if (!isUnary) { 431 for (unsigned i = 0; i != 16; i += 2) 432 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 433 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 434 return false; 435 } else { 436 for (unsigned i = 0; i != 8; i += 2) 437 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 438 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 439 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 440 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 441 return false; 442 } 443 return true; 444} 445 446/// isVMerge - Common function, used to match vmrg* shuffles. 447/// 448static bool isVMerge(SDNode *N, unsigned UnitSize, 449 unsigned LHSStart, unsigned RHSStart) { 450 assert(N->getOpcode() == ISD::BUILD_VECTOR && 451 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 452 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 453 "Unsupported merge size!"); 454 455 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 456 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 457 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 458 LHSStart+j+i*UnitSize) || 459 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 460 RHSStart+j+i*UnitSize)) 461 return false; 462 } 463 return true; 464} 465 466/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 467/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 468bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 469 if (!isUnary) 470 return isVMerge(N, UnitSize, 8, 24); 471 return isVMerge(N, UnitSize, 8, 8); 472} 473 474/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 475/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 476bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 477 if (!isUnary) 478 return isVMerge(N, UnitSize, 0, 16); 479 return isVMerge(N, UnitSize, 0, 0); 480} 481 482 483/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 484/// amount, otherwise return -1. 485int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 486 assert(N->getOpcode() == ISD::BUILD_VECTOR && 487 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 488 // Find the first non-undef value in the shuffle mask. 489 unsigned i; 490 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 491 /*search*/; 492 493 if (i == 16) return -1; // all undef. 494 495 // Otherwise, check to see if the rest of the elements are consequtively 496 // numbered from this value. 497 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 498 if (ShiftAmt < i) return -1; 499 ShiftAmt -= i; 500 501 if (!isUnary) { 502 // Check the rest of the elements to see if they are consequtive. 503 for (++i; i != 16; ++i) 504 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 505 return -1; 506 } else { 507 // Check the rest of the elements to see if they are consequtive. 508 for (++i; i != 16; ++i) 509 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 510 return -1; 511 } 512 513 return ShiftAmt; 514} 515 516/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 517/// specifies a splat of a single element that is suitable for input to 518/// VSPLTB/VSPLTH/VSPLTW. 519bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 520 assert(N->getOpcode() == ISD::BUILD_VECTOR && 521 N->getNumOperands() == 16 && 522 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 523 524 // This is a splat operation if each element of the permute is the same, and 525 // if the value doesn't reference the second vector. 526 unsigned ElementBase = 0; 527 SDOperand Elt = N->getOperand(0); 528 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 529 ElementBase = EltV->getValue(); 530 else 531 return false; // FIXME: Handle UNDEF elements too! 532 533 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 534 return false; 535 536 // Check that they are consequtive. 537 for (unsigned i = 1; i != EltSize; ++i) { 538 if (!isa<ConstantSDNode>(N->getOperand(i)) || 539 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 540 return false; 541 } 542 543 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 544 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 545 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 546 assert(isa<ConstantSDNode>(N->getOperand(i)) && 547 "Invalid VECTOR_SHUFFLE mask!"); 548 for (unsigned j = 0; j != EltSize; ++j) 549 if (N->getOperand(i+j) != N->getOperand(j)) 550 return false; 551 } 552 553 return true; 554} 555 556/// isAllNegativeZeroVector - Returns true if all elements of build_vector 557/// are -0.0. 558bool PPC::isAllNegativeZeroVector(SDNode *N) { 559 assert(N->getOpcode() == ISD::BUILD_VECTOR); 560 if (PPC::isSplatShuffleMask(N, N->getNumOperands())) 561 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) 562 return CFP->getValueAPF().isNegZero(); 563 return false; 564} 565 566/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 567/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 568unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 569 assert(isSplatShuffleMask(N, EltSize)); 570 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 571} 572 573/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 574/// by using a vspltis[bhw] instruction of the specified element size, return 575/// the constant being splatted. The ByteSize field indicates the number of 576/// bytes of each element [124] -> [bhw]. 577SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 578 SDOperand OpVal(0, 0); 579 580 // If ByteSize of the splat is bigger than the element size of the 581 // build_vector, then we have a case where we are checking for a splat where 582 // multiple elements of the buildvector are folded together into a single 583 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 584 unsigned EltSize = 16/N->getNumOperands(); 585 if (EltSize < ByteSize) { 586 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 587 SDOperand UniquedVals[4]; 588 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 589 590 // See if all of the elements in the buildvector agree across. 591 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 592 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 593 // If the element isn't a constant, bail fully out. 594 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 595 596 597 if (UniquedVals[i&(Multiple-1)].Val == 0) 598 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 599 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 600 return SDOperand(); // no match. 601 } 602 603 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 604 // either constant or undef values that are identical for each chunk. See 605 // if these chunks can form into a larger vspltis*. 606 607 // Check to see if all of the leading entries are either 0 or -1. If 608 // neither, then this won't fit into the immediate field. 609 bool LeadingZero = true; 610 bool LeadingOnes = true; 611 for (unsigned i = 0; i != Multiple-1; ++i) { 612 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 613 614 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 615 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 616 } 617 // Finally, check the least significant entry. 618 if (LeadingZero) { 619 if (UniquedVals[Multiple-1].Val == 0) 620 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 621 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 622 if (Val < 16) 623 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 624 } 625 if (LeadingOnes) { 626 if (UniquedVals[Multiple-1].Val == 0) 627 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 628 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 629 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 630 return DAG.getTargetConstant(Val, MVT::i32); 631 } 632 633 return SDOperand(); 634 } 635 636 // Check to see if this buildvec has a single non-undef value in its elements. 637 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 638 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 639 if (OpVal.Val == 0) 640 OpVal = N->getOperand(i); 641 else if (OpVal != N->getOperand(i)) 642 return SDOperand(); 643 } 644 645 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 646 647 unsigned ValSizeInBytes = 0; 648 uint64_t Value = 0; 649 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 650 Value = CN->getValue(); 651 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 652 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 653 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 654 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 655 ValSizeInBytes = 4; 656 } 657 658 // If the splat value is larger than the element value, then we can never do 659 // this splat. The only case that we could fit the replicated bits into our 660 // immediate field for would be zero, and we prefer to use vxor for it. 661 if (ValSizeInBytes < ByteSize) return SDOperand(); 662 663 // If the element value is larger than the splat value, cut it in half and 664 // check to see if the two halves are equal. Continue doing this until we 665 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 666 while (ValSizeInBytes > ByteSize) { 667 ValSizeInBytes >>= 1; 668 669 // If the top half equals the bottom half, we're still ok. 670 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 671 (Value & ((1 << (8*ValSizeInBytes))-1))) 672 return SDOperand(); 673 } 674 675 // Properly sign extend the value. 676 int ShAmt = (4-ByteSize)*8; 677 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 678 679 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 680 if (MaskVal == 0) return SDOperand(); 681 682 // Finally, if this value fits in a 5 bit sext field, return it 683 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 684 return DAG.getTargetConstant(MaskVal, MVT::i32); 685 return SDOperand(); 686} 687 688//===----------------------------------------------------------------------===// 689// Addressing Mode Selection 690//===----------------------------------------------------------------------===// 691 692/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 693/// or 64-bit immediate, and if the value can be accurately represented as a 694/// sign extension from a 16-bit value. If so, this returns true and the 695/// immediate. 696static bool isIntS16Immediate(SDNode *N, short &Imm) { 697 if (N->getOpcode() != ISD::Constant) 698 return false; 699 700 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 701 if (N->getValueType(0) == MVT::i32) 702 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 703 else 704 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 705} 706static bool isIntS16Immediate(SDOperand Op, short &Imm) { 707 return isIntS16Immediate(Op.Val, Imm); 708} 709 710 711/// SelectAddressRegReg - Given the specified addressed, check to see if it 712/// can be represented as an indexed [r+r] operation. Returns false if it 713/// can be more efficiently represented with [r+imm]. 714bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, 715 SDOperand &Index, 716 SelectionDAG &DAG) { 717 short imm = 0; 718 if (N.getOpcode() == ISD::ADD) { 719 if (isIntS16Immediate(N.getOperand(1), imm)) 720 return false; // r+i 721 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 722 return false; // r+i 723 724 Base = N.getOperand(0); 725 Index = N.getOperand(1); 726 return true; 727 } else if (N.getOpcode() == ISD::OR) { 728 if (isIntS16Immediate(N.getOperand(1), imm)) 729 return false; // r+i can fold it if we can. 730 731 // If this is an or of disjoint bitfields, we can codegen this as an add 732 // (for better address arithmetic) if the LHS and RHS of the OR are provably 733 // disjoint. 734 uint64_t LHSKnownZero, LHSKnownOne; 735 uint64_t RHSKnownZero, RHSKnownOne; 736 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 737 738 if (LHSKnownZero) { 739 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); 740 // If all of the bits are known zero on the LHS or RHS, the add won't 741 // carry. 742 if ((LHSKnownZero | RHSKnownZero) == ~0U) { 743 Base = N.getOperand(0); 744 Index = N.getOperand(1); 745 return true; 746 } 747 } 748 } 749 750 return false; 751} 752 753/// Returns true if the address N can be represented by a base register plus 754/// a signed 16-bit displacement [r+imm], and if it is not better 755/// represented as reg+reg. 756bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, 757 SDOperand &Base, SelectionDAG &DAG){ 758 // If this can be more profitably realized as r+r, fail. 759 if (SelectAddressRegReg(N, Disp, Base, DAG)) 760 return false; 761 762 if (N.getOpcode() == ISD::ADD) { 763 short imm = 0; 764 if (isIntS16Immediate(N.getOperand(1), imm)) { 765 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 766 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 767 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 768 } else { 769 Base = N.getOperand(0); 770 } 771 return true; // [r+i] 772 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 773 // Match LOAD (ADD (X, Lo(G))). 774 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 775 && "Cannot handle constant offsets yet!"); 776 Disp = N.getOperand(1).getOperand(0); // The global address. 777 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 778 Disp.getOpcode() == ISD::TargetConstantPool || 779 Disp.getOpcode() == ISD::TargetJumpTable); 780 Base = N.getOperand(0); 781 return true; // [&g+r] 782 } 783 } else if (N.getOpcode() == ISD::OR) { 784 short imm = 0; 785 if (isIntS16Immediate(N.getOperand(1), imm)) { 786 // If this is an or of disjoint bitfields, we can codegen this as an add 787 // (for better address arithmetic) if the LHS and RHS of the OR are 788 // provably disjoint. 789 uint64_t LHSKnownZero, LHSKnownOne; 790 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 791 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 792 // If all of the bits are known zero on the LHS or RHS, the add won't 793 // carry. 794 Base = N.getOperand(0); 795 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 796 return true; 797 } 798 } 799 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 800 // Loading from a constant address. 801 802 // If this address fits entirely in a 16-bit sext immediate field, codegen 803 // this as "d, 0" 804 short Imm; 805 if (isIntS16Immediate(CN, Imm)) { 806 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 807 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 808 return true; 809 } 810 811 // Handle 32-bit sext immediates with LIS + addr mode. 812 if (CN->getValueType(0) == MVT::i32 || 813 (int64_t)CN->getValue() == (int)CN->getValue()) { 814 int Addr = (int)CN->getValue(); 815 816 // Otherwise, break this down into an LIS + disp. 817 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 818 819 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 820 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 821 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 822 return true; 823 } 824 } 825 826 Disp = DAG.getTargetConstant(0, getPointerTy()); 827 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 828 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 829 else 830 Base = N; 831 return true; // [r+0] 832} 833 834/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 835/// represented as an indexed [r+r] operation. 836bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, 837 SDOperand &Index, 838 SelectionDAG &DAG) { 839 // Check to see if we can easily represent this as an [r+r] address. This 840 // will fail if it thinks that the address is more profitably represented as 841 // reg+imm, e.g. where imm = 0. 842 if (SelectAddressRegReg(N, Base, Index, DAG)) 843 return true; 844 845 // If the operand is an addition, always emit this as [r+r], since this is 846 // better (for code size, and execution, as the memop does the add for free) 847 // than emitting an explicit add. 848 if (N.getOpcode() == ISD::ADD) { 849 Base = N.getOperand(0); 850 Index = N.getOperand(1); 851 return true; 852 } 853 854 // Otherwise, do it the hard way, using R0 as the base register. 855 Base = DAG.getRegister(PPC::R0, N.getValueType()); 856 Index = N; 857 return true; 858} 859 860/// SelectAddressRegImmShift - Returns true if the address N can be 861/// represented by a base register plus a signed 14-bit displacement 862/// [r+imm*4]. Suitable for use by STD and friends. 863bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, 864 SDOperand &Base, 865 SelectionDAG &DAG) { 866 // If this can be more profitably realized as r+r, fail. 867 if (SelectAddressRegReg(N, Disp, Base, DAG)) 868 return false; 869 870 if (N.getOpcode() == ISD::ADD) { 871 short imm = 0; 872 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 873 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 874 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 875 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 876 } else { 877 Base = N.getOperand(0); 878 } 879 return true; // [r+i] 880 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 881 // Match LOAD (ADD (X, Lo(G))). 882 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 883 && "Cannot handle constant offsets yet!"); 884 Disp = N.getOperand(1).getOperand(0); // The global address. 885 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 886 Disp.getOpcode() == ISD::TargetConstantPool || 887 Disp.getOpcode() == ISD::TargetJumpTable); 888 Base = N.getOperand(0); 889 return true; // [&g+r] 890 } 891 } else if (N.getOpcode() == ISD::OR) { 892 short imm = 0; 893 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 894 // If this is an or of disjoint bitfields, we can codegen this as an add 895 // (for better address arithmetic) if the LHS and RHS of the OR are 896 // provably disjoint. 897 uint64_t LHSKnownZero, LHSKnownOne; 898 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 899 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 900 // If all of the bits are known zero on the LHS or RHS, the add won't 901 // carry. 902 Base = N.getOperand(0); 903 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 904 return true; 905 } 906 } 907 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 908 // Loading from a constant address. Verify low two bits are clear. 909 if ((CN->getValue() & 3) == 0) { 910 // If this address fits entirely in a 14-bit sext immediate field, codegen 911 // this as "d, 0" 912 short Imm; 913 if (isIntS16Immediate(CN, Imm)) { 914 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 915 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 916 return true; 917 } 918 919 // Fold the low-part of 32-bit absolute addresses into addr mode. 920 if (CN->getValueType(0) == MVT::i32 || 921 (int64_t)CN->getValue() == (int)CN->getValue()) { 922 int Addr = (int)CN->getValue(); 923 924 // Otherwise, break this down into an LIS + disp. 925 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 926 927 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 928 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 929 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 930 return true; 931 } 932 } 933 } 934 935 Disp = DAG.getTargetConstant(0, getPointerTy()); 936 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 937 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 938 else 939 Base = N; 940 return true; // [r+0] 941} 942 943 944/// getPreIndexedAddressParts - returns true by value, base pointer and 945/// offset pointer and addressing mode by reference if the node's address 946/// can be legally represented as pre-indexed load / store address. 947bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 948 SDOperand &Offset, 949 ISD::MemIndexedMode &AM, 950 SelectionDAG &DAG) { 951 // Disabled by default for now. 952 if (!EnablePPCPreinc) return false; 953 954 SDOperand Ptr; 955 MVT::ValueType VT; 956 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 957 Ptr = LD->getBasePtr(); 958 VT = LD->getLoadedVT(); 959 960 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 961 ST = ST; 962 Ptr = ST->getBasePtr(); 963 VT = ST->getStoredVT(); 964 } else 965 return false; 966 967 // PowerPC doesn't have preinc load/store instructions for vectors. 968 if (MVT::isVector(VT)) 969 return false; 970 971 // TODO: Check reg+reg first. 972 973 // LDU/STU use reg+imm*4, others use reg+imm. 974 if (VT != MVT::i64) { 975 // reg + imm 976 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 977 return false; 978 } else { 979 // reg + imm * 4. 980 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 981 return false; 982 } 983 984 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 985 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 986 // sext i32 to i64 when addr mode is r+i. 987 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 && 988 LD->getExtensionType() == ISD::SEXTLOAD && 989 isa<ConstantSDNode>(Offset)) 990 return false; 991 } 992 993 AM = ISD::PRE_INC; 994 return true; 995} 996 997//===----------------------------------------------------------------------===// 998// LowerOperation implementation 999//===----------------------------------------------------------------------===// 1000 1001static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 1002 MVT::ValueType PtrVT = Op.getValueType(); 1003 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1004 Constant *C = CP->getConstVal(); 1005 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1006 SDOperand Zero = DAG.getConstant(0, PtrVT); 1007 1008 const TargetMachine &TM = DAG.getTarget(); 1009 1010 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 1011 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 1012 1013 // If this is a non-darwin platform, we don't support non-static relo models 1014 // yet. 1015 if (TM.getRelocationModel() == Reloc::Static || 1016 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1017 // Generate non-pic code that has direct accesses to the constant pool. 1018 // The address of the global is just (hi(&g)+lo(&g)). 1019 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1020 } 1021 1022 if (TM.getRelocationModel() == Reloc::PIC_) { 1023 // With PIC, the first instruction is actually "GR+hi(&G)". 1024 Hi = DAG.getNode(ISD::ADD, PtrVT, 1025 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1026 } 1027 1028 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1029 return Lo; 1030} 1031 1032static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 1033 MVT::ValueType PtrVT = Op.getValueType(); 1034 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1035 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1036 SDOperand Zero = DAG.getConstant(0, PtrVT); 1037 1038 const TargetMachine &TM = DAG.getTarget(); 1039 1040 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 1041 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 1042 1043 // If this is a non-darwin platform, we don't support non-static relo models 1044 // yet. 1045 if (TM.getRelocationModel() == Reloc::Static || 1046 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1047 // Generate non-pic code that has direct accesses to the constant pool. 1048 // The address of the global is just (hi(&g)+lo(&g)). 1049 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1050 } 1051 1052 if (TM.getRelocationModel() == Reloc::PIC_) { 1053 // With PIC, the first instruction is actually "GR+hi(&G)". 1054 Hi = DAG.getNode(ISD::ADD, PtrVT, 1055 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1056 } 1057 1058 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1059 return Lo; 1060} 1061 1062static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 1063 assert(0 && "TLS not implemented for PPC."); 1064} 1065 1066static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 1067 MVT::ValueType PtrVT = Op.getValueType(); 1068 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1069 GlobalValue *GV = GSDN->getGlobal(); 1070 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1071 SDOperand Zero = DAG.getConstant(0, PtrVT); 1072 1073 const TargetMachine &TM = DAG.getTarget(); 1074 1075 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 1076 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1077 1078 // If this is a non-darwin platform, we don't support non-static relo models 1079 // yet. 1080 if (TM.getRelocationModel() == Reloc::Static || 1081 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1082 // Generate non-pic code that has direct accesses to globals. 1083 // The address of the global is just (hi(&g)+lo(&g)). 1084 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1085 } 1086 1087 if (TM.getRelocationModel() == Reloc::PIC_) { 1088 // With PIC, the first instruction is actually "GR+hi(&G)". 1089 Hi = DAG.getNode(ISD::ADD, PtrVT, 1090 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1091 } 1092 1093 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1094 1095 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1096 return Lo; 1097 1098 // If the global is weak or external, we have to go through the lazy 1099 // resolution stub. 1100 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1101} 1102 1103static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 1104 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1105 1106 // If we're comparing for equality to zero, expose the fact that this is 1107 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1108 // fold the new nodes. 1109 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1110 if (C->isNullValue() && CC == ISD::SETEQ) { 1111 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1112 SDOperand Zext = Op.getOperand(0); 1113 if (VT < MVT::i32) { 1114 VT = MVT::i32; 1115 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1116 } 1117 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1118 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1119 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1120 DAG.getConstant(Log2b, MVT::i32)); 1121 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1122 } 1123 // Leave comparisons against 0 and -1 alone for now, since they're usually 1124 // optimized. FIXME: revisit this when we can custom lower all setcc 1125 // optimizations. 1126 if (C->isAllOnesValue() || C->isNullValue()) 1127 return SDOperand(); 1128 } 1129 1130 // If we have an integer seteq/setne, turn it into a compare against zero 1131 // by xor'ing the rhs with the lhs, which is faster than setting a 1132 // condition register, reading it back out, and masking the correct bit. The 1133 // normal approach here uses sub to do this instead of xor. Using xor exposes 1134 // the result to other bit-twiddling opportunities. 1135 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1136 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1137 MVT::ValueType VT = Op.getValueType(); 1138 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1139 Op.getOperand(1)); 1140 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1141 } 1142 return SDOperand(); 1143} 1144 1145static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, 1146 int VarArgsFrameIndex, 1147 int VarArgsStackOffset, 1148 unsigned VarArgsNumGPR, 1149 unsigned VarArgsNumFPR, 1150 const PPCSubtarget &Subtarget) { 1151 1152 assert(0 && "VAARG in ELF32 ABI not implemented yet!"); 1153} 1154 1155static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 1156 int VarArgsFrameIndex, 1157 int VarArgsStackOffset, 1158 unsigned VarArgsNumGPR, 1159 unsigned VarArgsNumFPR, 1160 const PPCSubtarget &Subtarget) { 1161 1162 if (Subtarget.isMachoABI()) { 1163 // vastart just stores the address of the VarArgsFrameIndex slot into the 1164 // memory location argument. 1165 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1166 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1167 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1168 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 1169 SV->getOffset()); 1170 } 1171 1172 // For ELF 32 ABI we follow the layout of the va_list struct. 1173 // We suppose the given va_list is already allocated. 1174 // 1175 // typedef struct { 1176 // char gpr; /* index into the array of 8 GPRs 1177 // * stored in the register save area 1178 // * gpr=0 corresponds to r3, 1179 // * gpr=1 to r4, etc. 1180 // */ 1181 // char fpr; /* index into the array of 8 FPRs 1182 // * stored in the register save area 1183 // * fpr=0 corresponds to f1, 1184 // * fpr=1 to f2, etc. 1185 // */ 1186 // char *overflow_arg_area; 1187 // /* location on stack that holds 1188 // * the next overflow argument 1189 // */ 1190 // char *reg_save_area; 1191 // /* where r3:r10 and f1:f8 (if saved) 1192 // * are stored 1193 // */ 1194 // } va_list[1]; 1195 1196 1197 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); 1198 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); 1199 1200 1201 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1202 1203 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1204 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1205 1206 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, 1207 PtrVT); 1208 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1, 1209 PtrVT); 1210 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT); 1211 1212 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1213 1214 // Store first byte : number of int regs 1215 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, 1216 Op.getOperand(1), SV->getValue(), 1217 SV->getOffset()); 1218 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), 1219 ConstFPROffset); 1220 1221 // Store second byte : number of float regs 1222 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, 1223 SV->getValue(), SV->getOffset()); 1224 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); 1225 1226 // Store second word : arguments given on stack 1227 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr, 1228 SV->getValue(), SV->getOffset()); 1229 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); 1230 1231 // Store third word : arguments given in registers 1232 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(), 1233 SV->getOffset()); 1234 1235} 1236 1237#include "PPCGenCallingConv.inc" 1238 1239/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1240/// depending on which subtarget is selected. 1241static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1242 if (Subtarget.isMachoABI()) { 1243 static const unsigned FPR[] = { 1244 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1245 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1246 }; 1247 return FPR; 1248 } 1249 1250 1251 static const unsigned FPR[] = { 1252 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1253 PPC::F8 1254 }; 1255 return FPR; 1256} 1257 1258static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 1259 int &VarArgsFrameIndex, 1260 int &VarArgsStackOffset, 1261 unsigned &VarArgsNumGPR, 1262 unsigned &VarArgsNumFPR, 1263 const PPCSubtarget &Subtarget) { 1264 // TODO: add description of PPC stack frame format, or at least some docs. 1265 // 1266 MachineFunction &MF = DAG.getMachineFunction(); 1267 MachineFrameInfo *MFI = MF.getFrameInfo(); 1268 SSARegMap *RegMap = MF.getSSARegMap(); 1269 SmallVector<SDOperand, 8> ArgValues; 1270 SDOperand Root = Op.getOperand(0); 1271 1272 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1273 bool isPPC64 = PtrVT == MVT::i64; 1274 bool isMachoABI = Subtarget.isMachoABI(); 1275 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1276 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1277 1278 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1279 1280 static const unsigned GPR_32[] = { // 32-bit registers. 1281 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1282 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1283 }; 1284 static const unsigned GPR_64[] = { // 64-bit registers. 1285 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1286 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1287 }; 1288 1289 static const unsigned *FPR = GetFPR(Subtarget); 1290 1291 static const unsigned VR[] = { 1292 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1293 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1294 }; 1295 1296 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1297 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; 1298 const unsigned Num_VR_Regs = array_lengthof( VR); 1299 1300 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1301 1302 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1303 1304 // Add DAG nodes to load the arguments or copy them out of registers. On 1305 // entry to a function on PPC, the arguments start after the linkage area, 1306 // although the first ones are often in registers. 1307 // 1308 // In the ELF 32 ABI, GPRs and stack are double word align: an argument 1309 // represented with two words (long long or double) must be copied to an 1310 // even GPR_idx value or to an even ArgOffset value. 1311 1312 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1313 SDOperand ArgVal; 1314 bool needsLoad = false; 1315 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 1316 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 1317 unsigned ArgSize = ObjSize; 1318 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue(); 1319 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1320 // See if next argument requires stack alignment in ELF 1321 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) && 1322 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) && 1323 (!(Flags & AlignFlag))); 1324 1325 unsigned CurArgOffset = ArgOffset; 1326 switch (ObjectVT) { 1327 default: assert(0 && "Unhandled argument type!"); 1328 case MVT::i32: 1329 // Double word align in ELF 1330 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1331 if (GPR_idx != Num_GPR_Regs) { 1332 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1333 MF.addLiveIn(GPR[GPR_idx], VReg); 1334 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1335 ++GPR_idx; 1336 } else { 1337 needsLoad = true; 1338 ArgSize = PtrByteSize; 1339 } 1340 // Stack align in ELF 1341 if (needsLoad && Expand && isELF32_ABI) 1342 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1343 // All int arguments reserve stack space in Macho ABI. 1344 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1345 break; 1346 1347 case MVT::i64: // PPC64 1348 if (GPR_idx != Num_GPR_Regs) { 1349 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1350 MF.addLiveIn(GPR[GPR_idx], VReg); 1351 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1352 ++GPR_idx; 1353 } else { 1354 needsLoad = true; 1355 } 1356 // All int arguments reserve stack space in Macho ABI. 1357 if (isMachoABI || needsLoad) ArgOffset += 8; 1358 break; 1359 1360 case MVT::f32: 1361 case MVT::f64: 1362 // Every 4 bytes of argument space consumes one of the GPRs available for 1363 // argument passing. 1364 if (GPR_idx != Num_GPR_Regs && isMachoABI) { 1365 ++GPR_idx; 1366 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1367 ++GPR_idx; 1368 } 1369 if (FPR_idx != Num_FPR_Regs) { 1370 unsigned VReg; 1371 if (ObjectVT == MVT::f32) 1372 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 1373 else 1374 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1375 MF.addLiveIn(FPR[FPR_idx], VReg); 1376 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1377 ++FPR_idx; 1378 } else { 1379 needsLoad = true; 1380 } 1381 1382 // Stack align in ELF 1383 if (needsLoad && Expand && isELF32_ABI) 1384 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1385 // All FP arguments reserve stack space in Macho ABI. 1386 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1387 break; 1388 case MVT::v4f32: 1389 case MVT::v4i32: 1390 case MVT::v8i16: 1391 case MVT::v16i8: 1392 // Note that vector arguments in registers don't reserve stack space. 1393 if (VR_idx != Num_VR_Regs) { 1394 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); 1395 MF.addLiveIn(VR[VR_idx], VReg); 1396 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1397 ++VR_idx; 1398 } else { 1399 // This should be simple, but requires getting 16-byte aligned stack 1400 // values. 1401 assert(0 && "Loading VR argument not implemented yet!"); 1402 needsLoad = true; 1403 } 1404 break; 1405 } 1406 1407 // We need to load the argument to a virtual register if we determined above 1408 // that we ran out of physical registers of the appropriate type 1409 if (needsLoad) { 1410 // If the argument is actually used, emit a load from the right stack 1411 // slot. 1412 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 1413 int FI = MFI->CreateFixedObject(ObjSize, 1414 CurArgOffset + (ArgSize - ObjSize)); 1415 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1416 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1417 } else { 1418 // Don't emit a dead load. 1419 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); 1420 } 1421 } 1422 1423 ArgValues.push_back(ArgVal); 1424 } 1425 1426 // If the function takes variable number of arguments, make a frame index for 1427 // the start of the first vararg value... for expansion of llvm.va_start. 1428 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1429 if (isVarArg) { 1430 1431 int depth; 1432 if (isELF32_ABI) { 1433 VarArgsNumGPR = GPR_idx; 1434 VarArgsNumFPR = FPR_idx; 1435 1436 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame 1437 // pointer. 1438 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 + 1439 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 + 1440 MVT::getSizeInBits(PtrVT)/8); 1441 1442 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1443 ArgOffset); 1444 1445 } 1446 else 1447 depth = ArgOffset; 1448 1449 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1450 depth); 1451 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1452 1453 SmallVector<SDOperand, 8> MemOps; 1454 1455 // In ELF 32 ABI, the fixed integer arguments of a variadic function are 1456 // stored to the VarArgsFrameIndex on the stack. 1457 if (isELF32_ABI) { 1458 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { 1459 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT); 1460 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1461 MemOps.push_back(Store); 1462 // Increment the address by four for the next argument to store 1463 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1464 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1465 } 1466 } 1467 1468 // If this function is vararg, store any remaining integer argument regs 1469 // to their spots on the stack so that they may be loaded by deferencing the 1470 // result of va_next. 1471 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1472 unsigned VReg; 1473 if (isPPC64) 1474 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1475 else 1476 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1477 1478 MF.addLiveIn(GPR[GPR_idx], VReg); 1479 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1480 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1481 MemOps.push_back(Store); 1482 // Increment the address by four for the next argument to store 1483 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1484 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1485 } 1486 1487 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex 1488 // on the stack. 1489 if (isELF32_ABI) { 1490 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { 1491 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); 1492 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1493 MemOps.push_back(Store); 1494 // Increment the address by eight for the next argument to store 1495 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1496 PtrVT); 1497 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1498 } 1499 1500 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { 1501 unsigned VReg; 1502 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1503 1504 MF.addLiveIn(FPR[FPR_idx], VReg); 1505 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); 1506 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1507 MemOps.push_back(Store); 1508 // Increment the address by eight for the next argument to store 1509 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1510 PtrVT); 1511 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1512 } 1513 } 1514 1515 if (!MemOps.empty()) 1516 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1517 } 1518 1519 ArgValues.push_back(Root); 1520 1521 // Return the new list of results. 1522 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1523 Op.Val->value_end()); 1524 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1525} 1526 1527/// isCallCompatibleAddress - Return the immediate to use if the specified 1528/// 32-bit value is representable in the immediate field of a BxA instruction. 1529static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 1530 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1531 if (!C) return 0; 1532 1533 int Addr = C->getValue(); 1534 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1535 (Addr << 6 >> 6) != Addr) 1536 return 0; // Top 6 bits have to be sext of immediate. 1537 1538 return DAG.getConstant((int)C->getValue() >> 2, 1539 DAG.getTargetLoweringInfo().getPointerTy()).Val; 1540} 1541 1542 1543static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, 1544 const PPCSubtarget &Subtarget) { 1545 SDOperand Chain = Op.getOperand(0); 1546 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1547 SDOperand Callee = Op.getOperand(4); 1548 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1549 1550 bool isMachoABI = Subtarget.isMachoABI(); 1551 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1552 1553 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1554 bool isPPC64 = PtrVT == MVT::i64; 1555 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1556 1557 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1558 // SelectExpr to use to put the arguments in the appropriate registers. 1559 std::vector<SDOperand> args_to_use; 1560 1561 // Count how many bytes are to be pushed on the stack, including the linkage 1562 // area, and parameter passing area. We start with 24/48 bytes, which is 1563 // prereserved space for [SP][CR][LR][3 x unused]. 1564 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1565 1566 // Add up all the space actually used. 1567 for (unsigned i = 0; i != NumOps; ++i) { 1568 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 1569 ArgSize = std::max(ArgSize, PtrByteSize); 1570 NumBytes += ArgSize; 1571 } 1572 1573 // The prolog code of the callee may store up to 8 GPR argument registers to 1574 // the stack, allowing va_start to index over them in memory if its varargs. 1575 // Because we cannot tell if this is needed on the caller side, we have to 1576 // conservatively assume that it is needed. As such, make sure we have at 1577 // least enough stack space for the caller to store the 8 GPRs. 1578 NumBytes = std::max(NumBytes, 1579 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1580 1581 // Adjust the stack pointer for the new arguments... 1582 // These operations are automatically eliminated by the prolog/epilog pass 1583 Chain = DAG.getCALLSEQ_START(Chain, 1584 DAG.getConstant(NumBytes, PtrVT)); 1585 1586 // Set up a copy of the stack pointer for use loading and storing any 1587 // arguments that may not fit in the registers available for argument 1588 // passing. 1589 SDOperand StackPtr; 1590 if (isPPC64) 1591 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 1592 else 1593 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1594 1595 // Figure out which arguments are going to go in registers, and which in 1596 // memory. Also, if this is a vararg function, floating point operations 1597 // must be stored to our stack, and loaded into integer regs as well, if 1598 // any integer regs are available for argument passing. 1599 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1600 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1601 1602 static const unsigned GPR_32[] = { // 32-bit registers. 1603 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1604 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1605 }; 1606 static const unsigned GPR_64[] = { // 64-bit registers. 1607 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1608 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1609 }; 1610 static const unsigned *FPR = GetFPR(Subtarget); 1611 1612 static const unsigned VR[] = { 1613 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1614 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1615 }; 1616 const unsigned NumGPRs = array_lengthof(GPR_32); 1617 const unsigned NumFPRs = isMachoABI ? 13 : 8; 1618 const unsigned NumVRs = array_lengthof( VR); 1619 1620 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1621 1622 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1623 SmallVector<SDOperand, 8> MemOpChains; 1624 for (unsigned i = 0; i != NumOps; ++i) { 1625 bool inMem = false; 1626 SDOperand Arg = Op.getOperand(5+2*i); 1627 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1628 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1629 // See if next argument requires stack alignment in ELF 1630 unsigned next = 5+2*(i+1)+1; 1631 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) && 1632 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) && 1633 (!(Flags & AlignFlag))); 1634 1635 // PtrOff will be used to store the current argument to the stack if a 1636 // register cannot be found for it. 1637 SDOperand PtrOff; 1638 1639 // Stack align in ELF 32 1640 if (isELF32_ABI && Expand) 1641 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, 1642 StackPtr.getValueType()); 1643 else 1644 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1645 1646 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1647 1648 // On PPC64, promote integers to 64-bit values. 1649 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1650 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1651 1652 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1653 } 1654 1655 switch (Arg.getValueType()) { 1656 default: assert(0 && "Unexpected ValueType for argument!"); 1657 case MVT::i32: 1658 case MVT::i64: 1659 // Double word align in ELF 1660 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2); 1661 if (GPR_idx != NumGPRs) { 1662 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1663 } else { 1664 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1665 inMem = true; 1666 } 1667 if (inMem || isMachoABI) { 1668 // Stack align in ELF 1669 if (isELF32_ABI && Expand) 1670 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1671 1672 ArgOffset += PtrByteSize; 1673 } 1674 break; 1675 case MVT::f32: 1676 case MVT::f64: 1677 if (isVarArg) { 1678 // Float varargs need to be promoted to double. 1679 if (Arg.getValueType() == MVT::f32) 1680 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); 1681 } 1682 1683 if (FPR_idx != NumFPRs) { 1684 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1685 1686 if (isVarArg) { 1687 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1688 MemOpChains.push_back(Store); 1689 1690 // Float varargs are always shadowed in available integer registers 1691 if (GPR_idx != NumGPRs) { 1692 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1693 MemOpChains.push_back(Load.getValue(1)); 1694 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1695 Load)); 1696 } 1697 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 1698 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1699 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1700 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1701 MemOpChains.push_back(Load.getValue(1)); 1702 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1703 Load)); 1704 } 1705 } else { 1706 // If we have any FPRs remaining, we may also have GPRs remaining. 1707 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1708 // GPRs. 1709 if (isMachoABI) { 1710 if (GPR_idx != NumGPRs) 1711 ++GPR_idx; 1712 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 1713 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 1714 ++GPR_idx; 1715 } 1716 } 1717 } else { 1718 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1719 inMem = true; 1720 } 1721 if (inMem || isMachoABI) { 1722 // Stack align in ELF 1723 if (isELF32_ABI && Expand) 1724 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1725 if (isPPC64) 1726 ArgOffset += 8; 1727 else 1728 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1729 } 1730 break; 1731 case MVT::v4f32: 1732 case MVT::v4i32: 1733 case MVT::v8i16: 1734 case MVT::v16i8: 1735 assert(!isVarArg && "Don't support passing vectors to varargs yet!"); 1736 assert(VR_idx != NumVRs && 1737 "Don't support passing more than 12 vector args yet!"); 1738 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 1739 break; 1740 } 1741 } 1742 if (!MemOpChains.empty()) 1743 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1744 &MemOpChains[0], MemOpChains.size()); 1745 1746 // Build a sequence of copy-to-reg nodes chained together with token chain 1747 // and flag operands which copy the outgoing args into the appropriate regs. 1748 SDOperand InFlag; 1749 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1750 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1751 InFlag); 1752 InFlag = Chain.getValue(1); 1753 } 1754 1755 // With the ELF 32 ABI, set CR6 to true if this is a vararg call. 1756 if (isVarArg && isELF32_ABI) { 1757 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0); 1758 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag); 1759 InFlag = Chain.getValue(1); 1760 } 1761 1762 std::vector<MVT::ValueType> NodeTys; 1763 NodeTys.push_back(MVT::Other); // Returns a chain 1764 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1765 1766 SmallVector<SDOperand, 8> Ops; 1767 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 1768 1769 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1770 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1771 // node so that legalize doesn't hack it. 1772 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1773 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 1774 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1775 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 1776 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 1777 // If this is an absolute destination address, use the munged value. 1778 Callee = SDOperand(Dest, 0); 1779 else { 1780 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 1781 // to do the call, we can't use PPCISD::CALL. 1782 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 1783 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 1784 InFlag = Chain.getValue(1); 1785 1786 // Copy the callee address into R12 on darwin. 1787 if (isMachoABI) { 1788 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); 1789 InFlag = Chain.getValue(1); 1790 } 1791 1792 NodeTys.clear(); 1793 NodeTys.push_back(MVT::Other); 1794 NodeTys.push_back(MVT::Flag); 1795 Ops.push_back(Chain); 1796 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 1797 Callee.Val = 0; 1798 } 1799 1800 // If this is a direct call, pass the chain and the callee. 1801 if (Callee.Val) { 1802 Ops.push_back(Chain); 1803 Ops.push_back(Callee); 1804 } 1805 1806 // Add argument registers to the end of the list so that they are known live 1807 // into the call. 1808 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1809 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1810 RegsToPass[i].second.getValueType())); 1811 1812 if (InFlag.Val) 1813 Ops.push_back(InFlag); 1814 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 1815 InFlag = Chain.getValue(1); 1816 1817 Chain = DAG.getCALLSEQ_END(Chain, 1818 DAG.getConstant(NumBytes, PtrVT), 1819 DAG.getConstant(0, PtrVT), 1820 InFlag); 1821 if (Op.Val->getValueType(0) != MVT::Other) 1822 InFlag = Chain.getValue(1); 1823 1824 SDOperand ResultVals[3]; 1825 unsigned NumResults = 0; 1826 NodeTys.clear(); 1827 1828 // If the call has results, copy the values out of the ret val registers. 1829 switch (Op.Val->getValueType(0)) { 1830 default: assert(0 && "Unexpected ret value!"); 1831 case MVT::Other: break; 1832 case MVT::i32: 1833 if (Op.Val->getValueType(1) == MVT::i32) { 1834 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1835 ResultVals[0] = Chain.getValue(0); 1836 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, 1837 Chain.getValue(2)).getValue(1); 1838 ResultVals[1] = Chain.getValue(0); 1839 NumResults = 2; 1840 NodeTys.push_back(MVT::i32); 1841 } else { 1842 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1843 ResultVals[0] = Chain.getValue(0); 1844 NumResults = 1; 1845 } 1846 NodeTys.push_back(MVT::i32); 1847 break; 1848 case MVT::i64: 1849 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 1850 ResultVals[0] = Chain.getValue(0); 1851 NumResults = 1; 1852 NodeTys.push_back(MVT::i64); 1853 break; 1854 case MVT::f64: 1855 if (Op.Val->getValueType(1) == MVT::f64) { 1856 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1); 1857 ResultVals[0] = Chain.getValue(0); 1858 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64, 1859 Chain.getValue(2)).getValue(1); 1860 ResultVals[1] = Chain.getValue(0); 1861 NumResults = 2; 1862 NodeTys.push_back(MVT::f64); 1863 NodeTys.push_back(MVT::f64); 1864 break; 1865 } 1866 // else fall through 1867 case MVT::f32: 1868 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 1869 InFlag).getValue(1); 1870 ResultVals[0] = Chain.getValue(0); 1871 NumResults = 1; 1872 NodeTys.push_back(Op.Val->getValueType(0)); 1873 break; 1874 case MVT::v4f32: 1875 case MVT::v4i32: 1876 case MVT::v8i16: 1877 case MVT::v16i8: 1878 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 1879 InFlag).getValue(1); 1880 ResultVals[0] = Chain.getValue(0); 1881 NumResults = 1; 1882 NodeTys.push_back(Op.Val->getValueType(0)); 1883 break; 1884 } 1885 1886 NodeTys.push_back(MVT::Other); 1887 1888 // If the function returns void, just return the chain. 1889 if (NumResults == 0) 1890 return Chain; 1891 1892 // Otherwise, merge everything together with a MERGE_VALUES node. 1893 ResultVals[NumResults++] = Chain; 1894 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1895 ResultVals, NumResults); 1896 return Res.getValue(Op.ResNo); 1897} 1898 1899static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { 1900 SmallVector<CCValAssign, 16> RVLocs; 1901 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 1902 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1903 CCState CCInfo(CC, isVarArg, TM, RVLocs); 1904 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC); 1905 1906 // If this is the first return lowered for this function, add the regs to the 1907 // liveout set for the function. 1908 if (DAG.getMachineFunction().liveout_empty()) { 1909 for (unsigned i = 0; i != RVLocs.size(); ++i) 1910 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); 1911 } 1912 1913 SDOperand Chain = Op.getOperand(0); 1914 SDOperand Flag; 1915 1916 // Copy the result values into the output registers. 1917 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1918 CCValAssign &VA = RVLocs[i]; 1919 assert(VA.isRegLoc() && "Can only return in registers!"); 1920 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 1921 Flag = Chain.getValue(1); 1922 } 1923 1924 if (Flag.Val) 1925 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); 1926 else 1927 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); 1928} 1929 1930static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, 1931 const PPCSubtarget &Subtarget) { 1932 // When we pop the dynamic allocation we need to restore the SP link. 1933 1934 // Get the corect type for pointers. 1935 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1936 1937 // Construct the stack pointer operand. 1938 bool IsPPC64 = Subtarget.isPPC64(); 1939 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 1940 SDOperand StackPtr = DAG.getRegister(SP, PtrVT); 1941 1942 // Get the operands for the STACKRESTORE. 1943 SDOperand Chain = Op.getOperand(0); 1944 SDOperand SaveSP = Op.getOperand(1); 1945 1946 // Load the old link SP. 1947 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 1948 1949 // Restore the stack pointer. 1950 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 1951 1952 // Store the old link SP. 1953 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 1954} 1955 1956static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, 1957 const PPCSubtarget &Subtarget) { 1958 MachineFunction &MF = DAG.getMachineFunction(); 1959 bool IsPPC64 = Subtarget.isPPC64(); 1960 bool isMachoABI = Subtarget.isMachoABI(); 1961 1962 // Get current frame pointer save index. The users of this index will be 1963 // primarily DYNALLOC instructions. 1964 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1965 int FPSI = FI->getFramePointerSaveIndex(); 1966 1967 // If the frame pointer save index hasn't been defined yet. 1968 if (!FPSI) { 1969 // Find out what the fix offset of the frame pointer save area. 1970 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 1971 1972 // Allocate the frame index for frame pointer save area. 1973 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 1974 // Save the result. 1975 FI->setFramePointerSaveIndex(FPSI); 1976 } 1977 1978 // Get the inputs. 1979 SDOperand Chain = Op.getOperand(0); 1980 SDOperand Size = Op.getOperand(1); 1981 1982 // Get the corect type for pointers. 1983 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1984 // Negate the size. 1985 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, 1986 DAG.getConstant(0, PtrVT), Size); 1987 // Construct a node for the frame pointer save index. 1988 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); 1989 // Build a DYNALLOC node. 1990 SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; 1991 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 1992 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 1993} 1994 1995 1996/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 1997/// possible. 1998static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 1999 // Not FP? Not a fsel. 2000 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 2001 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 2002 return SDOperand(); 2003 2004 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2005 2006 // Cannot handle SETEQ/SETNE. 2007 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 2008 2009 MVT::ValueType ResVT = Op.getValueType(); 2010 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 2011 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2012 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 2013 2014 // If the RHS of the comparison is a 0.0, we don't need to do the 2015 // subtraction at all. 2016 if (isFloatingPointZero(RHS)) 2017 switch (CC) { 2018 default: break; // SETUO etc aren't handled by fsel. 2019 case ISD::SETULT: 2020 case ISD::SETOLT: 2021 case ISD::SETLT: 2022 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2023 case ISD::SETUGE: 2024 case ISD::SETOGE: 2025 case ISD::SETGE: 2026 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2027 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2028 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 2029 case ISD::SETUGT: 2030 case ISD::SETOGT: 2031 case ISD::SETGT: 2032 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2033 case ISD::SETULE: 2034 case ISD::SETOLE: 2035 case ISD::SETLE: 2036 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2037 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2038 return DAG.getNode(PPCISD::FSEL, ResVT, 2039 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 2040 } 2041 2042 SDOperand Cmp; 2043 switch (CC) { 2044 default: break; // SETUO etc aren't handled by fsel. 2045 case ISD::SETULT: 2046 case ISD::SETOLT: 2047 case ISD::SETLT: 2048 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2049 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2050 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2051 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2052 case ISD::SETUGE: 2053 case ISD::SETOGE: 2054 case ISD::SETGE: 2055 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2056 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2057 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2058 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2059 case ISD::SETUGT: 2060 case ISD::SETOGT: 2061 case ISD::SETGT: 2062 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2063 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2064 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2065 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2066 case ISD::SETULE: 2067 case ISD::SETOLE: 2068 case ISD::SETLE: 2069 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2070 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2071 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2072 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2073 } 2074 return SDOperand(); 2075} 2076 2077// FIXME: Split this code up when LegalizeDAGTypes lands. 2078static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 2079 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 2080 SDOperand Src = Op.getOperand(0); 2081 if (Src.getValueType() == MVT::f32) 2082 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 2083 2084 SDOperand Tmp; 2085 switch (Op.getValueType()) { 2086 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 2087 case MVT::i32: 2088 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 2089 break; 2090 case MVT::i64: 2091 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 2092 break; 2093 } 2094 2095 // Convert the FP value to an int value through memory. 2096 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64); 2097 2098 // Emit a store to the stack slot. 2099 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); 2100 2101 // Result is a load from the stack slot. If loading 4 bytes, make sure to 2102 // add in a bias. 2103 if (Op.getValueType() == MVT::i32) 2104 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, 2105 DAG.getConstant(4, FIPtr.getValueType())); 2106 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); 2107} 2108 2109static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) { 2110 assert(Op.getValueType() == MVT::ppcf128); 2111 SDNode *Node = Op.Val; 2112 assert(Node->getOperand(0).getValueType() == MVT::ppcf128); 2113 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR); 2114 SDOperand Lo = Node->getOperand(0).Val->getOperand(0); 2115 SDOperand Hi = Node->getOperand(0).Val->getOperand(1); 2116 2117 // This sequence changes FPSCR to do round-to-zero, adds the two halves 2118 // of the long double, and puts FPSCR back the way it was. We do not 2119 // actually model FPSCR. 2120 std::vector<MVT::ValueType> NodeTys; 2121 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg; 2122 2123 NodeTys.push_back(MVT::f64); // Return register 2124 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 2125 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 2126 MFFSreg = Result.getValue(0); 2127 InFlag = Result.getValue(1); 2128 2129 NodeTys.clear(); 2130 NodeTys.push_back(MVT::Flag); // Returns a flag 2131 Ops[0] = DAG.getConstant(31, MVT::i32); 2132 Ops[1] = InFlag; 2133 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); 2134 InFlag = Result.getValue(0); 2135 2136 NodeTys.clear(); 2137 NodeTys.push_back(MVT::Flag); // Returns a flag 2138 Ops[0] = DAG.getConstant(30, MVT::i32); 2139 Ops[1] = InFlag; 2140 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); 2141 InFlag = Result.getValue(0); 2142 2143 NodeTys.clear(); 2144 NodeTys.push_back(MVT::f64); // result of add 2145 NodeTys.push_back(MVT::Flag); // Returns a flag 2146 Ops[0] = Lo; 2147 Ops[1] = Hi; 2148 Ops[2] = InFlag; 2149 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); 2150 FPreg = Result.getValue(0); 2151 InFlag = Result.getValue(1); 2152 2153 NodeTys.clear(); 2154 NodeTys.push_back(MVT::f64); 2155 Ops[0] = DAG.getConstant(1, MVT::i32); 2156 Ops[1] = MFFSreg; 2157 Ops[2] = FPreg; 2158 Ops[3] = InFlag; 2159 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); 2160 FPreg = Result.getValue(0); 2161 2162 // We know the low half is about to be thrown away, so just use something 2163 // convenient. 2164 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); 2165} 2166 2167static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 2168 if (Op.getOperand(0).getValueType() == MVT::i64) { 2169 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 2170 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 2171 if (Op.getValueType() == MVT::f32) 2172 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 2173 return FP; 2174 } 2175 2176 assert(Op.getOperand(0).getValueType() == MVT::i32 && 2177 "Unhandled SINT_TO_FP type in custom expander!"); 2178 // Since we only generate this in 64-bit mode, we can take advantage of 2179 // 64-bit registers. In particular, sign extend the input value into the 2180 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 2181 // then lfd it and fcfid it. 2182 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2183 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 2184 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2185 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2186 2187 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 2188 Op.getOperand(0)); 2189 2190 // STD the extended value into the stack slot. 2191 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 2192 DAG.getEntryNode(), Ext64, FIdx, 2193 DAG.getSrcValue(NULL)); 2194 // Load the value as a double. 2195 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 2196 2197 // FCFID it and return it. 2198 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 2199 if (Op.getValueType() == MVT::f32) 2200 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 2201 return FP; 2202} 2203 2204static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2205 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2206 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 2207 2208 // Expand into a bunch of logical ops. Note that these ops 2209 // depend on the PPC behavior for oversized shift amounts. 2210 SDOperand Lo = Op.getOperand(0); 2211 SDOperand Hi = Op.getOperand(1); 2212 SDOperand Amt = Op.getOperand(2); 2213 2214 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2215 DAG.getConstant(32, MVT::i32), Amt); 2216 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 2217 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 2218 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2219 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2220 DAG.getConstant(-32U, MVT::i32)); 2221 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 2222 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2223 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 2224 SDOperand OutOps[] = { OutLo, OutHi }; 2225 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2226 OutOps, 2); 2227} 2228 2229static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2230 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2231 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); 2232 2233 // Otherwise, expand into a bunch of logical ops. Note that these ops 2234 // depend on the PPC behavior for oversized shift amounts. 2235 SDOperand Lo = Op.getOperand(0); 2236 SDOperand Hi = Op.getOperand(1); 2237 SDOperand Amt = Op.getOperand(2); 2238 2239 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2240 DAG.getConstant(32, MVT::i32), Amt); 2241 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2242 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2243 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2244 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2245 DAG.getConstant(-32U, MVT::i32)); 2246 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 2247 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2248 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 2249 SDOperand OutOps[] = { OutLo, OutHi }; 2250 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2251 OutOps, 2); 2252} 2253 2254static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 2255 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2256 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 2257 2258 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 2259 SDOperand Lo = Op.getOperand(0); 2260 SDOperand Hi = Op.getOperand(1); 2261 SDOperand Amt = Op.getOperand(2); 2262 2263 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2264 DAG.getConstant(32, MVT::i32), Amt); 2265 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2266 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2267 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2268 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2269 DAG.getConstant(-32U, MVT::i32)); 2270 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 2271 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 2272 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 2273 Tmp4, Tmp6, ISD::SETLE); 2274 SDOperand OutOps[] = { OutLo, OutHi }; 2275 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2276 OutOps, 2); 2277} 2278 2279//===----------------------------------------------------------------------===// 2280// Vector related lowering. 2281// 2282 2283// If this is a vector of constants or undefs, get the bits. A bit in 2284// UndefBits is set if the corresponding element of the vector is an 2285// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2286// zero. Return true if this is not an array of constants, false if it is. 2287// 2288static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 2289 uint64_t UndefBits[2]) { 2290 // Start with zero'd results. 2291 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 2292 2293 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 2294 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 2295 SDOperand OpVal = BV->getOperand(i); 2296 2297 unsigned PartNo = i >= e/2; // In the upper 128 bits? 2298 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 2299 2300 uint64_t EltBits = 0; 2301 if (OpVal.getOpcode() == ISD::UNDEF) { 2302 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 2303 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 2304 continue; 2305 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 2306 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 2307 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 2308 assert(CN->getValueType(0) == MVT::f32 && 2309 "Only one legal FP vector type!"); 2310 EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); 2311 } else { 2312 // Nonconstant element. 2313 return true; 2314 } 2315 2316 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 2317 } 2318 2319 //printf("%llx %llx %llx %llx\n", 2320 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 2321 return false; 2322} 2323 2324// If this is a splat (repetition) of a value across the whole vector, return 2325// the smallest size that splats it. For example, "0x01010101010101..." is a 2326// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2327// SplatSize = 1 byte. 2328static bool isConstantSplat(const uint64_t Bits128[2], 2329 const uint64_t Undef128[2], 2330 unsigned &SplatBits, unsigned &SplatUndef, 2331 unsigned &SplatSize) { 2332 2333 // Don't let undefs prevent splats from matching. See if the top 64-bits are 2334 // the same as the lower 64-bits, ignoring undefs. 2335 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 2336 return false; // Can't be a splat if two pieces don't match. 2337 2338 uint64_t Bits64 = Bits128[0] | Bits128[1]; 2339 uint64_t Undef64 = Undef128[0] & Undef128[1]; 2340 2341 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 2342 // undefs. 2343 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 2344 return false; // Can't be a splat if two pieces don't match. 2345 2346 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 2347 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 2348 2349 // If the top 16-bits are different than the lower 16-bits, ignoring 2350 // undefs, we have an i32 splat. 2351 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 2352 SplatBits = Bits32; 2353 SplatUndef = Undef32; 2354 SplatSize = 4; 2355 return true; 2356 } 2357 2358 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 2359 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 2360 2361 // If the top 8-bits are different than the lower 8-bits, ignoring 2362 // undefs, we have an i16 splat. 2363 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 2364 SplatBits = Bits16; 2365 SplatUndef = Undef16; 2366 SplatSize = 2; 2367 return true; 2368 } 2369 2370 // Otherwise, we have an 8-bit splat. 2371 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 2372 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 2373 SplatSize = 1; 2374 return true; 2375} 2376 2377/// BuildSplatI - Build a canonical splati of Val with an element size of 2378/// SplatSize. Cast the result to VT. 2379static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 2380 SelectionDAG &DAG) { 2381 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 2382 2383 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 2384 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 2385 }; 2386 2387 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 2388 2389 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 2390 if (Val == -1) 2391 SplatSize = 1; 2392 2393 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 2394 2395 // Build a canonical splat for this value. 2396 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT)); 2397 SmallVector<SDOperand, 8> Ops; 2398 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 2399 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 2400 &Ops[0], Ops.size()); 2401 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 2402} 2403 2404/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 2405/// specified intrinsic ID. 2406static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 2407 SelectionDAG &DAG, 2408 MVT::ValueType DestVT = MVT::Other) { 2409 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 2410 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2411 DAG.getConstant(IID, MVT::i32), LHS, RHS); 2412} 2413 2414/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 2415/// specified intrinsic ID. 2416static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 2417 SDOperand Op2, SelectionDAG &DAG, 2418 MVT::ValueType DestVT = MVT::Other) { 2419 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 2420 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2421 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 2422} 2423 2424 2425/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 2426/// amount. The result has the specified value type. 2427static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 2428 MVT::ValueType VT, SelectionDAG &DAG) { 2429 // Force LHS/RHS to be the right type. 2430 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 2431 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 2432 2433 SDOperand Ops[16]; 2434 for (unsigned i = 0; i != 16; ++i) 2435 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 2436 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 2437 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 2438 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 2439} 2440 2441// If this is a case we can't handle, return null and let the default 2442// expansion code take care of it. If we CAN select this case, and if it 2443// selects to a single instruction, return Op. Otherwise, if we can codegen 2444// this case more efficiently than a constant pool load, lower it to the 2445// sequence of ops that should be used. 2446static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2447 // If this is a vector of constants or undefs, get the bits. A bit in 2448 // UndefBits is set if the corresponding element of the vector is an 2449 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2450 // zero. 2451 uint64_t VectorBits[2]; 2452 uint64_t UndefBits[2]; 2453 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 2454 return SDOperand(); // Not a constant vector. 2455 2456 // If this is a splat (repetition) of a value across the whole vector, return 2457 // the smallest size that splats it. For example, "0x01010101010101..." is a 2458 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2459 // SplatSize = 1 byte. 2460 unsigned SplatBits, SplatUndef, SplatSize; 2461 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 2462 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 2463 2464 // First, handle single instruction cases. 2465 2466 // All zeros? 2467 if (SplatBits == 0) { 2468 // Canonicalize all zero vectors to be v4i32. 2469 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 2470 SDOperand Z = DAG.getConstant(0, MVT::i32); 2471 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 2472 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 2473 } 2474 return Op; 2475 } 2476 2477 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 2478 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 2479 if (SextVal >= -16 && SextVal <= 15) 2480 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 2481 2482 2483 // Two instruction sequences. 2484 2485 // If this value is in the range [-32,30] and is even, use: 2486 // tmp = VSPLTI[bhw], result = add tmp, tmp 2487 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 2488 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 2489 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 2490 } 2491 2492 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 2493 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 2494 // for fneg/fabs. 2495 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 2496 // Make -1 and vspltisw -1: 2497 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 2498 2499 // Make the VSLW intrinsic, computing 0x8000_0000. 2500 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 2501 OnesV, DAG); 2502 2503 // xor by OnesV to invert it. 2504 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 2505 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2506 } 2507 2508 // Check to see if this is a wide variety of vsplti*, binop self cases. 2509 unsigned SplatBitSize = SplatSize*8; 2510 static const signed char SplatCsts[] = { 2511 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 2512 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 2513 }; 2514 2515 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 2516 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 2517 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 2518 int i = SplatCsts[idx]; 2519 2520 // Figure out what shift amount will be used by altivec if shifted by i in 2521 // this splat size. 2522 unsigned TypeShiftAmt = i & (SplatBitSize-1); 2523 2524 // vsplti + shl self. 2525 if (SextVal == (i << (int)TypeShiftAmt)) { 2526 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2527 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2528 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 2529 Intrinsic::ppc_altivec_vslw 2530 }; 2531 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2532 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2533 } 2534 2535 // vsplti + srl self. 2536 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2537 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2538 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2539 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 2540 Intrinsic::ppc_altivec_vsrw 2541 }; 2542 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2543 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2544 } 2545 2546 // vsplti + sra self. 2547 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2548 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2549 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2550 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 2551 Intrinsic::ppc_altivec_vsraw 2552 }; 2553 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2554 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2555 } 2556 2557 // vsplti + rol self. 2558 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 2559 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 2560 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2561 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2562 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 2563 Intrinsic::ppc_altivec_vrlw 2564 }; 2565 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2566 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2567 } 2568 2569 // t = vsplti c, result = vsldoi t, t, 1 2570 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 2571 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2572 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 2573 } 2574 // t = vsplti c, result = vsldoi t, t, 2 2575 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 2576 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2577 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 2578 } 2579 // t = vsplti c, result = vsldoi t, t, 3 2580 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 2581 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2582 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 2583 } 2584 } 2585 2586 // Three instruction sequences. 2587 2588 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 2589 if (SextVal >= 0 && SextVal <= 31) { 2590 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 2591 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2592 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); 2593 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2594 } 2595 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 2596 if (SextVal >= -31 && SextVal <= 0) { 2597 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 2598 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2599 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); 2600 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2601 } 2602 } 2603 2604 return SDOperand(); 2605} 2606 2607/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2608/// the specified operations to build the shuffle. 2609static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 2610 SDOperand RHS, SelectionDAG &DAG) { 2611 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2612 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2613 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2614 2615 enum { 2616 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2617 OP_VMRGHW, 2618 OP_VMRGLW, 2619 OP_VSPLTISW0, 2620 OP_VSPLTISW1, 2621 OP_VSPLTISW2, 2622 OP_VSPLTISW3, 2623 OP_VSLDOI4, 2624 OP_VSLDOI8, 2625 OP_VSLDOI12 2626 }; 2627 2628 if (OpNum == OP_COPY) { 2629 if (LHSID == (1*9+2)*9+3) return LHS; 2630 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2631 return RHS; 2632 } 2633 2634 SDOperand OpLHS, OpRHS; 2635 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 2636 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 2637 2638 unsigned ShufIdxs[16]; 2639 switch (OpNum) { 2640 default: assert(0 && "Unknown i32 permute!"); 2641 case OP_VMRGHW: 2642 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 2643 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 2644 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 2645 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 2646 break; 2647 case OP_VMRGLW: 2648 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 2649 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 2650 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 2651 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 2652 break; 2653 case OP_VSPLTISW0: 2654 for (unsigned i = 0; i != 16; ++i) 2655 ShufIdxs[i] = (i&3)+0; 2656 break; 2657 case OP_VSPLTISW1: 2658 for (unsigned i = 0; i != 16; ++i) 2659 ShufIdxs[i] = (i&3)+4; 2660 break; 2661 case OP_VSPLTISW2: 2662 for (unsigned i = 0; i != 16; ++i) 2663 ShufIdxs[i] = (i&3)+8; 2664 break; 2665 case OP_VSPLTISW3: 2666 for (unsigned i = 0; i != 16; ++i) 2667 ShufIdxs[i] = (i&3)+12; 2668 break; 2669 case OP_VSLDOI4: 2670 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 2671 case OP_VSLDOI8: 2672 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 2673 case OP_VSLDOI12: 2674 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 2675 } 2676 SDOperand Ops[16]; 2677 for (unsigned i = 0; i != 16; ++i) 2678 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 2679 2680 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 2681 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2682} 2683 2684/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 2685/// is a shuffle we can handle in a single instruction, return it. Otherwise, 2686/// return the code it can be lowered into. Worst case, it can always be 2687/// lowered into a vperm. 2688static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 2689 SDOperand V1 = Op.getOperand(0); 2690 SDOperand V2 = Op.getOperand(1); 2691 SDOperand PermMask = Op.getOperand(2); 2692 2693 // Cases that are handled by instructions that take permute immediates 2694 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 2695 // selected by the instruction selector. 2696 if (V2.getOpcode() == ISD::UNDEF) { 2697 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 2698 PPC::isSplatShuffleMask(PermMask.Val, 2) || 2699 PPC::isSplatShuffleMask(PermMask.Val, 4) || 2700 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 2701 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 2702 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 2703 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 2704 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 2705 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 2706 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 2707 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 2708 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 2709 return Op; 2710 } 2711 } 2712 2713 // Altivec has a variety of "shuffle immediates" that take two vector inputs 2714 // and produce a fixed permutation. If any of these match, do not lower to 2715 // VPERM. 2716 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 2717 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 2718 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 2719 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 2720 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 2721 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 2722 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 2723 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 2724 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 2725 return Op; 2726 2727 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 2728 // perfect shuffle table to emit an optimal matching sequence. 2729 unsigned PFIndexes[4]; 2730 bool isFourElementShuffle = true; 2731 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 2732 unsigned EltNo = 8; // Start out undef. 2733 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 2734 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 2735 continue; // Undef, ignore it. 2736 2737 unsigned ByteSource = 2738 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 2739 if ((ByteSource & 3) != j) { 2740 isFourElementShuffle = false; 2741 break; 2742 } 2743 2744 if (EltNo == 8) { 2745 EltNo = ByteSource/4; 2746 } else if (EltNo != ByteSource/4) { 2747 isFourElementShuffle = false; 2748 break; 2749 } 2750 } 2751 PFIndexes[i] = EltNo; 2752 } 2753 2754 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 2755 // perfect shuffle vector to determine if it is cost effective to do this as 2756 // discrete instructions, or whether we should use a vperm. 2757 if (isFourElementShuffle) { 2758 // Compute the index in the perfect shuffle table. 2759 unsigned PFTableIndex = 2760 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2761 2762 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2763 unsigned Cost = (PFEntry >> 30); 2764 2765 // Determining when to avoid vperm is tricky. Many things affect the cost 2766 // of vperm, particularly how many times the perm mask needs to be computed. 2767 // For example, if the perm mask can be hoisted out of a loop or is already 2768 // used (perhaps because there are multiple permutes with the same shuffle 2769 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 2770 // the loop requires an extra register. 2771 // 2772 // As a compromise, we only emit discrete instructions if the shuffle can be 2773 // generated in 3 or fewer operations. When we have loop information 2774 // available, if this block is within a loop, we should avoid using vperm 2775 // for 3-operation perms and use a constant pool load instead. 2776 if (Cost < 3) 2777 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 2778 } 2779 2780 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 2781 // vector that will get spilled to the constant pool. 2782 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 2783 2784 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 2785 // that it is in input element units, not in bytes. Convert now. 2786 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); 2787 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 2788 2789 SmallVector<SDOperand, 16> ResultMask; 2790 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 2791 unsigned SrcElt; 2792 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 2793 SrcElt = 0; 2794 else 2795 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 2796 2797 for (unsigned j = 0; j != BytesPerElement; ++j) 2798 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 2799 MVT::i8)); 2800 } 2801 2802 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 2803 &ResultMask[0], ResultMask.size()); 2804 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 2805} 2806 2807/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 2808/// altivec comparison. If it is, return true and fill in Opc/isDot with 2809/// information about the intrinsic. 2810static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 2811 bool &isDot) { 2812 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 2813 CompareOpc = -1; 2814 isDot = false; 2815 switch (IntrinsicID) { 2816 default: return false; 2817 // Comparison predicates. 2818 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 2819 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 2820 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 2821 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 2822 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 2823 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 2824 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 2825 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 2826 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 2827 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 2828 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 2829 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 2830 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 2831 2832 // Normal Comparisons. 2833 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 2834 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 2835 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 2836 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 2837 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 2838 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 2839 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 2840 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 2841 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 2842 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 2843 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 2844 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 2845 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 2846 } 2847 return true; 2848} 2849 2850/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 2851/// lower, do it, otherwise return null. 2852static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 2853 // If this is a lowered altivec predicate compare, CompareOpc is set to the 2854 // opcode number of the comparison. 2855 int CompareOpc; 2856 bool isDot; 2857 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 2858 return SDOperand(); // Don't custom lower most intrinsics. 2859 2860 // If this is a non-dot comparison, make the VCMP node and we are done. 2861 if (!isDot) { 2862 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 2863 Op.getOperand(1), Op.getOperand(2), 2864 DAG.getConstant(CompareOpc, MVT::i32)); 2865 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 2866 } 2867 2868 // Create the PPCISD altivec 'dot' comparison node. 2869 SDOperand Ops[] = { 2870 Op.getOperand(2), // LHS 2871 Op.getOperand(3), // RHS 2872 DAG.getConstant(CompareOpc, MVT::i32) 2873 }; 2874 std::vector<MVT::ValueType> VTs; 2875 VTs.push_back(Op.getOperand(2).getValueType()); 2876 VTs.push_back(MVT::Flag); 2877 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2878 2879 // Now that we have the comparison, emit a copy from the CR to a GPR. 2880 // This is flagged to the above dot comparison. 2881 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 2882 DAG.getRegister(PPC::CR6, MVT::i32), 2883 CompNode.getValue(1)); 2884 2885 // Unpack the result based on how the target uses it. 2886 unsigned BitNo; // Bit # of CR6. 2887 bool InvertBit; // Invert result? 2888 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 2889 default: // Can't happen, don't crash on invalid number though. 2890 case 0: // Return the value of the EQ bit of CR6. 2891 BitNo = 0; InvertBit = false; 2892 break; 2893 case 1: // Return the inverted value of the EQ bit of CR6. 2894 BitNo = 0; InvertBit = true; 2895 break; 2896 case 2: // Return the value of the LT bit of CR6. 2897 BitNo = 2; InvertBit = false; 2898 break; 2899 case 3: // Return the inverted value of the LT bit of CR6. 2900 BitNo = 2; InvertBit = true; 2901 break; 2902 } 2903 2904 // Shift the bit into the low position. 2905 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 2906 DAG.getConstant(8-(3-BitNo), MVT::i32)); 2907 // Isolate the bit. 2908 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 2909 DAG.getConstant(1, MVT::i32)); 2910 2911 // If we are supposed to, toggle the bit. 2912 if (InvertBit) 2913 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 2914 DAG.getConstant(1, MVT::i32)); 2915 return Flags; 2916} 2917 2918static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2919 // Create a stack slot that is 16-byte aligned. 2920 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2921 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 2922 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2923 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2924 2925 // Store the input value into Value#0 of the stack slot. 2926 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 2927 Op.getOperand(0), FIdx, NULL, 0); 2928 // Load it out. 2929 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 2930} 2931 2932static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 2933 if (Op.getValueType() == MVT::v4i32) { 2934 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2935 2936 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 2937 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 2938 2939 SDOperand RHSSwap = // = vrlw RHS, 16 2940 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 2941 2942 // Shrinkify inputs to v8i16. 2943 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 2944 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 2945 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 2946 2947 // Low parts multiplied together, generating 32-bit results (we ignore the 2948 // top parts). 2949 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 2950 LHS, RHS, DAG, MVT::v4i32); 2951 2952 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 2953 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 2954 // Shift the high parts up 16 bits. 2955 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 2956 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 2957 } else if (Op.getValueType() == MVT::v8i16) { 2958 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2959 2960 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 2961 2962 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 2963 LHS, RHS, Zero, DAG); 2964 } else if (Op.getValueType() == MVT::v16i8) { 2965 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2966 2967 // Multiply the even 8-bit parts, producing 16-bit sums. 2968 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 2969 LHS, RHS, DAG, MVT::v8i16); 2970 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 2971 2972 // Multiply the odd 8-bit parts, producing 16-bit sums. 2973 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 2974 LHS, RHS, DAG, MVT::v8i16); 2975 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 2976 2977 // Merge the results together. 2978 SDOperand Ops[16]; 2979 for (unsigned i = 0; i != 8; ++i) { 2980 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 2981 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 2982 } 2983 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 2984 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2985 } else { 2986 assert(0 && "Unknown mul to lower!"); 2987 abort(); 2988 } 2989} 2990 2991/// LowerOperation - Provide custom lowering hooks for some operations. 2992/// 2993SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2994 switch (Op.getOpcode()) { 2995 default: assert(0 && "Wasn't expecting to be able to lower this!"); 2996 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2997 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2998 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 2999 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 3000 case ISD::SETCC: return LowerSETCC(Op, DAG); 3001 case ISD::VASTART: 3002 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3003 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3004 3005 case ISD::VAARG: 3006 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3007 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3008 3009 case ISD::FORMAL_ARGUMENTS: 3010 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, 3011 VarArgsStackOffset, VarArgsNumGPR, 3012 VarArgsNumFPR, PPCSubTarget); 3013 3014 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget); 3015 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); 3016 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 3017 case ISD::DYNAMIC_STACKALLOC: 3018 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 3019 3020 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 3021 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 3022 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 3023 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG); 3024 3025 // Lower 64-bit shifts. 3026 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 3027 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 3028 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 3029 3030 // Vector-related lowering. 3031 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3032 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3033 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 3034 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 3035 case ISD::MUL: return LowerMUL(Op, DAG); 3036 3037 // Frame & Return address. 3038 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3039 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3040 } 3041 return SDOperand(); 3042} 3043 3044SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) { 3045 switch (N->getOpcode()) { 3046 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3047 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val; 3048 } 3049} 3050 3051 3052//===----------------------------------------------------------------------===// 3053// Other Lowering Code 3054//===----------------------------------------------------------------------===// 3055 3056MachineBasicBlock * 3057PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3058 MachineBasicBlock *BB) { 3059 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3060 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 3061 MI->getOpcode() == PPC::SELECT_CC_I8 || 3062 MI->getOpcode() == PPC::SELECT_CC_F4 || 3063 MI->getOpcode() == PPC::SELECT_CC_F8 || 3064 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 3065 "Unexpected instr type to insert"); 3066 3067 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 3068 // control-flow pattern. The incoming instruction knows the destination vreg 3069 // to set, the condition code register to branch on, the true/false values to 3070 // select between, and a branch opcode to use. 3071 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3072 ilist<MachineBasicBlock>::iterator It = BB; 3073 ++It; 3074 3075 // thisMBB: 3076 // ... 3077 // TrueVal = ... 3078 // cmpTY ccX, r1, r2 3079 // bCC copy1MBB 3080 // fallthrough --> copy0MBB 3081 MachineBasicBlock *thisMBB = BB; 3082 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 3083 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 3084 unsigned SelectPred = MI->getOperand(4).getImm(); 3085 BuildMI(BB, TII->get(PPC::BCC)) 3086 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 3087 MachineFunction *F = BB->getParent(); 3088 F->getBasicBlockList().insert(It, copy0MBB); 3089 F->getBasicBlockList().insert(It, sinkMBB); 3090 // Update machine-CFG edges by first adding all successors of the current 3091 // block to the new block which will contain the Phi node for the select. 3092 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 3093 e = BB->succ_end(); i != e; ++i) 3094 sinkMBB->addSuccessor(*i); 3095 // Next, remove all successors of the current block, and add the true 3096 // and fallthrough blocks as its successors. 3097 while(!BB->succ_empty()) 3098 BB->removeSuccessor(BB->succ_begin()); 3099 BB->addSuccessor(copy0MBB); 3100 BB->addSuccessor(sinkMBB); 3101 3102 // copy0MBB: 3103 // %FalseValue = ... 3104 // # fallthrough to sinkMBB 3105 BB = copy0MBB; 3106 3107 // Update machine-CFG edges 3108 BB->addSuccessor(sinkMBB); 3109 3110 // sinkMBB: 3111 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 3112 // ... 3113 BB = sinkMBB; 3114 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 3115 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 3116 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 3117 3118 delete MI; // The pseudo instruction is gone now. 3119 return BB; 3120} 3121 3122//===----------------------------------------------------------------------===// 3123// Target Optimization Hooks 3124//===----------------------------------------------------------------------===// 3125 3126SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 3127 DAGCombinerInfo &DCI) const { 3128 TargetMachine &TM = getTargetMachine(); 3129 SelectionDAG &DAG = DCI.DAG; 3130 switch (N->getOpcode()) { 3131 default: break; 3132 case PPCISD::SHL: 3133 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3134 if (C->getValue() == 0) // 0 << V -> 0. 3135 return N->getOperand(0); 3136 } 3137 break; 3138 case PPCISD::SRL: 3139 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3140 if (C->getValue() == 0) // 0 >>u V -> 0. 3141 return N->getOperand(0); 3142 } 3143 break; 3144 case PPCISD::SRA: 3145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3146 if (C->getValue() == 0 || // 0 >>s V -> 0. 3147 C->isAllOnesValue()) // -1 >>s V -> -1. 3148 return N->getOperand(0); 3149 } 3150 break; 3151 3152 case ISD::SINT_TO_FP: 3153 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 3154 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 3155 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 3156 // We allow the src/dst to be either f32/f64, but the intermediate 3157 // type must be i64. 3158 if (N->getOperand(0).getValueType() == MVT::i64 && 3159 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 3160 SDOperand Val = N->getOperand(0).getOperand(0); 3161 if (Val.getValueType() == MVT::f32) { 3162 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3163 DCI.AddToWorklist(Val.Val); 3164 } 3165 3166 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 3167 DCI.AddToWorklist(Val.Val); 3168 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 3169 DCI.AddToWorklist(Val.Val); 3170 if (N->getValueType(0) == MVT::f32) { 3171 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 3172 DCI.AddToWorklist(Val.Val); 3173 } 3174 return Val; 3175 } else if (N->getOperand(0).getValueType() == MVT::i32) { 3176 // If the intermediate type is i32, we can avoid the load/store here 3177 // too. 3178 } 3179 } 3180 } 3181 break; 3182 case ISD::STORE: 3183 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 3184 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 3185 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 3186 N->getOperand(1).getValueType() == MVT::i32 && 3187 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 3188 SDOperand Val = N->getOperand(1).getOperand(0); 3189 if (Val.getValueType() == MVT::f32) { 3190 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3191 DCI.AddToWorklist(Val.Val); 3192 } 3193 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 3194 DCI.AddToWorklist(Val.Val); 3195 3196 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 3197 N->getOperand(2), N->getOperand(3)); 3198 DCI.AddToWorklist(Val.Val); 3199 return Val; 3200 } 3201 3202 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 3203 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 3204 N->getOperand(1).Val->hasOneUse() && 3205 (N->getOperand(1).getValueType() == MVT::i32 || 3206 N->getOperand(1).getValueType() == MVT::i16)) { 3207 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 3208 // Do an any-extend to 32-bits if this is a half-word input. 3209 if (BSwapOp.getValueType() == MVT::i16) 3210 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 3211 3212 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 3213 N->getOperand(2), N->getOperand(3), 3214 DAG.getValueType(N->getOperand(1).getValueType())); 3215 } 3216 break; 3217 case ISD::BSWAP: 3218 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 3219 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 3220 N->getOperand(0).hasOneUse() && 3221 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 3222 SDOperand Load = N->getOperand(0); 3223 LoadSDNode *LD = cast<LoadSDNode>(Load); 3224 // Create the byte-swapping load. 3225 std::vector<MVT::ValueType> VTs; 3226 VTs.push_back(MVT::i32); 3227 VTs.push_back(MVT::Other); 3228 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); 3229 SDOperand Ops[] = { 3230 LD->getChain(), // Chain 3231 LD->getBasePtr(), // Ptr 3232 SV, // SrcValue 3233 DAG.getValueType(N->getValueType(0)) // VT 3234 }; 3235 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 3236 3237 // If this is an i16 load, insert the truncate. 3238 SDOperand ResVal = BSLoad; 3239 if (N->getValueType(0) == MVT::i16) 3240 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 3241 3242 // First, combine the bswap away. This makes the value produced by the 3243 // load dead. 3244 DCI.CombineTo(N, ResVal); 3245 3246 // Next, combine the load away, we give it a bogus result value but a real 3247 // chain result. The result value is dead because the bswap is dead. 3248 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 3249 3250 // Return N so it doesn't get rechecked! 3251 return SDOperand(N, 0); 3252 } 3253 3254 break; 3255 case PPCISD::VCMP: { 3256 // If a VCMPo node already exists with exactly the same operands as this 3257 // node, use its result instead of this node (VCMPo computes both a CR6 and 3258 // a normal output). 3259 // 3260 if (!N->getOperand(0).hasOneUse() && 3261 !N->getOperand(1).hasOneUse() && 3262 !N->getOperand(2).hasOneUse()) { 3263 3264 // Scan all of the users of the LHS, looking for VCMPo's that match. 3265 SDNode *VCMPoNode = 0; 3266 3267 SDNode *LHSN = N->getOperand(0).Val; 3268 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 3269 UI != E; ++UI) 3270 if ((*UI)->getOpcode() == PPCISD::VCMPo && 3271 (*UI)->getOperand(1) == N->getOperand(1) && 3272 (*UI)->getOperand(2) == N->getOperand(2) && 3273 (*UI)->getOperand(0) == N->getOperand(0)) { 3274 VCMPoNode = *UI; 3275 break; 3276 } 3277 3278 // If there is no VCMPo node, or if the flag value has a single use, don't 3279 // transform this. 3280 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 3281 break; 3282 3283 // Look at the (necessarily single) use of the flag value. If it has a 3284 // chain, this transformation is more complex. Note that multiple things 3285 // could use the value result, which we should ignore. 3286 SDNode *FlagUser = 0; 3287 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 3288 FlagUser == 0; ++UI) { 3289 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 3290 SDNode *User = *UI; 3291 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 3292 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 3293 FlagUser = User; 3294 break; 3295 } 3296 } 3297 } 3298 3299 // If the user is a MFCR instruction, we know this is safe. Otherwise we 3300 // give up for right now. 3301 if (FlagUser->getOpcode() == PPCISD::MFCR) 3302 return SDOperand(VCMPoNode, 0); 3303 } 3304 break; 3305 } 3306 case ISD::BR_CC: { 3307 // If this is a branch on an altivec predicate comparison, lower this so 3308 // that we don't have to do a MFCR: instead, branch directly on CR6. This 3309 // lowering is done pre-legalize, because the legalizer lowers the predicate 3310 // compare down to code that is difficult to reassemble. 3311 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 3312 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 3313 int CompareOpc; 3314 bool isDot; 3315 3316 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 3317 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 3318 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 3319 assert(isDot && "Can't compare against a vector result!"); 3320 3321 // If this is a comparison against something other than 0/1, then we know 3322 // that the condition is never/always true. 3323 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 3324 if (Val != 0 && Val != 1) { 3325 if (CC == ISD::SETEQ) // Cond never true, remove branch. 3326 return N->getOperand(0); 3327 // Always !=, turn it into an unconditional branch. 3328 return DAG.getNode(ISD::BR, MVT::Other, 3329 N->getOperand(0), N->getOperand(4)); 3330 } 3331 3332 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 3333 3334 // Create the PPCISD altivec 'dot' comparison node. 3335 std::vector<MVT::ValueType> VTs; 3336 SDOperand Ops[] = { 3337 LHS.getOperand(2), // LHS of compare 3338 LHS.getOperand(3), // RHS of compare 3339 DAG.getConstant(CompareOpc, MVT::i32) 3340 }; 3341 VTs.push_back(LHS.getOperand(2).getValueType()); 3342 VTs.push_back(MVT::Flag); 3343 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 3344 3345 // Unpack the result based on how the target uses it. 3346 PPC::Predicate CompOpc; 3347 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 3348 default: // Can't happen, don't crash on invalid number though. 3349 case 0: // Branch on the value of the EQ bit of CR6. 3350 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 3351 break; 3352 case 1: // Branch on the inverted value of the EQ bit of CR6. 3353 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 3354 break; 3355 case 2: // Branch on the value of the LT bit of CR6. 3356 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 3357 break; 3358 case 3: // Branch on the inverted value of the LT bit of CR6. 3359 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 3360 break; 3361 } 3362 3363 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 3364 DAG.getConstant(CompOpc, MVT::i32), 3365 DAG.getRegister(PPC::CR6, MVT::i32), 3366 N->getOperand(4), CompNode.getValue(1)); 3367 } 3368 break; 3369 } 3370 } 3371 3372 return SDOperand(); 3373} 3374 3375//===----------------------------------------------------------------------===// 3376// Inline Assembly Support 3377//===----------------------------------------------------------------------===// 3378 3379void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 3380 uint64_t Mask, 3381 uint64_t &KnownZero, 3382 uint64_t &KnownOne, 3383 const SelectionDAG &DAG, 3384 unsigned Depth) const { 3385 KnownZero = 0; 3386 KnownOne = 0; 3387 switch (Op.getOpcode()) { 3388 default: break; 3389 case PPCISD::LBRX: { 3390 // lhbrx is known to have the top bits cleared out. 3391 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 3392 KnownZero = 0xFFFF0000; 3393 break; 3394 } 3395 case ISD::INTRINSIC_WO_CHAIN: { 3396 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 3397 default: break; 3398 case Intrinsic::ppc_altivec_vcmpbfp_p: 3399 case Intrinsic::ppc_altivec_vcmpeqfp_p: 3400 case Intrinsic::ppc_altivec_vcmpequb_p: 3401 case Intrinsic::ppc_altivec_vcmpequh_p: 3402 case Intrinsic::ppc_altivec_vcmpequw_p: 3403 case Intrinsic::ppc_altivec_vcmpgefp_p: 3404 case Intrinsic::ppc_altivec_vcmpgtfp_p: 3405 case Intrinsic::ppc_altivec_vcmpgtsb_p: 3406 case Intrinsic::ppc_altivec_vcmpgtsh_p: 3407 case Intrinsic::ppc_altivec_vcmpgtsw_p: 3408 case Intrinsic::ppc_altivec_vcmpgtub_p: 3409 case Intrinsic::ppc_altivec_vcmpgtuh_p: 3410 case Intrinsic::ppc_altivec_vcmpgtuw_p: 3411 KnownZero = ~1U; // All bits but the low one are known to be zero. 3412 break; 3413 } 3414 } 3415 } 3416} 3417 3418 3419/// getConstraintType - Given a constraint, return the type of 3420/// constraint it is for this target. 3421PPCTargetLowering::ConstraintType 3422PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 3423 if (Constraint.size() == 1) { 3424 switch (Constraint[0]) { 3425 default: break; 3426 case 'b': 3427 case 'r': 3428 case 'f': 3429 case 'v': 3430 case 'y': 3431 return C_RegisterClass; 3432 } 3433 } 3434 return TargetLowering::getConstraintType(Constraint); 3435} 3436 3437std::pair<unsigned, const TargetRegisterClass*> 3438PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3439 MVT::ValueType VT) const { 3440 if (Constraint.size() == 1) { 3441 // GCC RS6000 Constraint Letters 3442 switch (Constraint[0]) { 3443 case 'b': // R1-R31 3444 case 'r': // R0-R31 3445 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 3446 return std::make_pair(0U, PPC::G8RCRegisterClass); 3447 return std::make_pair(0U, PPC::GPRCRegisterClass); 3448 case 'f': 3449 if (VT == MVT::f32) 3450 return std::make_pair(0U, PPC::F4RCRegisterClass); 3451 else if (VT == MVT::f64) 3452 return std::make_pair(0U, PPC::F8RCRegisterClass); 3453 break; 3454 case 'v': 3455 return std::make_pair(0U, PPC::VRRCRegisterClass); 3456 case 'y': // crrc 3457 return std::make_pair(0U, PPC::CRRCRegisterClass); 3458 } 3459 } 3460 3461 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3462} 3463 3464 3465/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3466/// vector. If it is invalid, don't add anything to Ops. 3467void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter, 3468 std::vector<SDOperand>&Ops, 3469 SelectionDAG &DAG) { 3470 SDOperand Result(0,0); 3471 switch (Letter) { 3472 default: break; 3473 case 'I': 3474 case 'J': 3475 case 'K': 3476 case 'L': 3477 case 'M': 3478 case 'N': 3479 case 'O': 3480 case 'P': { 3481 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 3482 if (!CST) return; // Must be an immediate to match. 3483 unsigned Value = CST->getValue(); 3484 switch (Letter) { 3485 default: assert(0 && "Unknown constraint letter!"); 3486 case 'I': // "I" is a signed 16-bit constant. 3487 if ((short)Value == (int)Value) 3488 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3489 break; 3490 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 3491 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 3492 if ((short)Value == 0) 3493 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3494 break; 3495 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 3496 if ((Value >> 16) == 0) 3497 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3498 break; 3499 case 'M': // "M" is a constant that is greater than 31. 3500 if (Value > 31) 3501 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3502 break; 3503 case 'N': // "N" is a positive constant that is an exact power of two. 3504 if ((int)Value > 0 && isPowerOf2_32(Value)) 3505 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3506 break; 3507 case 'O': // "O" is the constant zero. 3508 if (Value == 0) 3509 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3510 break; 3511 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 3512 if ((short)-Value == (int)-Value) 3513 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3514 break; 3515 } 3516 break; 3517 } 3518 } 3519 3520 if (Result.Val) { 3521 Ops.push_back(Result); 3522 return; 3523 } 3524 3525 // Handle standard constraint letters. 3526 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); 3527} 3528 3529// isLegalAddressingMode - Return true if the addressing mode represented 3530// by AM is legal for this target, for a load/store of the specified type. 3531bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3532 const Type *Ty) const { 3533 // FIXME: PPC does not allow r+i addressing modes for vectors! 3534 3535 // PPC allows a sign-extended 16-bit immediate field. 3536 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3537 return false; 3538 3539 // No global is ever allowed as a base. 3540 if (AM.BaseGV) 3541 return false; 3542 3543 // PPC only support r+r, 3544 switch (AM.Scale) { 3545 case 0: // "r+i" or just "i", depending on HasBaseReg. 3546 break; 3547 case 1: 3548 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3549 return false; 3550 // Otherwise we have r+r or r+i. 3551 break; 3552 case 2: 3553 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3554 return false; 3555 // Allow 2*r as r+r. 3556 break; 3557 default: 3558 // No other scales are supported. 3559 return false; 3560 } 3561 3562 return true; 3563} 3564 3565/// isLegalAddressImmediate - Return true if the integer value can be used 3566/// as the offset of the target addressing mode for load / store of the 3567/// given type. 3568bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 3569 // PPC allows a sign-extended 16-bit immediate field. 3570 return (V > -(1 << 16) && V < (1 << 16)-1); 3571} 3572 3573bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 3574 return false; 3575} 3576 3577SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { 3578 // Depths > 0 not supported yet! 3579 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3580 return SDOperand(); 3581 3582 MachineFunction &MF = DAG.getMachineFunction(); 3583 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 3584 int RAIdx = FuncInfo->getReturnAddrSaveIndex(); 3585 if (RAIdx == 0) { 3586 bool isPPC64 = PPCSubTarget.isPPC64(); 3587 int Offset = 3588 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI()); 3589 3590 // Set up a frame object for the return address. 3591 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset); 3592 3593 // Remember it for next time. 3594 FuncInfo->setReturnAddrSaveIndex(RAIdx); 3595 3596 // Make sure the function really does not optimize away the store of the RA 3597 // to the stack. 3598 FuncInfo->setLRStoreRequired(); 3599 } 3600 3601 // Just load the return address off the stack. 3602 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy()); 3603 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 3604} 3605 3606SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { 3607 // Depths > 0 not supported yet! 3608 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3609 return SDOperand(); 3610 3611 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3612 bool isPPC64 = PtrVT == MVT::i64; 3613 3614 MachineFunction &MF = DAG.getMachineFunction(); 3615 MachineFrameInfo *MFI = MF.getFrameInfo(); 3616 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 3617 && MFI->getStackSize(); 3618 3619 if (isPPC64) 3620 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, 3621 MVT::i64); 3622 else 3623 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, 3624 MVT::i32); 3625} 3626