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Searched defs:RetVT (Results 1 - 10 of 10) sorted by relevance

/external/llvm/lib/CodeGen/
H A D	TargetLoweringBase.cpp	435 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { argument 437 if (RetVT == MVT::f32) 440 if (RetVT == MVT::f64) 442 if (RetVT == MVT::f128) 445 if (RetVT == MVT::f128) 454 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { argument 455 if (RetVT == MVT::f16) { 466 } else if (RetVT == MVT::f32) { 475 } else if (RetVT == MVT::f64) { 489 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { argument 539 getFPTOUINT(EVT OpVT, EVT RetVT) argument 589 getSINTTOFP(EVT OpVT, EVT RetVT) argument 629 getUINTTOFP(EVT OpVT, EVT RetVT) argument [all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A D	FastISel.cpp	`1951 unsigned FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, argument 1953 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));`
H A D	LegalizeFloatTypes.cpp	`1588 static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT) { argument 1591 } else if (RetVT == MVT::f16) {`
H A D	TargetLowering.cpp	84 /// result of type RetVT. 87 RTLIB::Libcall LC, EVT RetVT, 107 Type RetTy = RetVT.getTypeForEVT(DAG.getContext()); 109 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned); 202 EVT RetVT = getCmpLibcallReturnType(); local 204 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/sign irrelevant/, 206 NewRHS = DAG.getConstant(0, RetVT); 210 getSetCCResultType(DAG.getContext(), RetVT), 212 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/sign irrelevant/, 215 getSetCCResultType(DAG.getContext(), RetVT), NewLH 86 makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn, bool isReturnValueUsed) const argument [all...]
H A D	LegalizeVectorTypes.cpp	`2910 EVT RetVT = WidenEltVT; local 2912 return RetVT; 2926 RetVT = MemVT; 2942 if (RetVT.getSizeInBits() < MemVTWidth \|\| MemVT == WidenVT) 2947 return RetVT;`
/external/llvm/lib/Target/Mips/
H A D	MipsFastISel.cpp	`134 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS, 171 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes); 218 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, argument 1075 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, argument 1079 if (RetVT != MVT::isVoid) { 1082 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips); 1090 if (RetVT == MVT::i1 \|\| RetVT == MVT::i8 \|\| RetVT == MVT::i16) 1121 MVT RetVT; [all...]`
/external/llvm/lib/Target/PowerPC/
H A D	PPCFastISel.cpp	`182 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes); 1358 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) { argument 1369 if (RetVT != MVT::isVoid) { 1372 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS); 1382 if (RetVT == MVT::i8 \|\| RetVT == MVT::i16 \|\| RetVT == MVT::i32) 1388 if (RetVT == CopyVT) { 1398 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1406 } else if (RetVT 1445 MVT RetVT; local [all...]`
/external/llvm/lib/Target/ARM/
H A D	ARMFastISel.cpp	`208 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 2025 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, argument 2035 if (RetVT != MVT::isVoid) { 2038 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg)); 2041 if (RVLocs.size() == 2 && RetVT == MVT::f64) { 2062 if (RetVT == MVT::i1 \|\| RetVT == MVT::i8 \|\| RetVT == MVT::i16) 2194 MVT RetVT; local 2196 RetVT 2303 MVT RetVT; local [all...]`
/external/llvm/lib/Target/X86/
H A D	X86FastISel.cpp	117 bool X86FastEmitCMoveSelect(MVT RetVT, const Instruction I); 119 bool X86FastEmitSSESelect(MVT RetVT, const Instruction I); 121 bool X86FastEmitPseudoSelect(MVT RetVT, const Instruction I); 257 MVT RetVT; local 261 if (!isTypeLegal(RetTy, RetVT)) 264 if (RetVT != MVT::i32 && RetVT != MVT::i64) 1739 bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction I) { argument 1745 if (RetVT < MVT::i16 \|\| RetVT > MV 1859 X86FastEmitSSESelect(MVT RetVT, const Instruction I) argument 1957 X86FastEmitPseudoSelect(MVT RetVT, const Instruction I) argument 2022 MVT RetVT; local [all...]
/external/llvm/lib/Target/AArch64/
H A D	AArch64FastISel.cpp	153 bool optimizeIntExtLoad(const Instruction I, MVT RetVT, MVT SrcVT); 158 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value LHS, 161 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, 164 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, 167 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, 172 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, 181 bool emitICmp(MVT RetVT, const Value LHS, const Value RHS, bool IsZExt); 182 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm); 183 bool emitFCmp(MVT RetVT, const Value LHS, const Value RHS); 190 unsigned emitAdd(MVT RetVT, cons 1084 emitAddSub(bool UseAdd, MVT RetVT, const Value LHS, const Value RHS, bool SetFlags, bool WantResult, bool IsZExt) argument 1231 emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, bool SetFlags, bool WantResult) argument 1265 emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm, bool SetFlags, bool WantResult) argument 1310 emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument 1347 emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ExtType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument 1409 emitICmp(MVT RetVT, const Value LHS, const Value RHS, bool IsZExt) argument 1415 emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm) argument 1421 emitFCmp(MVT RetVT, const Value LHS, const Value RHS) argument 1456 emitAdd(MVT RetVT, const Value LHS, const Value RHS, bool SetFlags, bool WantResult, bool IsZExt) argument 1486 emitSub(MVT RetVT, const Value LHS, const Value RHS, bool SetFlags, bool WantResult, bool IsZExt) argument 1492 emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, bool WantResult) argument 1499 emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool WantResult) argument 1509 emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value LHS, const Value RHS) argument 1587 emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm) argument 1633 emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, uint64_t ShiftImm) argument 1671 emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm) argument 1676 emitLoad(MVT VT, MVT RetVT, Address Addr, bool WantZExt, MachineMemOperand MMO) argument 1881 MVT RetVT = VT; local 3017 finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes) argument 3247 MVT RetVT; local 3411 MVT RetVT; local 3849 emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 3869 emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 3879 emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 3889 emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument 3915 emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 3995 emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument 4022 emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 4116 emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument 4143 emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 4334 optimizeIntExtLoad(const Instruction I, MVT RetVT, MVT SrcVT) argument 4390 MVT RetVT; local 4561 MVT RetVT; local 4650 MVT RetVT, SrcVT; local 4691 MVT RetVT; local [all...]

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