/external/clang/lib/StaticAnalyzer/Core/ |
H A D | SimpleConstraintManager.h | 25 SubEngine *SU; member in class:clang::ento::SimpleConstraintManager 29 : SU(subengine), SVB(SB) {}
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/external/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument 38 MachineInstr *MI = SU->getInstr(); 75 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); 84 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { argument 85 MachineInstr *MI = SU->getInstr(); 91 ScoreboardHazardRecognizer::EmitInstruction(SU);
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/external/llvm/lib/CodeGen/ |
H A D | LatencyPriorityQueue.cpp | 55 /// of SU, return it, otherwise return null. 56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { argument 58 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 73 void LatencyPriorityQueue::push(SUnit *SU) { argument 77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 79 if (getSingleUnscheduledPred(I->getSUnit()) == SU) 82 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; 84 Queue.push_back(SU); 92 scheduledNode(SUnit *SU) argument 105 AdjustPriorityOfUnscheduledPreds(SUnit *SU) argument 134 remove(SUnit *SU) argument [all...] |
H A D | ScheduleDAGPrinter.cpp | 77 std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU, argument 79 return G->getGraphNodeLabel(SU);
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H A D | DFAPacketizer.cpp | 166 // Generate MI -> SU map. 169 SUnit *SU = &VLIWScheduler->SUnits[i]; local 170 MIToSUnit[SU->getInstr()] = SU;
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H A D | ScoreboardHazardRecognizer.cpp | 119 ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument 129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 166 DEBUG(dbgs() << "SU(" << SU->NodeNum << "): "); 167 DEBUG(DAG->dumpNode(SU)); 179 void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { argument 185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
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H A D | CriticalAntiDepBreaker.cpp | 128 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up 130 static const SDep *CriticalPathStep(const SUnit *SU) { argument 134 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end(); 441 const SUnit *SU = &SUnits[i]; local 442 MISUnitMap[SU->getInstr()] = SU; 443 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) 444 Max = SU; 646 const SUnit *SU = MISUnitMap[Q->second->getParent()]; local [all...] |
H A D | PostRASchedulerList.cpp | 179 void ReleaseSucc(SUnit *SU, SDep *SuccEdge); 180 void ReleaseSuccessors(SUnit *SU); 181 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle); 245 if (SUnit *SU = Sequence[i]) 246 SU->dump(this); 435 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) { argument 454 // SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency()); 469 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors. 470 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) { argument 471 for (SUnit::succ_iterator I = SU 480 ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) argument [all...] |
H A D | ScheduleDAGInstrs.cpp | 207 /// the exit SU to the register defs and use list. This is because we want to 250 /// MO is an operand of SU's instruction that defines a physical register. Add 251 /// data dependencies from SU to any uses of the physical register. 252 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { argument 253 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 264 SUnit *UseSU = I->SU; 265 if (UseSU == SU) 274 Dep = SDep(SU, SDep::Artificial); 278 SU->hasPhysRegDefs = true; 279 Dep = SDep(SU, SDe 295 addPhysRegDeps(SUnit *SU, unsigned OperIdx) argument 376 addVRegDefDeps(SUnit *SU, unsigned OperIdx) argument 414 addVRegUseDeps(SUnit *SU, unsigned OperIdx) argument 631 adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI, const DataLayout &DL, SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList, unsigned LatencyToLoad) argument 706 SUnit *SU = newSUnit(MI); local 810 SUnit *SU = MISUnitMap[MI]; local 1279 visitPreorder(const SUnit *SU) argument 1287 visitPostorderNode(const SUnit *SU) argument 1439 follow(const SUnit *SU) argument 1459 hasDataSucc(const SUnit *SU) argument 1477 const SUnit *SU = &*SI; local [all...] |
H A D | MachineScheduler.cpp | 539 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { argument 556 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However, 558 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) 559 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); 566 /// releaseSuccessors - Call releaseSucc on each of SU's successors. 567 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { argument 568 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 570 releaseSucc(SU, &*I); 578 void ScheduleDAGMI::releasePred(SUnit *SU, SDe argument 606 releasePredecessors(SUnit *SU) argument 743 SUnit *SU = &(*I); local 791 updateQueues(SUnit *SU, bool IsTopNode) argument 927 updateScheduledPressure(const SUnit *SU, const std::vector<unsigned> &NewMaxPressure) argument 980 SUnit *SU = UI->SU; local 1188 scheduleMI(SUnit *SU, bool IsTopNode) argument 1242 SUnit *SU; member in struct:__anon10439::LoadClusterMutation::LoadInfo 1270 SUnit *SU = Loads[Idx]; local 1318 SUnit *SU = &DAG->SUnits[Idx]; local 1368 SUnit *SU = &DAG->SUnits[--Idx]; local 1568 SUnit *SU = &DAG->SUnits[Idx]; local 1658 getLatencyStallCycles(SUnit *SU) argument 1695 checkHazard(SUnit *SU) argument 1775 releaseNode(SUnit *SU, unsigned ReadyCycle) argument 1801 releaseTopNode(SUnit *SU) argument 1808 releaseBottomNode(SUnit *SU) argument 1898 bumpNode(SUnit *SU) argument 2037 SUnit *SU = *(Pending.begin()+i); local 2058 removeReady(SUnit *SU) argument 2521 getWeakLeft(const SUnit *SU, bool isTop) argument 2532 biasPhysRegCopy(const SUnit *SU, bool isTop) argument 2790 SUnit *SU; local 2830 reschedulePhysRegCopies(SUnit *SU, bool isTop) argument 2862 schedNode(SUnit *SU, bool IsTopNode) argument 2997 SUnit *SU; local 3022 schedNode(SUnit *SU, bool IsTopNode) argument 3101 SUnit *SU = ReadyQ.back(); variable 3188 SUnit *SU; variable 3277 getNodeLabel(const SUnit *SU, const ScheduleDAG *G) argument 3288 getNodeDescription(const SUnit *SU, const ScheduleDAG *G) argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGVLIW.cpp | 87 void releaseSucc(SUnit *SU, const SDep &D); 88 void releaseSuccessors(SUnit *SU); 89 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle); 116 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { argument 131 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); 140 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { argument 142 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 147 releaseSucc(SU, *I); 154 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigne argument [all...] |
H A D | ResourcePriorityQueue.cpp | 70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { argument 72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, argument 110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 145 static unsigned numberCtrlDepsInSU(SUnit *SU) { argument 147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 155 static unsigned numberCtrlPredInSU(SUnit *SU) { argument 173 SUnit *SU = &(*SUnits)[i]; local 215 getSingleUnscheduledPred(SUnit *SU) argument 231 push(SUnit *SU) argument 246 isResourceAvailable(SUnit *SU) argument 289 reserveResources(SUnit *SU) argument 326 rawRegPressureDelta(SUnit *SU, unsigned RCId) argument 360 regPressureDelta(SUnit *SU, bool RawPressure) argument 401 SUSchedulingCost(SUnit *SU) argument 471 scheduledNode(SUnit *SU) argument 547 initNumRegDefsLeft(SUnit *SU) argument 579 adjustPriorityOfUnscheduledPreds(SUnit *SU) argument 632 remove(SUnit *SU) argument [all...] |
H A D | ScheduleDAGSDNodes.cpp | 78 SUnit *SU = &SUnits.back(); local 83 SU->SchedulingPref = Sched::None; 85 SU->SchedulingPref = TLI.getSchedulingPreference(N); 86 return SU; 90 SUnit *SU = newSUnit(Old->getNode()); local 91 SU->OrigNode = Old->OrigNode; 92 SU->Latency = Old->Latency; 93 SU->isVRegCycle = Old->isVRegCycle; 94 SU->isCall = Old->isCall; 95 SU [all...] |
H A D | ScheduleDAGFast.cpp | 86 /// AddPred - adds a predecessor edge to SUnit SU. 88 void AddPred(SUnit *SU, const SDep &D) { argument 89 SU->addPred(D); 92 /// RemovePred - removes a predecessor edge from SUnit SU. 94 void RemovePred(SUnit *SU, const SDep &D) { argument 95 SU->removePred(D); 99 void ReleasePred(SUnit *SU, SDep *PredEdge); 100 void ReleasePredecessors(SUnit *SU, unsigned CurCycle); 140 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { argument 161 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigne argument 183 ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) argument 213 CopyAndMoveSuccessors(SUnit *SU) argument 388 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument 455 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument 476 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument [all...] |
H A D | ScheduleDAGRRList.cpp | 185 /// IsReachable - Checks if SU is reachable from TargetSU. 186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument 187 return Topo.IsReachable(SU, TargetSU); 190 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will 192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument 193 return Topo.WillCreateCycle(SU, TargetSU); 196 /// AddPred - adds a predecessor edge to SUnit SU. 199 void AddPred(SUnit *SU, const SDep &D) { argument 200 Topo.AddPred(SU, D.getSUnit()); 201 SU 207 RemovePred(SUnit *SU, const SDep &D) argument 213 isReady(SUnit *SU) argument 365 ReleasePred(SUnit *SU, const SDep *PredEdge) argument 525 ReleasePredecessors(SUnit *SU) argument 622 AdvancePastStalls(SUnit *SU) argument 664 EmitNode(SUnit *SU) argument 706 ScheduleNodeBottomUp(SUnit *SU) argument 805 UnscheduleNodeBottomUp(SUnit *SU) argument 894 SUnit *SU = *I; local 904 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument 926 isOperandOf(const SUnit *SU, SDNode *N) argument 937 CopyAndMoveSuccessors(SUnit *SU) argument 1136 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument 1212 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument 1234 CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs) argument 1262 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument 1339 SUnit *SU = Interferences[i-1]; local 1511 SUnit *SU = PickNodeToScheduleBottomUp(); local 1800 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); variable [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.cpp | 26 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) { argument 28 if (isBCTRAfterSet(SU)) 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 38 // SU is a load; for any predecessors in this dispatch group, that are stores, 40 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) { 41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); 45 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier()) 49 if (SU->Preds[i].getSUnit() == CurGroup[j]) 56 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) { argument 141 getHazardType(SUnit *SU, int Stalls) argument 148 ShouldPreferAnother(SUnit *SU) argument 157 PreEmitNoops(SUnit *SU) argument 175 EmitInstruction(SUnit *SU) argument 325 getHazardType(SUnit *SU, int Stalls) argument 385 EmitInstruction(SUnit *SU) argument [all...] |
/external/eigen/blas/fortran/ |
H A D | srotmg.f | 55 + SQ2,STEMP,SU,TWO,ZERO local in subroutine:SROTMG 86 SU = ONE - SH12*SH21 88 IF (.NOT.SU.LE.ZERO) GO TO 30 93 SD1 = SD1/SU 94 SD2 = SD2/SU 95 SX1 = SX1*SU 106 SU = ONE + SH11*SH22 107 STEMP = SD2/SU 108 SD2 = SD1/SU 110 SX1 = SY1*SU [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ScheduleDAGInstrs.h | 36 SUnit *SU; member in struct:llvm::VReg2SUnit 38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} 48 SUnit *SU; member in struct:llvm::PhysRegSUOper 52 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} 172 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { 173 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) 174 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); 175 return SU->SchedClass; 231 void dumpNode(const SUnit *SU) cons [all...] |
H A D | ScheduleDAG.h | 165 void setSUnit(SUnit *SU) { argument 166 Dep.setPointer(SU); 513 virtual void addNode(const SUnit *SU) = 0; 514 virtual void updateNode(const SUnit *SU) = 0; 537 virtual void remove(SUnit *SU) = 0; 584 const MCInstrDesc *getInstrDesc(const SUnit *SU) const { 585 if (SU->isInstr()) return &SU->getInstr()->getDesc(); 586 return getNodeDesc(SU->getNode()); 595 virtual void dumpNode(const SUnit *SU) cons [all...] |
H A D | MachineScheduler.h | 199 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0; 203 virtual void releaseTopNode(SUnit *SU) = 0; 206 virtual void releaseBottomNode(SUnit *SU) = 0; 280 /// \brief Add a DAG edge to the given SU with the given predecessor 324 void updateQueues(SUnit *SU, bool IsTopNode); 338 void releaseSucc(SUnit *SU, SDep *SuccEdge); 339 void releaseSuccessors(SUnit *SU); 340 void releasePred(SUnit *SU, SDep *PredEdge); 341 void releasePredecessors(SUnit *SU); 357 // Map each SU t 411 getPressureDiff(const SUnit *SU) argument 503 find(SUnit *SU) argument 507 push(SUnit *SU) argument 789 SUnit *SU; member in struct:llvm::GenericSchedulerBase::SchedCandidate [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.h | 87 bool isResourceAvailable(SUnit *SU); 88 bool reserveResources(SUnit *SU); 115 SUnit *SU; member in struct:llvm::ConvergingVLIWScheduler::SchedCandidate 123 SchedCandidate(): SU(nullptr), SCost(0) {} 176 bool checkHazard(SUnit *SU); 178 void releaseNode(SUnit *SU, unsigned ReadyCycle); 182 void bumpNode(SUnit *SU); 186 void removeReady(SUnit *SU); 214 void schedNode(SUnit *SU, bool IsTopNode) override; 216 void releaseTopNode(SUnit *SU) overrid [all...] |
H A D | HexagonMachineScheduler.cpp | 38 /// Check if scheduling of this SU is possible 43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { argument 44 if (!SU || !SU->getInstr()) 49 switch (SU->getInstr()->getOpcode()) { 51 if (!ResourcesModel->canReserveResources(SU->getInstr())) 75 if (I->getSUnit() == SU) 83 bool VLIWResourceModel::reserveResources(SUnit *SU) { argument 86 if (!SU) { 92 // If this SU doe 224 releaseTopNode(SUnit *SU) argument 241 releaseBottomNode(SUnit *SU) argument 273 checkHazard(SUnit *SU) argument 284 releaseNode(SUnit *SU, unsigned ReadyCycle) argument 325 bumpNode(SUnit *SU) argument 363 SUnit *SU = *(Pending.begin()+i); local 383 removeReady(SUnit *SU) argument 412 traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, PressureChange P) argument 427 getSingleUnscheduledPred(SUnit *SU) argument 445 getSingleUnscheduledSucc(SUnit *SU) argument 470 SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) argument 645 SUnit *SU; local 687 schedNode(SUnit *SU, bool IsTopNode) argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600MachineScheduler.cpp | 58 SUnit *SU = nullptr; local 98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || 101 SU = pickAlu(); 102 if (!SU && !PhysicalRegCopy.empty()) { 103 SU = PhysicalRegCopy.front(); 106 if (SU) { 113 if (!SU) { 115 SU = pickOther(IDFetch); 116 if (SU) 121 if (!SU) { 144 schedNode(SUnit *SU, bool IsTopNode) argument 192 releaseTopNode(SUnit *SU) argument 196 releaseBottomNode(SUnit *SU) argument 296 getInstKind(SUnit* SU) argument 325 SUnit *SU = *It; local 435 SUnit *SU = AttemptFillSlot(3, true); local 444 SUnit *SU = AttemptFillSlot(Chan, false); local 458 SUnit *SU = nullptr; local [all...] |