| /art/disassembler/ |
| H A D | disassembler_mips.cc | 64 { kRTypeMask | (0x1f << 11), 9 | (31 << 11), "jalr", "S", }, // rd = 31 is implicit.
65 { kRTypeMask | (0x1f << 11), 9, "jr", "S", }, // rd = 0 is implicit.
325 uint32_t rd = (instruction >> 11) & 0x1f; // R-type. local
362 case 'D': args << 'r' << rd; break; local
363 case 'd': args << 'f' << rd; break; local
411 case 'Z': args << rd; break; // sz ([d]ext size). local
|
| /art/compiler/utils/x86_64/ |
| H A D | assembler_x86_64_test.cc | 53 std::random_device rd; local
54 std::default_random_engine e1(rd());
|
| /art/compiler/utils/arm64/ |
| H A D | assembler_arm64.cc | 75 void Arm64Assembler::AddConstant(XRegister rd, int32_t value, Condition cond) { argument
76 AddConstant(rd, rd, value, cond);
79 void Arm64Assembler::AddConstant(XRegister rd, XRegister rn, int32_t value, argument
83 ___ Add(reg_x(rd), reg_x(rn), value);
85 // temp = rd + value
86 // rd = cond ? temp : rn
88 temps.Exclude(reg_x(rd), reg_x(rn));
91 ___ Csel(reg_x(rd), temp, reg_x(rd), con
[all...] |
| /art/compiler/utils/arm/ |
| H A D | assembler_arm32.cc | 51 bool Arm32Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED,
59 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, argument
61 EmitType01(cond, so.type(), AND, 0, rn, rd, so);
65 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, argument
67 EmitType01(cond, so.type(), EOR, 0, rn, rd, so);
71 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, argument
73 EmitType01(cond, so.type(), SUB, 0, rn, rd, so);
76 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, argument
78 EmitType01(cond, so.type(), RSB, 0, rn, rd, so);
81 void Arm32Assembler::rsbs(Register rd, Registe argument
87 add(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
93 adds(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
99 subs(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
105 adc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
111 sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
117 rsc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
145 orr(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
151 orrs(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
157 mov(Register rd, const ShifterOperand& so, Condition cond) argument
162 movs(Register rd, const ShifterOperand& so, Condition cond) argument
167 bic(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
173 mvn(Register rd, const ShifterOperand& so, Condition cond) argument
178 mvns(Register rd, const ShifterOperand& so, Condition cond) argument
183 mul(Register rd, Register rn, Register rm, Condition cond) argument
189 mla(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
196 mls(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
210 sdiv(Register rd, Register rn, Register rm, Condition cond) argument
226 udiv(Register rd, Register rn, Register rm, Condition cond) argument
242 sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
261 ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
280 ldr(Register rd, const Address& ad, Condition cond) argument
285 str(Register rd, const Address& ad, Condition cond) argument
290 ldrb(Register rd, const Address& ad, Condition cond) argument
295 strb(Register rd, const Address& ad, Condition cond) argument
300 ldrh(Register rd, const Address& ad, Condition cond) argument
305 strh(Register rd, const Address& ad, Condition cond) argument
310 ldrsb(Register rd, const Address& ad, Condition cond) argument
315 ldrsh(Register rd, const Address& ad, Condition cond) argument
320 ldrd(Register rd, const Address& ad, Condition cond) argument
326 strd(Register rd, const Address& ad, Condition cond) argument
583 EmitType01(Condition cond, int type, Opcode opcode, int set_cc, Register rn, Register rd, const ShifterOperand& so) argument
612 EmitMemOp(Condition cond, bool load, bool byte, Register rd, const Address& ad) argument
651 EmitMemOpAddressMode3(Condition cond, int32_t mode, Register rd, const Address& ad) argument
684 EmitShiftImmediate(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
701 EmitShiftRegister(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
731 clz(Register rd, Register rm, Condition cond) argument
745 movw(Register rd, uint16_t imm16, Condition cond) argument
754 movt(Register rd, uint16_t imm16, Condition cond) argument
763 EmitMulOp(Condition cond, int32_t opcode, Register rd, Register rn, Register rm, Register rs) argument
816 strex(Register rd, Register rt, Register rn, Condition cond) argument
834 strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) argument
1153 Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
1164 Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
1176 Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
1188 Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
1198 Rrx(Register rd, Register rm, bool setcc, Condition cond) argument
1207 Lsl(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
1217 Lsr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
1227 Asr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
1237 Ror(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
1290 Push(Register rd, Condition cond) argument
1295 Pop(Register rd, Condition cond) argument
1310 Mov(Register rd, Register rm, Condition cond) argument
1350 AddConstant(Register rd, int32_t value, Condition cond) argument
1355 AddConstant(Register rd, Register rn, int32_t value, Condition cond) argument
1391 AddConstantSetFlags(Register rd, Register rn, int32_t value, Condition cond) argument
1417 LoadImmediate(Register rd, int32_t value, Condition cond) argument
[all...] |
| H A D | assembler_thumb2.cc | 28 bool Thumb2Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED,
54 void Thumb2Assembler::and_(Register rd, Register rn, const ShifterOperand& so, argument
56 EmitDataProcessing(cond, AND, 0, rn, rd, so);
60 void Thumb2Assembler::eor(Register rd, Register rn, const ShifterOperand& so, argument
62 EmitDataProcessing(cond, EOR, 0, rn, rd, so);
66 void Thumb2Assembler::sub(Register rd, Register rn, const ShifterOperand& so, argument
68 EmitDataProcessing(cond, SUB, 0, rn, rd, so);
72 void Thumb2Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, argument
74 EmitDataProcessing(cond, RSB, 0, rn, rd, so);
78 void Thumb2Assembler::rsbs(Register rd, Registe argument
84 add(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
90 adds(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
96 subs(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
102 adc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
108 sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
114 rsc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
142 orr(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
148 orrs(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
154 mov(Register rd, const ShifterOperand& so, Condition cond) argument
159 movs(Register rd, const ShifterOperand& so, Condition cond) argument
164 bic(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
170 mvn(Register rd, const ShifterOperand& so, Condition cond) argument
175 mvns(Register rd, const ShifterOperand& so, Condition cond) argument
180 mul(Register rd, Register rn, Register rm, Condition cond) argument
205 mla(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
223 mls(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
259 sdiv(Register rd, Register rn, Register rm, Condition cond) argument
276 udiv(Register rd, Register rn, Register rm, Condition cond) argument
293 sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
314 ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
335 ldr(Register rd, const Address& ad, Condition cond) argument
340 str(Register rd, const Address& ad, Condition cond) argument
345 ldrb(Register rd, const Address& ad, Condition cond) argument
350 strb(Register rd, const Address& ad, Condition cond) argument
355 ldrh(Register rd, const Address& ad, Condition cond) argument
360 strh(Register rd, const Address& ad, Condition cond) argument
365 ldrsb(Register rd, const Address& ad, Condition cond) argument
370 ldrsh(Register rd, const Address& ad, Condition cond) argument
375 ldrd(Register rd, const Address& ad, Condition cond) argument
380 ldrd(Register rd, Register rd2, const Address& ad, Condition cond) argument
392 strd(Register rd, const Address& ad, Condition cond) argument
397 strd(Register rd, Register rd2, const Address& ad, Condition cond) argument
694 Is32BitDataProcessing(Condition cond ATTRIBUTE_UNUSED, Opcode opcode, bool set_cc, Register rn, Register rd, const ShifterOperand& so) argument
800 Emit32BitDataProcessing(Condition cond ATTRIBUTE_UNUSED, Opcode opcode, bool set_cc, Register rn, Register rd, const ShifterOperand& so) argument
885 Emit16BitDataProcessing(Condition cond, Opcode opcode, bool set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1049 Emit16BitAddSub(Condition cond ATTRIBUTE_UNUSED, Opcode opcode, bool set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1186 EmitDataProcessing(Condition cond, Opcode opcode, bool set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1202 EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, bool setcc) argument
1241 EmitShift(Register rd, Register rn, Shift shift, Register rm, bool setcc) argument
1359 EmitLoadStore(Condition cond, bool load, bool byte, bool half, bool is_signed, Register rd, const Address& ad) argument
1636 clz(Register rd, Register rm, Condition cond) argument
1653 movw(Register rd, uint16_t imm16, Condition cond) argument
1682 movt(Register rd, uint16_t imm16, Condition cond) argument
1720 strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond) argument
1756 strex(Register rd, Register rt, Register rn, Condition cond) argument
1764 strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) argument
2214 Push(Register rd, Condition cond) argument
2219 Pop(Register rd, Condition cond) argument
2234 Mov(Register rd, Register rm, Condition cond) argument
2320 Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
2328 Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
2337 Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
2346 Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
2354 Rrx(Register rd, Register rm, bool setcc, Condition cond) argument
2360 Lsl(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
2367 Lsr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
2374 Asr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
2381 Ror(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
2455 AddConstant(Register rd, int32_t value, Condition cond) argument
2460 AddConstant(Register rd, Register rn, int32_t value, Condition cond) argument
2496 AddConstantSetFlags(Register rd, Register rn, int32_t value, Condition cond) argument
2523 LoadImmediate(Register rd, int32_t value, Condition cond) argument
[all...] |
| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 42 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { argument
45 CHECK_NE(rd, kNoRegister);
49 static_cast<int32_t>(rd) << kRdShift |
163 void MipsAssembler::Add(Register rd, Register rs, Register rt) { argument
164 EmitR(0, rs, rt, rd, 0, 0x20);
167 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { argument
168 EmitR(0, rs, rt, rd, 0, 0x21);
179 void MipsAssembler::Sub(Register rd, Register rs, Register rt) { argument
180 EmitR(0, rs, rt, rd, 0, 0x22);
183 void MipsAssembler::Subu(Register rd, Registe argument
203 And(Register rd, Register rs, Register rt) argument
211 Or(Register rd, Register rs, Register rt) argument
219 Xor(Register rd, Register rs, Register rt) argument
227 Nor(Register rd, Register rs, Register rt) argument
231 Sll(Register rd, Register rs, int shamt) argument
235 Srl(Register rd, Register rs, int shamt) argument
239 Sra(Register rd, Register rs, int shamt) argument
243 Sllv(Register rd, Register rs, Register rt) argument
247 Srlv(Register rd, Register rs, Register rt) argument
251 Srav(Register rd, Register rs, Register rt) argument
279 Mfhi(Register rd) argument
283 Mflo(Register rd) argument
299 Slt(Register rd, Register rs, Register rt) argument
303 Sltu(Register rd, Register rs, Register rt) argument
435 Mul(Register rd, Register rs, Register rt) argument
440 Div(Register rd, Register rs, Register rt) argument
445 Rem(Register rd, Register rs, Register rt) argument
[all...] |
| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 33 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, argument
37 CHECK_NE(rd, kNoGpuRegister);
41 static_cast<uint32_t>(rd) << kRdShift |
94 void Mips64Assembler::Add(GpuRegister rd, GpuRegister rs, GpuRegister rt) { argument
95 EmitR(0, rs, rt, rd, 0, 0x20);
102 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { argument
103 EmitR(0, rs, rt, rd, 0, 0x21);
110 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { argument
111 EmitR(0, rs, rt, rd, 0, 0x2d);
118 void Mips64Assembler::Sub(GpuRegister rd, GpuRegiste argument
122 Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
126 Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
146 MulR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
150 DivR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
155 ModR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
160 DivuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
165 ModuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
170 MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
174 DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
178 ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
182 DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
186 ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
190 Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
194 Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
198 Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
202 Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
206 Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
210 And(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
218 Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
226 Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
234 Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
238 Seb(GpuRegister rd, GpuRegister rt) argument
242 Seh(GpuRegister rd, GpuRegister rt) argument
252 Sll(GpuRegister rd, GpuRegister rt, int shamt) argument
256 Srl(GpuRegister rd, GpuRegister rt, int shamt) argument
260 Sra(GpuRegister rd, GpuRegister rt, int shamt) argument
264 Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
268 Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
272 Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
276 Dsll(GpuRegister rd, GpuRegister rt, int shamt) argument
280 Dsrl(GpuRegister rd, GpuRegister rt, int shamt) argument
284 Dsra(GpuRegister rd, GpuRegister rt, int shamt) argument
288 Dsll32(GpuRegister rd, GpuRegister rt, int shamt) argument
292 Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) argument
296 Dsra32(GpuRegister rd, GpuRegister rt, int shamt) argument
300 Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
304 Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
308 Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
357 Mfhi(GpuRegister rd) argument
361 Mflo(GpuRegister rd) argument
381 Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
385 Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
417 Jalr(GpuRegister rd, GpuRegister rs) argument
620 Move(GpuRegister rd, GpuRegister rs) argument
624 Clear(GpuRegister rd) argument
628 Not(GpuRegister rd, GpuRegister rs) argument
632 LoadConst32(GpuRegister rd, int32_t value) argument
646 LoadConst64(GpuRegister rd, int64_t value) argument
[all...] |