Searched refs:INTEL_MSAA_LAYOUT_CMS (Results 1 - 8 of 8) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_tex_layout.c173 case INTEL_MSAA_LAYOUT_CMS:
H A Dbrw_blorp_blit.cpp730 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
1024 case INTEL_MSAA_LAYOUT_CMS:
1111 case INTEL_MSAA_LAYOUT_CMS:
1249 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
1301 if (i == 0 && key->tex_layout == INTEL_MSAA_LAYOUT_CMS) {
1348 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
1414 * INTEL_MSAA_LAYOUT_CMS.
1416 case INTEL_MSAA_LAYOUT_CMS:
1493 case INTEL_MSAA_LAYOUT_CMS:
1292 assert(stack_depth < ARRAY_SIZE(texture_data)); if (i == 0) { s_is_zero = true; } else { s_is_zero = false; brw_MOV(&func, S, brw_imm_uw(i)); } texel_fetch(texture_data[stack_depth++]); if (i == 0 && key->tex_layout == INTEL_MSAA_LAYOUT_CMS) argument
H A Dintel_mipmap_tree.c119 case INTEL_MSAA_LAYOUT_CMS:
333 return INTEL_MSAA_LAYOUT_CMS;
479 if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
796 * We set msaa_format to INTEL_MSAA_LAYOUT_CMS to force
810 INTEL_MSAA_LAYOUT_CMS);
H A Dgen7_blorp.cpp147 /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
195 if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
H A Dgen7_wm_surface_state.c571 if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
/external/mesa3d/src/mesa/drivers/dri/intel/
H A Dintel_mipmap_tree.h180 INTEL_MSAA_LAYOUT_CMS, enumerator in enum:intel_msaa_layout
H A Dintel_mipmap_tree.c119 case INTEL_MSAA_LAYOUT_CMS:
333 return INTEL_MSAA_LAYOUT_CMS;
479 if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
796 * We set msaa_format to INTEL_MSAA_LAYOUT_CMS to force
810 INTEL_MSAA_LAYOUT_CMS);
/external/mesa3d/src/mesa/drivers/dri/i915/
H A Dintel_mipmap_tree.c119 case INTEL_MSAA_LAYOUT_CMS:
333 return INTEL_MSAA_LAYOUT_CMS;
479 if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
796 * We set msaa_format to INTEL_MSAA_LAYOUT_CMS to force
810 INTEL_MSAA_LAYOUT_CMS);

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