Searched refs:msaa_layout (Results 1 - 10 of 10) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_blorp.cpp75 this->msaa_layout = mt->msaa_layout;
H A Dintel_mipmap_tree.c85 enum intel_msaa_layout msaa_layout)
107 mt->msaa_layout = msaa_layout;
113 switch (msaa_layout) {
137 enum intel_msaa_layout msaa_layout = local
149 msaa_layout);
197 enum intel_msaa_layout msaa_layout)
217 else if (msaa_layout != INTEL_MSAA_LAYOUT_NONE) {
238 false, num_samples, msaa_layout);
403 enum intel_msaa_layout msaa_layout local
75 intel_miptree_create_internal(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool for_region, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
187 intel_miptree_create(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
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H A Dbrw_blorp.h141 intel_msaa_layout msaa_layout; member in class:brw_blorp_surface_info
H A Dbrw_tex_layout.c171 switch (mt->msaa_layout) {
H A Dgen7_wm_surface_state.c518 assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
569 gen7_set_surface_msaa(surf, irb->mt->num_samples, irb->mt->msaa_layout);
571 if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
H A Dbrw_blorp_blit.cpp1692 if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS)
1742 compute_msaa_layout_for_pipeline(brw, src.num_samples, src.msaa_layout);
1744 compute_msaa_layout_for_pipeline(brw, dst.num_samples, dst.msaa_layout);
1749 wm_prog_key.src_layout = src_mt->msaa_layout;
1750 wm_prog_key.dst_layout = dst_mt->msaa_layout;
1774 assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS);
H A Dgen7_blorp.cpp194 gen7_set_surface_msaa(surf, surface->num_samples, surface->msaa_layout);
195 if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
/external/mesa3d/src/mesa/drivers/dri/intel/
H A Dintel_mipmap_tree.h244 enum intel_msaa_layout msaa_layout; member in struct:intel_mipmap_tree
382 enum intel_msaa_layout msaa_layout);
H A Dintel_mipmap_tree.c85 enum intel_msaa_layout msaa_layout)
107 mt->msaa_layout = msaa_layout;
113 switch (msaa_layout) {
137 enum intel_msaa_layout msaa_layout = local
149 msaa_layout);
197 enum intel_msaa_layout msaa_layout)
217 else if (msaa_layout != INTEL_MSAA_LAYOUT_NONE) {
238 false, num_samples, msaa_layout);
403 enum intel_msaa_layout msaa_layout local
75 intel_miptree_create_internal(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool for_region, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
187 intel_miptree_create(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
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/external/mesa3d/src/mesa/drivers/dri/i915/
H A Dintel_mipmap_tree.c85 enum intel_msaa_layout msaa_layout)
107 mt->msaa_layout = msaa_layout;
113 switch (msaa_layout) {
137 enum intel_msaa_layout msaa_layout = local
149 msaa_layout);
197 enum intel_msaa_layout msaa_layout)
217 else if (msaa_layout != INTEL_MSAA_LAYOUT_NONE) {
238 false, num_samples, msaa_layout);
403 enum intel_msaa_layout msaa_layout local
75 intel_miptree_create_internal(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool for_region, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
187 intel_miptree_create(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
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