/art/runtime/base/unix_file/ |
H A D | random_access_file_utils.h | 24 // Copies from 'src' to 'dst'. Reads all the data from 'src', and writes it 25 // to 'dst'. Not thread-safe. Neither file will be closed. 26 bool CopyFile(const RandomAccessFile& src, RandomAccessFile* dst);
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H A D | random_access_file_utils.cc | 23 bool CopyFile(const RandomAccessFile& src, RandomAccessFile* dst) { argument 30 if (dst->Write(&buf[0], n, offset) != n) {
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/art/runtime/base/ |
H A D | stringprintf.h | 29 // Appends a printf-like formatting of the arguments to 'dst'. 30 void StringAppendF(std::string* dst, const char* fmt, ...) 33 // Appends a printf-like formatting of the arguments to 'dst'. 34 void StringAppendV(std::string* dst, const char* format, va_list ap);
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H A D | stringprintf.cc | 23 void StringAppendV(std::string* dst, const char* format, va_list ap) { argument 38 dst->append(space, result); 60 dst->append(buf, result); 74 void StringAppendF(std::string* dst, const char* format, ...) { argument 77 StringAppendV(dst, format, ap);
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/art/compiler/utils/x86/ |
H A D | assembler_x86.h | 226 void movl(Register dst, const Immediate& src); 227 void movl(Register dst, Register src); 229 void movl(Register dst, const Address& src); 230 void movl(const Address& dst, Register src); 231 void movl(const Address& dst, const Immediate& imm); 232 void movl(const Address& dst, Label* lbl); 234 void bswapl(Register dst); 236 void movzxb(Register dst, ByteRegister src); 237 void movzxb(Register dst, const Address& src); 238 void movsxb(Register dst, ByteRegiste [all...] |
H A D | assembler_x86.cc | 106 void X86Assembler::movl(Register dst, const Immediate& imm) { argument 108 EmitUint8(0xB8 + dst); 113 void X86Assembler::movl(Register dst, Register src) { argument 116 EmitRegisterOperand(src, dst); 120 void X86Assembler::movl(Register dst, const Address& src) { argument 123 EmitOperand(dst, src); 127 void X86Assembler::movl(const Address& dst, Register src) { argument 130 EmitOperand(src, dst); 134 void X86Assembler::movl(const Address& dst, const Immediate& imm) { argument 137 EmitOperand(0, dst); 141 movl(const Address& dst, Label* lbl) argument 148 bswapl(Register dst) argument 154 movzxb(Register dst, ByteRegister src) argument 162 movzxb(Register dst, const Address& src) argument 170 movsxb(Register dst, ByteRegister src) argument 178 movsxb(Register dst, const Address& src) argument 191 movb(const Address& dst, ByteRegister src) argument 198 movb(const Address& dst, const Immediate& imm) argument 207 movzxw(Register dst, Register src) argument 215 movzxw(Register dst, const Address& src) argument 223 movsxw(Register dst, Register src) argument 231 movsxw(Register dst, const Address& src) argument 244 movw(const Address& dst, Register src) argument 252 movw(const Address& dst, const Immediate& imm) argument 263 leal(Register dst, const Address& src) argument 270 cmovl(Condition condition, Register dst, Register src) argument 278 setb(Condition condition, Register dst) argument 286 movaps(XmmRegister dst, XmmRegister src) argument 294 movss(XmmRegister dst, const Address& src) argument 303 movss(const Address& dst, XmmRegister src) argument 312 movss(XmmRegister dst, XmmRegister src) argument 321 movd(XmmRegister dst, Register src) argument 330 movd(Register dst, XmmRegister src) argument 339 addss(XmmRegister dst, XmmRegister src) argument 348 addss(XmmRegister dst, const Address& src) argument 357 subss(XmmRegister dst, XmmRegister src) argument 366 subss(XmmRegister dst, const Address& src) argument 375 mulss(XmmRegister dst, XmmRegister src) argument 384 mulss(XmmRegister dst, const Address& src) argument 393 divss(XmmRegister dst, XmmRegister src) argument 402 divss(XmmRegister dst, const Address& src) argument 418 fsts(const Address& dst) argument 425 fstps(const Address& dst) argument 432 movsd(XmmRegister dst, const Address& src) argument 441 movsd(const Address& dst, XmmRegister src) argument 450 movsd(XmmRegister dst, XmmRegister src) argument 459 movhpd(XmmRegister dst, const Address& src) argument 468 movhpd(const Address& dst, XmmRegister src) argument 501 punpckldq(XmmRegister dst, XmmRegister src) argument 510 addsd(XmmRegister dst, XmmRegister src) argument 519 addsd(XmmRegister dst, const Address& src) argument 528 subsd(XmmRegister dst, XmmRegister src) argument 537 subsd(XmmRegister dst, const Address& src) argument 546 mulsd(XmmRegister dst, XmmRegister src) argument 555 mulsd(XmmRegister dst, const Address& src) argument 564 divsd(XmmRegister dst, XmmRegister src) argument 573 divsd(XmmRegister dst, const Address& src) argument 582 cvtsi2ss(XmmRegister dst, Register src) argument 591 cvtsi2sd(XmmRegister dst, Register src) argument 600 cvtss2si(Register dst, XmmRegister src) argument 609 cvtss2sd(XmmRegister dst, XmmRegister src) argument 618 cvtsd2si(Register dst, XmmRegister src) argument 627 cvttss2si(Register dst, XmmRegister src) argument 636 cvttsd2si(Register dst, XmmRegister src) argument 645 cvtsd2ss(XmmRegister dst, XmmRegister src) argument 654 cvtdq2pd(XmmRegister dst, XmmRegister src) argument 697 roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument 708 roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) argument 719 sqrtsd(XmmRegister dst, XmmRegister src) argument 728 sqrtss(XmmRegister dst, XmmRegister src) argument 737 xorpd(XmmRegister dst, const Address& src) argument 746 xorpd(XmmRegister dst, XmmRegister src) argument 755 andps(XmmRegister dst, XmmRegister src) argument 763 andpd(XmmRegister dst, XmmRegister src) argument 772 orpd(XmmRegister dst, XmmRegister src) argument 781 xorps(XmmRegister dst, const Address& src) argument 789 orps(XmmRegister dst, XmmRegister src) argument 797 xorps(XmmRegister dst, XmmRegister src) argument 805 andps(XmmRegister dst, const Address& src) argument 813 andpd(XmmRegister dst, const Address& src) argument 829 fstl(const Address& dst) argument 836 fstpl(const Address& dst) argument 851 fnstcw(const Address& dst) argument 865 fistpl(const Address& dst) argument 872 fistps(const Address& dst) argument 943 xchgl(Register dst, Register src) argument 984 addl(Register dst, Register src) argument 1050 andl(Register dst, Register src) argument 1064 andl(Register dst, const Immediate& imm) argument 1070 orl(Register dst, Register src) argument 1084 orl(Register dst, const Immediate& imm) argument 1090 xorl(Register dst, Register src) argument 1104 xorl(Register dst, const Immediate& imm) argument 1135 adcl(Register dst, Register src) argument 1142 adcl(Register dst, const Address& address) argument 1149 subl(Register dst, Register src) argument 1189 imull(Register dst, Register src) argument 1241 sbbl(Register dst, Register src) argument 1254 sbbl(Register dst, const Address& address) argument 1354 shld(Register dst, Register src, Register shifter) argument 1363 shld(Register dst, Register src, const Immediate& imm) argument 1372 shrd(Register dst, Register src, Register shifter) argument 1381 shrd(Register dst, Register src, const Immediate& imm) argument 1581 LoadLongConstant(XmmRegister dst, int64_t value) argument 1590 LoadDoubleConstant(XmmRegister dst, double value) argument [all...] |
/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64.h | 324 void movq(CpuRegister dst, const Immediate& src); 325 void movl(CpuRegister dst, const Immediate& src); 326 void movq(CpuRegister dst, CpuRegister src); 327 void movl(CpuRegister dst, CpuRegister src); 329 void movq(CpuRegister dst, const Address& src); 330 void movl(CpuRegister dst, const Address& src); 331 void movq(const Address& dst, CpuRegister src); 332 void movq(const Address& dst, const Immediate& src); 333 void movl(const Address& dst, CpuRegister src); 334 void movl(const Address& dst, cons [all...] |
H A D | assembler_x86_64.cc | 106 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { argument 110 EmitRex64(dst); 112 EmitRegisterOperand(0, dst.LowBits()); 115 EmitRex64(dst); 116 EmitUint8(0xB8 + dst.LowBits()); 122 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { argument 125 EmitOptionalRex32(dst); 126 EmitUint8(0xB8 + dst.LowBits()); 131 void X86_64Assembler::movq(const Address& dst, const Immediate& imm) { argument 134 EmitRex64(dst); 141 movq(CpuRegister dst, CpuRegister src) argument 150 movl(CpuRegister dst, CpuRegister src) argument 158 movq(CpuRegister dst, const Address& src) argument 166 movl(CpuRegister dst, const Address& src) argument 174 movq(const Address& dst, CpuRegister src) argument 182 movl(const Address& dst, CpuRegister src) argument 189 movl(const Address& dst, const Immediate& imm) argument 198 cmov(Condition c, CpuRegister dst, CpuRegister src) argument 202 cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit) argument 211 movzxb(CpuRegister dst, CpuRegister src) argument 220 movzxb(CpuRegister dst, const Address& src) argument 231 movsxb(CpuRegister dst, CpuRegister src) argument 240 movsxb(CpuRegister dst, const Address& src) argument 256 movb(const Address& dst, CpuRegister src) argument 264 movb(const Address& dst, const Immediate& imm) argument 274 movzxw(CpuRegister dst, CpuRegister src) argument 283 movzxw(CpuRegister dst, const Address& src) argument 292 movsxw(CpuRegister dst, CpuRegister src) argument 301 movsxw(CpuRegister dst, const Address& src) argument 315 movw(const Address& dst, CpuRegister src) argument 324 movw(const Address& dst, const Immediate& imm) argument 336 leaq(CpuRegister dst, const Address& src) argument 344 leal(CpuRegister dst, const Address& src) argument 352 movaps(XmmRegister dst, XmmRegister src) argument 361 movss(XmmRegister dst, const Address& src) argument 371 movss(const Address& dst, XmmRegister src) argument 381 movss(XmmRegister dst, XmmRegister src) argument 391 movsxd(CpuRegister dst, CpuRegister src) argument 399 movsxd(CpuRegister dst, const Address& src) argument 407 movd(XmmRegister dst, CpuRegister src) argument 411 movd(CpuRegister dst, XmmRegister src) argument 415 movd(XmmRegister dst, CpuRegister src, bool is64bit) argument 424 movd(CpuRegister dst, XmmRegister src, bool is64bit) argument 434 addss(XmmRegister dst, XmmRegister src) argument 444 addss(XmmRegister dst, const Address& src) argument 454 subss(XmmRegister dst, XmmRegister src) argument 464 subss(XmmRegister dst, const Address& src) argument 474 mulss(XmmRegister dst, XmmRegister src) argument 484 mulss(XmmRegister dst, const Address& src) argument 494 divss(XmmRegister dst, XmmRegister src) argument 504 divss(XmmRegister dst, const Address& src) argument 521 fsts(const Address& dst) argument 528 fstps(const Address& dst) argument 535 movsd(XmmRegister dst, const Address& src) argument 545 movsd(const Address& dst, XmmRegister src) argument 555 movsd(XmmRegister dst, XmmRegister src) argument 565 addsd(XmmRegister dst, XmmRegister src) argument 575 addsd(XmmRegister dst, const Address& src) argument 585 subsd(XmmRegister dst, XmmRegister src) argument 595 subsd(XmmRegister dst, const Address& src) argument 605 mulsd(XmmRegister dst, XmmRegister src) argument 615 mulsd(XmmRegister dst, const Address& src) argument 625 divsd(XmmRegister dst, XmmRegister src) argument 635 divsd(XmmRegister dst, const Address& src) argument 645 cvtsi2ss(XmmRegister dst, CpuRegister src) argument 650 cvtsi2ss(XmmRegister dst, CpuRegister src, bool is64bit) argument 665 cvtsi2ss(XmmRegister dst, const Address& src, bool is64bit) argument 680 cvtsi2sd(XmmRegister dst, CpuRegister src) argument 685 cvtsi2sd(XmmRegister dst, CpuRegister src, bool is64bit) argument 700 cvtsi2sd(XmmRegister dst, const Address& src, bool is64bit) argument 715 cvtss2si(CpuRegister dst, XmmRegister src) argument 725 cvtss2sd(XmmRegister dst, XmmRegister src) argument 735 cvtss2sd(XmmRegister dst, const Address& src) argument 745 cvtsd2si(CpuRegister dst, XmmRegister src) argument 755 cvttss2si(CpuRegister dst, XmmRegister src) argument 760 cvttss2si(CpuRegister dst, XmmRegister src, bool is64bit) argument 775 cvttsd2si(CpuRegister dst, XmmRegister src) argument 780 cvttsd2si(CpuRegister dst, XmmRegister src, bool is64bit) argument 795 cvtsd2ss(XmmRegister dst, XmmRegister src) argument 805 cvtsd2ss(XmmRegister dst, const Address& src) argument 815 cvtdq2pd(XmmRegister dst, XmmRegister src) argument 901 roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument 913 roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) argument 925 sqrtsd(XmmRegister dst, XmmRegister src) argument 935 sqrtss(XmmRegister dst, XmmRegister src) argument 945 xorpd(XmmRegister dst, const Address& src) argument 955 xorpd(XmmRegister dst, XmmRegister src) argument 965 xorps(XmmRegister dst, const Address& src) argument 974 xorps(XmmRegister dst, XmmRegister src) argument 983 andpd(XmmRegister dst, const Address& src) argument 992 andpd(XmmRegister dst, XmmRegister src) argument 1001 andps(XmmRegister dst, XmmRegister src) argument 1009 orpd(XmmRegister dst, XmmRegister src) argument 1018 orps(XmmRegister dst, XmmRegister src) argument 1033 fstl(const Address& dst) argument 1040 fstpl(const Address& dst) argument 1055 fnstcw(const Address& dst) argument 1069 fistpl(const Address& dst) argument 1076 fistps(const Address& dst) argument 1146 xchgl(CpuRegister dst, CpuRegister src) argument 1166 xchgq(CpuRegister dst, CpuRegister src) argument 1277 addl(CpuRegister dst, CpuRegister src) argument 1351 andl(CpuRegister dst, CpuRegister src) argument 1367 andl(CpuRegister dst, const Immediate& imm) argument 1382 andq(CpuRegister dst, CpuRegister src) argument 1390 andq(CpuRegister dst, const Address& src) argument 1398 orl(CpuRegister dst, CpuRegister src) argument 1414 orl(CpuRegister dst, const Immediate& imm) argument 1421 orq(CpuRegister dst, const Immediate& imm) argument 1429 orq(CpuRegister dst, CpuRegister src) argument 1437 orq(CpuRegister dst, const Address& src) argument 1445 xorl(CpuRegister dst, CpuRegister src) argument 1461 xorl(CpuRegister dst, const Immediate& imm) argument 1468 xorq(CpuRegister dst, CpuRegister src) argument 1476 xorq(CpuRegister dst, const Immediate& imm) argument 1483 xorq(CpuRegister dst, const Address& src) argument 1559 addq(CpuRegister dst, const Address& address) argument 1567 addq(CpuRegister dst, CpuRegister src) argument 1591 subl(CpuRegister dst, CpuRegister src) argument 1614 subq(CpuRegister dst, CpuRegister src) argument 1667 imull(CpuRegister dst, CpuRegister src) argument 1706 imulq(CpuRegister dst, CpuRegister src) argument 1719 imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm) argument 2042 setcc(Condition condition, CpuRegister dst) argument 2053 bswapl(CpuRegister dst) argument 2060 bswapq(CpuRegister dst) argument 2076 LoadDoubleConstant(XmmRegister dst, double value) argument 2242 EmitOptionalRex32(CpuRegister dst, CpuRegister src) argument 2246 EmitOptionalRex32(XmmRegister dst, XmmRegister src) argument 2250 EmitOptionalRex32(CpuRegister dst, XmmRegister src) argument 2254 EmitOptionalRex32(XmmRegister dst, CpuRegister src) argument 2265 EmitOptionalRex32(CpuRegister dst, const Operand& operand) argument 2275 EmitOptionalRex32(XmmRegister dst, const Operand& operand) argument 2299 EmitRex64(CpuRegister dst, CpuRegister src) argument 2303 EmitRex64(XmmRegister dst, CpuRegister src) argument 2307 EmitRex64(CpuRegister dst, XmmRegister src) argument 2311 EmitRex64(CpuRegister dst, const Operand& operand) argument 2319 EmitRex64(XmmRegister dst, const Operand& operand) argument 2327 EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src) argument 2333 EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) argument [all...] |
/art/runtime/ |
H A D | monitor_android.cc | 37 static char* EventLogWriteInt(char* dst, int value) { argument 38 *dst++ = EVENT_TYPE_INT; 39 Set4LE(reinterpret_cast<uint8_t*>(dst), value); 40 return dst + 4; 43 static char* EventLogWriteString(char* dst, const char* value, size_t len) { argument 44 *dst++ = EVENT_TYPE_STRING; 46 Set4LE(reinterpret_cast<uint8_t*>(dst), len); 47 dst += 4; 48 memcpy(dst, value, len); 49 return dst [all...] |
H A D | reflection-inl.h | 33 const JValue& src, JValue* dst) { 36 dst->SetJ(src.GetJ()); 47 dst->SetS(src.GetI()); 54 dst->SetI(src.GetI()); 61 dst->SetJ(src.GetI()); 68 dst->SetF(src.GetI()); 71 dst->SetF(src.GetJ()); 78 dst->SetD(src.GetI()); 81 dst->SetD(src.GetJ()); 84 dst 31 ConvertPrimitiveValue(bool unbox_for_result, Primitive::Type srcType, Primitive::Type dstType, const JValue& src, JValue* dst) argument [all...] |
H A D | dex_file_verifier_test.cc | 94 std::unique_ptr<uint8_t[]> dst(new uint8_t[tmp.size()]); 100 std::copy(tmp.begin(), tmp.end(), dst.get()); 101 return dst.release();
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H A D | reflection.h | 45 const JValue& src, JValue* dst)
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H A D | dex_file_test.cc | 100 std::unique_ptr<uint8_t[]> dst(new uint8_t[tmp.size()]); 106 std::copy(tmp.begin(), tmp.end(), dst.get()); 107 return dst.release();
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/art/runtime/jdwp/ |
H A D | jdwp_bits.h | 100 static inline void Write1BE(uint8_t** dst, uint8_t value) { argument 101 Set1(*dst, value); 102 *dst += sizeof(value); 105 static inline void Write2BE(uint8_t** dst, uint16_t value) { argument 106 Set2BE(*dst, value); 107 *dst += sizeof(value); 110 static inline void Write4BE(uint8_t** dst, uint32_t value) { argument 111 Set4BE(*dst, value); 112 *dst += sizeof(value); 115 static inline void Write8BE(uint8_t** dst, uint64_ argument [all...] |
/art/compiler/utils/arm/ |
H A D | assembler_arm.cc | 533 ArmManagedRegister dst = mdest.AsArm(); 534 CHECK(dst.IsCoreRegister() && dst.IsCoreRegister()) << dst; 535 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), 538 rsb(dst.AsCoreRegister(), dst.AsCoreRegister(), ShifterOperand(0)); 543 ArmManagedRegister dst = mdest.AsArm(); 544 CHECK(dst.IsCoreRegister()) << dst; [all...] |
/art/test/201-built-in-exception-detail-messages/src/ |
H A D | Main.java | 136 Integer[] dst = new Integer[10]; 137 System.arraycopy(src, 1, dst, 0, 5); 145 int[] dst = new int[1]; 146 System.arraycopy(src, 0, dst, 0, 1); 148 assertEquals("Incompatible types: src=java.lang.String[], dst=int[]", ex.getMessage()); 153 Runnable[] dst = new Runnable[1]; 154 System.arraycopy(src, 0, dst, 0, 1); 156 assertEquals("Incompatible types: src=float[], dst=java.lang.Runnable[]", ex.getMessage()); 161 double[][] dst = new double[1][]; 162 System.arraycopy(src, 0, dst, [all...] |
/art/compiler/optimizing/ |
H A D | code_generator_mips64.cc | 800 GpuRegister dst = location.AsRegister<GpuRegister>(); local 802 __ LoadConst32(dst, GetInt32ValueOf(instruction->AsConstant())); 804 __ LoadConst64(dst, instruction->AsLongConstant()->GetValue()); 1057 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 1072 __ Andi(dst, lhs, rhs_imm); 1074 __ And(dst, lhs, rhs_reg); 1077 __ Ori(dst, lhs, rhs_imm); 1079 __ Or(dst, lhs, rhs_reg); 1082 __ Xori(dst, lhs, rhs_imm); 1084 __ Xor(dst, lh 1115 FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>(); local 1164 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 1687 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 1732 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 1840 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 1851 FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>(); local 2148 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 2152 FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>(); local 2616 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 2627 FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>(); local 2669 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 2679 FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>(); local 2750 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 2889 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 3096 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); local 3130 FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>(); local 3162 FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>(); local [all...] |
H A D | code_generator_arm64.cc | 551 Register dst = RegisterFrom(location, type); local 552 DCHECK(((instruction->IsIntConstant() || instruction->IsNullConstant()) && dst.Is32Bits()) || 553 (instruction->IsLongConstant() && dst.Is64Bits())); 554 __ Mov(dst, value); 757 CPURegister dst = CPURegisterFrom(destination, type); local 759 DCHECK(dst.Is64Bits() == source.IsDoubleStackSlot()); 760 __ Ldr(dst, StackOperandFrom(source)); 763 MoveConstant(dst, source.GetConstant()); 766 __ Mov(Register(dst), RegisterFrom(source, type)); 769 __ Fmov(FPRegister(dst), FPRegisterFro 814 Load(Primitive::Type type, CPURegister dst, const MemOperand& src) argument 843 LoadAcquire(HInstruction* instruction, CPURegister dst, const MemOperand& src) argument 900 Store(Primitive::Type type, CPURegister src, const MemOperand& dst) argument 906 __ Strb(Register(src), dst); local 910 __ Strh(Register(src), dst); local 925 StoreRelease(Primitive::Type type, CPURegister src, const MemOperand& dst) argument 1208 Register dst = OutputRegister(instr); local 1227 FPRegister dst = OutputFPRegister(instr); local 1269 Register dst = OutputRegister(instr); local [all...] |
H A D | code_generator_arm64.h | 325 void Load(Primitive::Type type, vixl::CPURegister dst, const vixl::MemOperand& src); 326 void Store(Primitive::Type type, vixl::CPURegister rt, const vixl::MemOperand& dst); 328 void LoadAcquire(HInstruction* instruction, vixl::CPURegister dst, const vixl::MemOperand& src); 329 void StoreRelease(Primitive::Type type, vixl::CPURegister rt, const vixl::MemOperand& dst);
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H A D | code_generator_x86.h | 109 void MoveMemoryToMemory32(int dst, int src); 110 void MoveMemoryToMemory64(int dst, int src);
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/art/runtime/native/ |
H A D | libcore_util_CharsetUtils.cc | 122 jchar* dst = &chars[0]; local 126 *dst++ = (ch <= 0x7f) ? ch : REPLACEMENT_CHAR; 142 jchar* dst = &chars[0]; local 144 *dst++ = static_cast<jchar>(*src++ & 0xff); 169 jbyte* dst = &bytes[0]; local 175 *dst++ = static_cast<jbyte>(ch);
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/art/compiler/utils/arm64/ |
H A D | assembler_arm64.cc | 291 Arm64ManagedRegister dst = m_dst.AsArm64(); local 292 CHECK(dst.IsXRegister()) << dst; 293 LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), SP, offs.Int32Value()); 298 Arm64ManagedRegister dst = m_dst.AsArm64(); local 300 CHECK(dst.IsXRegister() && base.IsXRegister()); 301 LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), base.AsXRegister(), 304 WRegister ref_reg = dst.AsOverlappingWRegister(); 310 Arm64ManagedRegister dst = m_dst.AsArm64(); local 312 CHECK(dst 320 Arm64ManagedRegister dst = m_dst.AsArm64(); local 327 Arm64ManagedRegister dst = m_dst.AsArm64(); local [all...] |
H A D | assembler_arm64.h | 164 // src holds a handle scope entry (Object**) load this into dst. 165 void LoadReferenceFromHandleScope(ManagedRegister dst, ManagedRegister src) OVERRIDE; 223 void Load(Arm64ManagedRegister dst, XRegister src, int32_t src_offset, size_t size);
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/art/compiler/utils/mips/ |
H A D | assembler_mips.cc | 460 MipsManagedRegister dst = m_dst.AsMips(); local 461 if (dst.IsNoRegister()) { 462 CHECK_EQ(0u, size) << dst; 463 } else if (dst.IsCoreRegister()) { 464 CHECK_EQ(4u, size) << dst; 465 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), src_register, src_offset); 466 } else if (dst.IsRegisterPair()) { 467 CHECK_EQ(8u, size) << dst; 468 LoadFromOffset(kLoadWord, dst.AsRegisterPairLow(), src_register, src_offset); 469 LoadFromOffset(kLoadWord, dst [all...] |
/art/compiler/ |
H A D | image_writer.h | 195 uint8_t* dst = image_->Begin() + offset; local 196 return reinterpret_cast<mirror::Object*>(dst); 271 void FixupPointerArray(mirror::Object* dst, mirror::PointerArray* arr, mirror::Class* klass,
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