target_arm64.cc revision 5d7cdec7527f8043bf15e23a0041c40156727243 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "codegen_arm64.h"
18
19#include <inttypes.h>
20
21#include <string>
22
23#include "dex/compiler_internals.h"
24#include "dex/quick/mir_to_lir-inl.h"
25#include "dex/reg_storage_eq.h"
26
27namespace art {
28
29static constexpr RegStorage core_regs_arr[] =
30    {rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7,
31     rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15,
32     rs_w16, rs_w17, rs_w18, rs_w19, rs_w20, rs_w21, rs_w22, rs_w23,
33     rs_w24, rs_w25, rs_w26, rs_w27, rs_w28, rs_w29, rs_w30, rs_w31,
34     rs_wzr};
35static constexpr RegStorage core64_regs_arr[] =
36    {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7,
37     rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15,
38     rs_x16, rs_x17, rs_x18, rs_x19, rs_x20, rs_x21, rs_x22, rs_x23,
39     rs_x24, rs_x25, rs_x26, rs_x27, rs_x28, rs_x29, rs_x30, rs_x31,
40     rs_xzr};
41static constexpr RegStorage sp_regs_arr[] =
42    {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7,
43     rs_f8, rs_f9, rs_f10, rs_f11, rs_f12, rs_f13, rs_f14, rs_f15,
44     rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23,
45     rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31};
46static constexpr RegStorage dp_regs_arr[] =
47    {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7,
48     rs_d8, rs_d9, rs_d10, rs_d11, rs_d12, rs_d13, rs_d14, rs_d15,
49     rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23,
50     rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31};
51// Note: we are not able to call to C function since rs_xSELF is a special register need to be
52// preserved but would be scratched by native functions follow aapcs64.
53static constexpr RegStorage reserved_regs_arr[] =
54    {rs_wSUSPEND, rs_wSELF, rs_wsp, rs_wLR, rs_wzr};
55static constexpr RegStorage reserved64_regs_arr[] =
56    {rs_xSUSPEND, rs_xSELF, rs_sp, rs_xLR, rs_xzr};
57static constexpr RegStorage core_temps_arr[] =
58    {rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7,
59     rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15, rs_w16,
60     rs_w17};
61static constexpr RegStorage core64_temps_arr[] =
62    {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7,
63     rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, rs_x16,
64     rs_x17};
65static constexpr RegStorage sp_temps_arr[] =
66    {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7,
67     rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23,
68     rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31};
69static constexpr RegStorage dp_temps_arr[] =
70    {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7,
71     rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23,
72     rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31};
73
74static constexpr ArrayRef<const RegStorage> core_regs(core_regs_arr);
75static constexpr ArrayRef<const RegStorage> core64_regs(core64_regs_arr);
76static constexpr ArrayRef<const RegStorage> sp_regs(sp_regs_arr);
77static constexpr ArrayRef<const RegStorage> dp_regs(dp_regs_arr);
78static constexpr ArrayRef<const RegStorage> reserved_regs(reserved_regs_arr);
79static constexpr ArrayRef<const RegStorage> reserved64_regs(reserved64_regs_arr);
80static constexpr ArrayRef<const RegStorage> core_temps(core_temps_arr);
81static constexpr ArrayRef<const RegStorage> core64_temps(core64_temps_arr);
82static constexpr ArrayRef<const RegStorage> sp_temps(sp_temps_arr);
83static constexpr ArrayRef<const RegStorage> dp_temps(dp_temps_arr);
84
85RegLocation Arm64Mir2Lir::LocCReturn() {
86  return arm_loc_c_return;
87}
88
89RegLocation Arm64Mir2Lir::LocCReturnRef() {
90  return arm_loc_c_return_ref;
91}
92
93RegLocation Arm64Mir2Lir::LocCReturnWide() {
94  return arm_loc_c_return_wide;
95}
96
97RegLocation Arm64Mir2Lir::LocCReturnFloat() {
98  return arm_loc_c_return_float;
99}
100
101RegLocation Arm64Mir2Lir::LocCReturnDouble() {
102  return arm_loc_c_return_double;
103}
104
105// Return a target-dependent special register.
106RegStorage Arm64Mir2Lir::TargetReg(SpecialTargetRegister reg) {
107  RegStorage res_reg = RegStorage::InvalidReg();
108  switch (reg) {
109    case kSelf: res_reg = rs_wSELF; break;
110    case kSuspend: res_reg = rs_wSUSPEND; break;
111    case kLr: res_reg =  rs_wLR; break;
112    case kPc: res_reg = RegStorage::InvalidReg(); break;
113    case kSp: res_reg =  rs_wsp; break;
114    case kArg0: res_reg = rs_w0; break;
115    case kArg1: res_reg = rs_w1; break;
116    case kArg2: res_reg = rs_w2; break;
117    case kArg3: res_reg = rs_w3; break;
118    case kArg4: res_reg = rs_w4; break;
119    case kArg5: res_reg = rs_w5; break;
120    case kArg6: res_reg = rs_w6; break;
121    case kArg7: res_reg = rs_w7; break;
122    case kFArg0: res_reg = rs_f0; break;
123    case kFArg1: res_reg = rs_f1; break;
124    case kFArg2: res_reg = rs_f2; break;
125    case kFArg3: res_reg = rs_f3; break;
126    case kFArg4: res_reg = rs_f4; break;
127    case kFArg5: res_reg = rs_f5; break;
128    case kFArg6: res_reg = rs_f6; break;
129    case kFArg7: res_reg = rs_f7; break;
130    case kRet0: res_reg = rs_w0; break;
131    case kRet1: res_reg = rs_w1; break;
132    case kInvokeTgt: res_reg = rs_wLR; break;
133    case kHiddenArg: res_reg = rs_wIP1; break;
134    case kHiddenFpArg: res_reg = RegStorage::InvalidReg(); break;
135    case kCount: res_reg = RegStorage::InvalidReg(); break;
136    default: res_reg = RegStorage::InvalidReg();
137  }
138  return res_reg;
139}
140
141/*
142 * Decode the register id. This routine makes assumptions on the encoding made by RegStorage.
143 */
144ResourceMask Arm64Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const {
145  // TODO(Arm64): this function depends too much on the internal RegStorage encoding. Refactor.
146
147  // Check if the shape mask is zero (i.e. invalid).
148  if (UNLIKELY(reg == rs_wzr || reg == rs_xzr)) {
149    // The zero register is not a true register. It is just an immediate zero.
150    return kEncodeNone;
151  }
152
153  return ResourceMask::Bit(
154      // FP register starts at bit position 32.
155      (reg.IsFloat() ? kArm64FPReg0 : 0) + reg.GetRegNum());
156}
157
158ResourceMask Arm64Mir2Lir::GetPCUseDefEncoding() const {
159  // Note: On arm64, we are not able to set pc except branch instructions, which is regarded as a
160  //       kind of barrier. All other instructions only use pc, which has no dependency between any
161  //       of them. So it is fine to just return kEncodeNone here.
162  return kEncodeNone;
163}
164
165// Arm64 specific setup.  TODO: inline?:
166void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags,
167                                            ResourceMask* use_mask, ResourceMask* def_mask) {
168  DCHECK_EQ(cu_->instruction_set, kArm64);
169  DCHECK(!lir->flags.use_def_invalid);
170
171  // Note: REG_USE_PC is ignored, the reason is the same with what we do in GetPCUseDefEncoding().
172  // These flags are somewhat uncommon - bypass if we can.
173  if ((flags & (REG_DEF_SP | REG_USE_SP | REG_DEF_LR)) != 0) {
174    if (flags & REG_DEF_SP) {
175      def_mask->SetBit(kArm64RegSP);
176    }
177
178    if (flags & REG_USE_SP) {
179      use_mask->SetBit(kArm64RegSP);
180    }
181
182    if (flags & REG_DEF_LR) {
183      def_mask->SetBit(kArm64RegLR);
184    }
185  }
186}
187
188ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) {
189  ArmConditionCode res;
190  switch (ccode) {
191    case kCondEq: res = kArmCondEq; break;
192    case kCondNe: res = kArmCondNe; break;
193    case kCondCs: res = kArmCondCs; break;
194    case kCondCc: res = kArmCondCc; break;
195    case kCondUlt: res = kArmCondCc; break;
196    case kCondUge: res = kArmCondCs; break;
197    case kCondMi: res = kArmCondMi; break;
198    case kCondPl: res = kArmCondPl; break;
199    case kCondVs: res = kArmCondVs; break;
200    case kCondVc: res = kArmCondVc; break;
201    case kCondHi: res = kArmCondHi; break;
202    case kCondLs: res = kArmCondLs; break;
203    case kCondGe: res = kArmCondGe; break;
204    case kCondLt: res = kArmCondLt; break;
205    case kCondGt: res = kArmCondGt; break;
206    case kCondLe: res = kArmCondLe; break;
207    case kCondAl: res = kArmCondAl; break;
208    case kCondNv: res = kArmCondNv; break;
209    default:
210      LOG(FATAL) << "Bad condition code " << ccode;
211      res = static_cast<ArmConditionCode>(0);  // Quiet gcc
212  }
213  return res;
214}
215
216static const char *shift_names[4] = {
217  "lsl",
218  "lsr",
219  "asr",
220  "ror"
221};
222
223static const char* extend_names[8] = {
224  "uxtb",
225  "uxth",
226  "uxtw",
227  "uxtx",
228  "sxtb",
229  "sxth",
230  "sxtw",
231  "sxtx",
232};
233
234/* Decode and print a register extension (e.g. ", uxtb #1") */
235static void DecodeRegExtendOrShift(int operand, char *buf, size_t buf_size) {
236  if ((operand & (1 << 6)) == 0) {
237    const char *shift_name = shift_names[(operand >> 7) & 0x3];
238    int amount = operand & 0x3f;
239    snprintf(buf, buf_size, ", %s #%d", shift_name, amount);
240  } else {
241    const char *extend_name = extend_names[(operand >> 3) & 0x7];
242    int amount = operand & 0x7;
243    if (amount == 0) {
244      snprintf(buf, buf_size, ", %s", extend_name);
245    } else {
246      snprintf(buf, buf_size, ", %s #%d", extend_name, amount);
247    }
248  }
249}
250
251#define BIT_MASK(w) ((UINT64_C(1) << (w)) - UINT64_C(1))
252
253static uint64_t RotateRight(uint64_t value, unsigned rotate, unsigned width) {
254  DCHECK_LE(width, 64U);
255  rotate &= 63;
256  value = value & BIT_MASK(width);
257  return ((value & BIT_MASK(rotate)) << (width - rotate)) | (value >> rotate);
258}
259
260static uint64_t RepeatBitsAcrossReg(bool is_wide, uint64_t value, unsigned width) {
261  unsigned i;
262  unsigned reg_size = (is_wide) ? 64 : 32;
263  uint64_t result = value & BIT_MASK(width);
264  for (i = width; i < reg_size; i *= 2) {
265    result |= (result << i);
266  }
267  DCHECK_EQ(i, reg_size);
268  return result;
269}
270
271/**
272 * @brief Decode an immediate in the form required by logical instructions.
273 *
274 * @param is_wide Whether @p value encodes a 64-bit (as opposed to 32-bit) immediate.
275 * @param value The encoded logical immediates that is to be decoded.
276 * @return The decoded logical immediate.
277 * @note This is the inverse of Arm64Mir2Lir::EncodeLogicalImmediate().
278 */
279uint64_t Arm64Mir2Lir::DecodeLogicalImmediate(bool is_wide, int value) {
280  unsigned n     = (value >> 12) & 0x01;
281  unsigned imm_r = (value >>  6) & 0x3f;
282  unsigned imm_s = (value >>  0) & 0x3f;
283
284  // An integer is constructed from the n, imm_s and imm_r bits according to
285  // the following table:
286  //
287  // N   imms immr  size S             R
288  // 1 ssssss rrrrrr 64  UInt(ssssss) UInt(rrrrrr)
289  // 0 0sssss xrrrrr 32  UInt(sssss)  UInt(rrrrr)
290  // 0 10ssss xxrrrr 16  UInt(ssss)   UInt(rrrr)
291  // 0 110sss xxxrrr 8   UInt(sss)    UInt(rrr)
292  // 0 1110ss xxxxrr 4   UInt(ss)     UInt(rr)
293  // 0 11110s xxxxxr 2   UInt(s)      UInt(r)
294  // (s bits must not be all set)
295  //
296  // A pattern is constructed of size bits, where the least significant S+1
297  // bits are set. The pattern is rotated right by R, and repeated across a
298  // 32 or 64-bit value, depending on destination register width.
299
300  if (n == 1) {
301    DCHECK_NE(imm_s, 0x3fU);
302    uint64_t bits = BIT_MASK(imm_s + 1);
303    return RotateRight(bits, imm_r, 64);
304  } else {
305    DCHECK_NE((imm_s >> 1), 0x1fU);
306    for (unsigned width = 0x20; width >= 0x2; width >>= 1) {
307      if ((imm_s & width) == 0) {
308        unsigned mask = (unsigned)(width - 1);
309        DCHECK_NE((imm_s & mask), mask);
310        uint64_t bits = BIT_MASK((imm_s & mask) + 1);
311        return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width);
312      }
313    }
314  }
315  return 0;
316}
317
318/**
319 * @brief Decode an 8-bit single point number encoded with EncodeImmSingle().
320 */
321static float DecodeImmSingle(uint8_t small_float) {
322  int mantissa = (small_float & 0x0f) + 0x10;
323  int sign = ((small_float & 0x80) == 0) ? 1 : -1;
324  float signed_mantissa = static_cast<float>(sign*mantissa);
325  int exponent = (((small_float >> 4) & 0x7) + 4) & 0x7;
326  return signed_mantissa*static_cast<float>(1 << exponent)*0.0078125f;
327}
328
329static const char* cc_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
330                                 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"};
331/*
332 * Interpret a format string and build a string no longer than size
333 * See format key in assemble_arm64.cc.
334 */
335std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) {
336  std::string buf;
337  const char* fmt_end = &fmt[strlen(fmt)];
338  char tbuf[256];
339  const char* name;
340  char nc;
341  while (fmt < fmt_end) {
342    int operand;
343    if (*fmt == '!') {
344      fmt++;
345      DCHECK_LT(fmt, fmt_end);
346      nc = *fmt++;
347      if (nc == '!') {
348        strcpy(tbuf, "!");
349      } else {
350         DCHECK_LT(fmt, fmt_end);
351         DCHECK_LT(static_cast<unsigned>(nc-'0'), 4U);
352         operand = lir->operands[nc-'0'];
353         switch (*fmt++) {
354           case 'e':  {
355               // Omit ", uxtw #0" in strings like "add w0, w1, w3, uxtw #0" and
356               // ", uxtx #0" in strings like "add x0, x1, x3, uxtx #0"
357               int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) :
358                                EncodeExtend(kA64Uxtw, 0));
359               if (LIKELY(operand == omittable)) {
360                 strcpy(tbuf, "");
361               } else {
362                 DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf));
363               }
364             }
365             break;
366           case 'o':
367             // Omit ", lsl #0"
368             if (LIKELY(operand == EncodeShift(kA64Lsl, 0))) {
369               strcpy(tbuf, "");
370             } else {
371               DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf));
372             }
373             break;
374           case 'B':
375             switch (operand) {
376               case kSY:
377                 name = "sy";
378                 break;
379               case kST:
380                 name = "st";
381                 break;
382               case kISH:
383                 name = "ish";
384                 break;
385               case kISHST:
386                 name = "ishst";
387                 break;
388               case kNSH:
389                 name = "nsh";
390                 break;
391               case kNSHST:
392                 name = "shst";
393                 break;
394               default:
395                 name = "DecodeError2";
396                 break;
397             }
398             strcpy(tbuf, name);
399             break;
400           case 's':
401             snprintf(tbuf, arraysize(tbuf), "s%d", operand & RegStorage::kRegNumMask);
402             break;
403           case 'S':
404             snprintf(tbuf, arraysize(tbuf), "d%d", operand & RegStorage::kRegNumMask);
405             break;
406           case 'f':
407             snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_FWIDE(lir->opcode)) ? 'd' : 's',
408                      operand & RegStorage::kRegNumMask);
409             break;
410           case 'l': {
411               bool is_wide = IS_WIDE(lir->opcode);
412               uint64_t imm = DecodeLogicalImmediate(is_wide, operand);
413               snprintf(tbuf, arraysize(tbuf), "%" PRId64 " (%#" PRIx64 ")", imm, imm);
414             }
415             break;
416           case 'I':
417             snprintf(tbuf, arraysize(tbuf), "%f", DecodeImmSingle(operand));
418             break;
419           case 'M':
420             if (LIKELY(operand == 0))
421               strcpy(tbuf, "");
422             else
423               snprintf(tbuf, arraysize(tbuf), ", lsl #%d", 16*operand);
424             break;
425           case 'd':
426             snprintf(tbuf, arraysize(tbuf), "%d", operand);
427             break;
428           case 'w':
429             if (LIKELY(operand != rwzr))
430               snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask);
431             else
432               strcpy(tbuf, "wzr");
433             break;
434           case 'W':
435             if (LIKELY(operand != rwsp))
436               snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask);
437             else
438               strcpy(tbuf, "wsp");
439             break;
440           case 'x':
441             if (LIKELY(operand != rxzr))
442               snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask);
443             else
444               strcpy(tbuf, "xzr");
445             break;
446           case 'X':
447             if (LIKELY(operand != rsp))
448               snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask);
449             else
450               strcpy(tbuf, "sp");
451             break;
452           case 'D':
453             snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4));
454             break;
455           case 'E':
456             snprintf(tbuf, arraysize(tbuf), "%d", operand*4);
457             break;
458           case 'F':
459             snprintf(tbuf, arraysize(tbuf), "%d", operand*2);
460             break;
461           case 'G':
462             if (LIKELY(operand == 0))
463               strcpy(tbuf, "");
464             else
465               strcpy(tbuf, (IS_WIDE(lir->opcode)) ? ", lsl #3" : ", lsl #2");
466             break;
467           case 'c':
468             strcpy(tbuf, cc_names[operand]);
469             break;
470           case 't':
471             snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)",
472                 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + (operand << 2),
473                 lir->target);
474             break;
475           case 'r': {
476               bool is_wide = IS_WIDE(lir->opcode);
477               if (LIKELY(operand != rwzr && operand != rxzr)) {
478                 snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w',
479                          operand & RegStorage::kRegNumMask);
480               } else {
481                 strcpy(tbuf, (is_wide) ? "xzr" : "wzr");
482               }
483             }
484             break;
485           case 'R': {
486               bool is_wide = IS_WIDE(lir->opcode);
487               if (LIKELY(operand != rwsp && operand != rsp)) {
488                 snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w',
489                          operand & RegStorage::kRegNumMask);
490               } else {
491                 strcpy(tbuf, (is_wide) ? "sp" : "wsp");
492               }
493             }
494             break;
495           case 'p':
496             snprintf(tbuf, arraysize(tbuf), ".+%d (addr %#" PRIxPTR ")", 4*operand,
497                      reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4*operand);
498             break;
499           case 'T':
500             if (LIKELY(operand == 0))
501               strcpy(tbuf, "");
502             else if (operand == 1)
503               strcpy(tbuf, ", lsl #12");
504             else
505               strcpy(tbuf, ", DecodeError3");
506             break;
507           case 'h':
508             snprintf(tbuf, arraysize(tbuf), "%d", operand);
509             break;
510           default:
511             strcpy(tbuf, "DecodeError1");
512             break;
513        }
514        buf += tbuf;
515      }
516    } else {
517       buf += *fmt++;
518    }
519  }
520  return buf;
521}
522
523void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) {
524  char buf[256];
525  buf[0] = 0;
526
527  if (mask.Equals(kEncodeAll)) {
528    strcpy(buf, "all");
529  } else {
530    char num[8];
531    int i;
532
533    for (i = 0; i < kArm64RegEnd; i++) {
534      if (mask.HasBit(i)) {
535        snprintf(num, arraysize(num), "%d ", i);
536        strcat(buf, num);
537      }
538    }
539
540    if (mask.HasBit(ResourceMask::kCCode)) {
541      strcat(buf, "cc ");
542    }
543    if (mask.HasBit(ResourceMask::kFPStatus)) {
544      strcat(buf, "fpcc ");
545    }
546
547    /* Memory bits */
548    if (arm_lir && (mask.HasBit(ResourceMask::kDalvikReg))) {
549      snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s",
550               DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info),
551               DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : "");
552    }
553    if (mask.HasBit(ResourceMask::kLiteral)) {
554      strcat(buf, "lit ");
555    }
556
557    if (mask.HasBit(ResourceMask::kHeapRef)) {
558      strcat(buf, "heap ");
559    }
560    if (mask.HasBit(ResourceMask::kMustNotAlias)) {
561      strcat(buf, "noalias ");
562    }
563  }
564  if (buf[0]) {
565    LOG(INFO) << prefix << ": " << buf;
566  }
567}
568
569bool Arm64Mir2Lir::IsUnconditionalBranch(LIR* lir) {
570  return (lir->opcode == kA64B1t);
571}
572
573RegisterClass Arm64Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) {
574  if (UNLIKELY(is_volatile)) {
575    // On arm64, fp register load/store is atomic only for single bytes.
576    if (size != kSignedByte && size != kUnsignedByte) {
577      return (size == kReference) ? kRefReg : kCoreReg;
578    }
579  }
580  return RegClassBySize(size);
581}
582
583Arm64Mir2Lir::Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena)
584    : Mir2Lir(cu, mir_graph, arena) {
585  // Sanity check - make sure encoding map lines up.
586  for (int i = 0; i < kA64Last; i++) {
587    if (UNWIDE(Arm64Mir2Lir::EncodingMap[i].opcode) != i) {
588      LOG(FATAL) << "Encoding order for " << Arm64Mir2Lir::EncodingMap[i].name
589                 << " is wrong: expecting " << i << ", seeing "
590                 << static_cast<int>(Arm64Mir2Lir::EncodingMap[i].opcode);
591    }
592  }
593}
594
595Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
596                            ArenaAllocator* const arena) {
597  return new Arm64Mir2Lir(cu, mir_graph, arena);
598}
599
600void Arm64Mir2Lir::CompilerInitializeRegAlloc() {
601  reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs, core64_regs, sp_regs, dp_regs,
602                                        reserved_regs, reserved64_regs, core_temps, core64_temps,
603                                        sp_temps, dp_temps);
604
605  // Target-specific adjustments.
606  // Alias single precision float registers to corresponding double registers.
607  GrowableArray<RegisterInfo*>::Iterator fp_it(&reg_pool_->sp_regs_);
608  for (RegisterInfo* info = fp_it.Next(); info != nullptr; info = fp_it.Next()) {
609    int fp_reg_num = info->GetReg().GetRegNum();
610    RegStorage dp_reg = RegStorage::FloatSolo64(fp_reg_num);
611    RegisterInfo* dp_reg_info = GetRegInfo(dp_reg);
612    // Double precision register's master storage should refer to itself.
613    DCHECK_EQ(dp_reg_info, dp_reg_info->Master());
614    // Redirect single precision's master storage to master.
615    info->SetMaster(dp_reg_info);
616    // Singles should show a single 32-bit mask bit, at first referring to the low half.
617    DCHECK_EQ(info->StorageMask(), 0x1U);
618  }
619
620  // Alias 32bit W registers to corresponding 64bit X registers.
621  GrowableArray<RegisterInfo*>::Iterator w_it(&reg_pool_->core_regs_);
622  for (RegisterInfo* info = w_it.Next(); info != nullptr; info = w_it.Next()) {
623    int x_reg_num = info->GetReg().GetRegNum();
624    RegStorage x_reg = RegStorage::Solo64(x_reg_num);
625    RegisterInfo* x_reg_info = GetRegInfo(x_reg);
626    // 64bit X register's master storage should refer to itself.
627    DCHECK_EQ(x_reg_info, x_reg_info->Master());
628    // Redirect 32bit W master storage to 64bit X.
629    info->SetMaster(x_reg_info);
630    // 32bit W should show a single 32-bit mask bit, at first referring to the low half.
631    DCHECK_EQ(info->StorageMask(), 0x1U);
632  }
633
634  // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods.
635  // TODO: adjust when we roll to hard float calling convention.
636  reg_pool_->next_core_reg_ = 2;
637  reg_pool_->next_sp_reg_ = 0;
638  reg_pool_->next_dp_reg_ = 0;
639}
640
641/*
642 * TUNING: is true leaf?  Can't just use METHOD_IS_LEAF to determine as some
643 * instructions might call out to C/assembly helper functions.  Until
644 * machinery is in place, always spill lr.
645 */
646
647void Arm64Mir2Lir::AdjustSpillMask() {
648  core_spill_mask_ |= (1 << rs_xLR.GetRegNum());
649  num_core_spills_++;
650}
651
652/* Clobber all regs that might be used by an external C call */
653void Arm64Mir2Lir::ClobberCallerSave() {
654  Clobber(rs_x0);
655  Clobber(rs_x1);
656  Clobber(rs_x2);
657  Clobber(rs_x3);
658  Clobber(rs_x4);
659  Clobber(rs_x5);
660  Clobber(rs_x6);
661  Clobber(rs_x7);
662  Clobber(rs_x8);
663  Clobber(rs_x9);
664  Clobber(rs_x10);
665  Clobber(rs_x11);
666  Clobber(rs_x12);
667  Clobber(rs_x13);
668  Clobber(rs_x14);
669  Clobber(rs_x15);
670  Clobber(rs_x16);
671  Clobber(rs_x17);
672  Clobber(rs_x30);
673
674  Clobber(rs_f0);
675  Clobber(rs_f1);
676  Clobber(rs_f2);
677  Clobber(rs_f3);
678  Clobber(rs_f4);
679  Clobber(rs_f5);
680  Clobber(rs_f6);
681  Clobber(rs_f7);
682  Clobber(rs_f16);
683  Clobber(rs_f17);
684  Clobber(rs_f18);
685  Clobber(rs_f19);
686  Clobber(rs_f20);
687  Clobber(rs_f21);
688  Clobber(rs_f22);
689  Clobber(rs_f23);
690  Clobber(rs_f24);
691  Clobber(rs_f25);
692  Clobber(rs_f26);
693  Clobber(rs_f27);
694  Clobber(rs_f28);
695  Clobber(rs_f29);
696  Clobber(rs_f30);
697  Clobber(rs_f31);
698}
699
700RegLocation Arm64Mir2Lir::GetReturnWideAlt() {
701  RegLocation res = LocCReturnWide();
702  res.reg.SetReg(rx2);
703  res.reg.SetHighReg(rx3);
704  Clobber(rs_x2);
705  Clobber(rs_x3);
706  MarkInUse(rs_x2);
707  MarkInUse(rs_x3);
708  MarkWide(res.reg);
709  return res;
710}
711
712RegLocation Arm64Mir2Lir::GetReturnAlt() {
713  RegLocation res = LocCReturn();
714  res.reg.SetReg(rx1);
715  Clobber(rs_x1);
716  MarkInUse(rs_x1);
717  return res;
718}
719
720/* To be used when explicitly managing register use */
721void Arm64Mir2Lir::LockCallTemps() {
722  // TODO: needs cleanup.
723  LockTemp(rs_x0);
724  LockTemp(rs_x1);
725  LockTemp(rs_x2);
726  LockTemp(rs_x3);
727  LockTemp(rs_x4);
728  LockTemp(rs_x5);
729  LockTemp(rs_x6);
730  LockTemp(rs_x7);
731  LockTemp(rs_f0);
732  LockTemp(rs_f1);
733  LockTemp(rs_f2);
734  LockTemp(rs_f3);
735  LockTemp(rs_f4);
736  LockTemp(rs_f5);
737  LockTemp(rs_f6);
738  LockTemp(rs_f7);
739}
740
741/* To be used when explicitly managing register use */
742void Arm64Mir2Lir::FreeCallTemps() {
743  // TODO: needs cleanup.
744  FreeTemp(rs_x0);
745  FreeTemp(rs_x1);
746  FreeTemp(rs_x2);
747  FreeTemp(rs_x3);
748  FreeTemp(rs_x4);
749  FreeTemp(rs_x5);
750  FreeTemp(rs_x6);
751  FreeTemp(rs_x7);
752  FreeTemp(rs_f0);
753  FreeTemp(rs_f1);
754  FreeTemp(rs_f2);
755  FreeTemp(rs_f3);
756  FreeTemp(rs_f4);
757  FreeTemp(rs_f5);
758  FreeTemp(rs_f6);
759  FreeTemp(rs_f7);
760}
761
762RegStorage Arm64Mir2Lir::LoadHelper(QuickEntrypointEnum trampoline) {
763  // TODO(Arm64): use LoadWordDisp instead.
764  //   e.g. LoadWordDisp(rs_rA64_SELF, offset.Int32Value(), rs_rA64_LR);
765  LoadBaseDisp(rs_xSELF, GetThreadOffset<8>(trampoline).Int32Value(), rs_xLR, k64, kNotVolatile);
766  return rs_xLR;
767}
768
769LIR* Arm64Mir2Lir::CheckSuspendUsingLoad() {
770  RegStorage tmp = rs_x0;
771  LoadWordDisp(rs_xSELF, Thread::ThreadSuspendTriggerOffset<8>().Int32Value(), tmp);
772  LIR* load2 = LoadWordDisp(tmp, 0, tmp);
773  return load2;
774}
775
776uint64_t Arm64Mir2Lir::GetTargetInstFlags(int opcode) {
777  DCHECK(!IsPseudoLirOp(opcode));
778  return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].flags;
779}
780
781const char* Arm64Mir2Lir::GetTargetInstName(int opcode) {
782  DCHECK(!IsPseudoLirOp(opcode));
783  return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].name;
784}
785
786const char* Arm64Mir2Lir::GetTargetInstFmt(int opcode) {
787  DCHECK(!IsPseudoLirOp(opcode));
788  return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].fmt;
789}
790
791RegStorage Arm64Mir2Lir::InToRegStorageArm64Mapper::GetNextReg(bool is_double_or_float,
792                                                               bool is_wide,
793                                                               bool is_ref) {
794  const RegStorage coreArgMappingToPhysicalReg[] =
795      {rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7};
796  const int coreArgMappingToPhysicalRegSize =
797      sizeof(coreArgMappingToPhysicalReg) / sizeof(RegStorage);
798  const RegStorage fpArgMappingToPhysicalReg[] =
799      {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7};
800  const int fpArgMappingToPhysicalRegSize =
801      sizeof(fpArgMappingToPhysicalReg) / sizeof(RegStorage);
802
803  RegStorage result = RegStorage::InvalidReg();
804  if (is_double_or_float) {
805    if (cur_fp_reg_ < fpArgMappingToPhysicalRegSize) {
806      DCHECK(!is_ref);
807      result = fpArgMappingToPhysicalReg[cur_fp_reg_++];
808      if (result.Valid()) {
809        // TODO: switching between widths remains a bit ugly.  Better way?
810        int res_reg = result.GetReg();
811        result = is_wide ? RegStorage::FloatSolo64(res_reg) : RegStorage::FloatSolo32(res_reg);
812      }
813    }
814  } else {
815    if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) {
816      result = coreArgMappingToPhysicalReg[cur_core_reg_++];
817      if (result.Valid()) {
818        // TODO: switching between widths remains a bit ugly.  Better way?
819        int res_reg = result.GetReg();
820        DCHECK(!(is_wide && is_ref));
821        result = (is_wide || is_ref) ? RegStorage::Solo64(res_reg) : RegStorage::Solo32(res_reg);
822      }
823    }
824  }
825  return result;
826}
827
828RegStorage Arm64Mir2Lir::InToRegStorageMapping::Get(int in_position) {
829  DCHECK(IsInitialized());
830  auto res = mapping_.find(in_position);
831  return res != mapping_.end() ? res->second : RegStorage::InvalidReg();
832}
833
834void Arm64Mir2Lir::InToRegStorageMapping::Initialize(RegLocation* arg_locs, int count,
835                                                     InToRegStorageMapper* mapper) {
836  DCHECK(mapper != nullptr);
837  max_mapped_in_ = -1;
838  is_there_stack_mapped_ = false;
839  for (int in_position = 0; in_position < count; in_position++) {
840     RegStorage reg = mapper->GetNextReg(arg_locs[in_position].fp,
841                                         arg_locs[in_position].wide,
842                                         arg_locs[in_position].ref);
843     if (reg.Valid()) {
844       mapping_[in_position] = reg;
845       if (arg_locs[in_position].wide) {
846         // We covered 2 args, so skip the next one
847         in_position++;
848       }
849       max_mapped_in_ = std::max(max_mapped_in_, in_position);
850     } else {
851       is_there_stack_mapped_ = true;
852     }
853  }
854  initialized_ = true;
855}
856
857
858// Deprecate.  Use the new mechanism.
859// TODO(Arm64): reuse info in QuickArgumentVisitor?
860static RegStorage GetArgPhysicalReg(RegLocation* loc, int* num_gpr_used, int* num_fpr_used,
861                                    OpSize* op_size) {
862  if (loc->fp) {
863    int n = *num_fpr_used;
864    if (n < 8) {
865      *num_fpr_used = n + 1;
866      RegStorage::RegStorageKind reg_kind;
867      if (loc->wide) {
868        *op_size = kDouble;
869        reg_kind = RegStorage::k64BitSolo;
870      } else {
871        *op_size = kSingle;
872        reg_kind = RegStorage::k32BitSolo;
873      }
874      return RegStorage(RegStorage::kValid | reg_kind | RegStorage::kFloatingPoint | n);
875    }
876  } else {
877    int n = *num_gpr_used;
878    if (n < 8) {
879      *num_gpr_used = n + 1;
880      if (loc->wide || loc->ref) {
881        *op_size = k64;
882        return RegStorage::Solo64(n);
883      } else {
884        *op_size = k32;
885        return RegStorage::Solo32(n);
886      }
887    }
888  }
889  *op_size = kWord;
890  return RegStorage::InvalidReg();
891}
892
893RegStorage Arm64Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) {
894  if (!in_to_reg_storage_mapping_.IsInitialized()) {
895    int start_vreg = cu_->num_dalvik_registers - cu_->num_ins;
896    RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg];
897
898    InToRegStorageArm64Mapper mapper;
899    in_to_reg_storage_mapping_.Initialize(arg_locs, cu_->num_ins, &mapper);
900  }
901  return in_to_reg_storage_mapping_.Get(arg_num);
902}
903
904
905/*
906 * If there are any ins passed in registers that have not been promoted
907 * to a callee-save register, flush them to the frame.  Perform initial
908 * assignment of promoted arguments.
909 *
910 * ArgLocs is an array of location records describing the incoming arguments
911 * with one location record per word of argument.
912 */
913void Arm64Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) {
914  int num_gpr_used = 1;
915  int num_fpr_used = 0;
916
917  /*
918   * Dummy up a RegLocation for the incoming StackReference<mirror::ArtMethod>
919   * It will attempt to keep kArg0 live (or copy it to home location
920   * if promoted).
921   */
922  RegLocation rl_src = rl_method;
923  rl_src.location = kLocPhysReg;
924  rl_src.reg = TargetReg(kArg0, kRef);
925  rl_src.home = false;
926  MarkLive(rl_src);
927  StoreValue(rl_method, rl_src);
928  // If Method* has been promoted, explicitly flush
929  if (rl_method.location == kLocPhysReg) {
930    StoreRefDisp(TargetPtrReg(kSp), 0, rl_src.reg, kNotVolatile);
931  }
932
933  if (cu_->num_ins == 0) {
934    return;
935  }
936
937  // Handle dalvik registers.
938  ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
939  int start_vreg = cu_->num_dalvik_registers - cu_->num_ins;
940  for (int i = 0; i < cu_->num_ins; i++) {
941    RegLocation* t_loc = &ArgLocs[i];
942    OpSize op_size;
943    RegStorage reg = GetArgPhysicalReg(t_loc, &num_gpr_used, &num_fpr_used, &op_size);
944
945    if (reg.Valid()) {
946      // If arriving in register.
947
948      // We have already updated the arg location with promoted info
949      // so we can be based on it.
950      if (t_loc->location == kLocPhysReg) {
951        // Just copy it.
952        OpRegCopy(t_loc->reg, reg);
953      } else {
954        // Needs flush.
955        if (t_loc->ref) {
956          StoreRefDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), reg, kNotVolatile);
957        } else {
958          StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32,
959              kNotVolatile);
960        }
961      }
962    } else {
963      // If arriving in frame & promoted.
964      if (t_loc->location == kLocPhysReg) {
965        if (t_loc->ref) {
966          LoadRefDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), t_loc->reg, kNotVolatile);
967        } else {
968          LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), t_loc->reg,
969                       t_loc->wide ? k64 : k32, kNotVolatile);
970        }
971      }
972    }
973    if (t_loc->wide) {
974      // Increment i to skip the next one.
975      i++;
976    }
977    //      if ((v_map->core_location == kLocPhysReg) && !t_loc->fp) {
978    //        OpRegCopy(RegStorage::Solo32(v_map->core_reg), reg);
979    //      } else if ((v_map->fp_location == kLocPhysReg) && t_loc->fp) {
980    //        OpRegCopy(RegStorage::Solo32(v_map->fp_reg), reg);
981    //      } else {
982    //        StoreBaseDisp(TargetReg(kSp), SRegOffset(start_vreg + i), reg, op_size, kNotVolatile);
983    //        if (reg.Is64Bit()) {
984    //          if (SRegOffset(start_vreg + i) + 4 != SRegOffset(start_vreg + i + 1)) {
985    //            LOG(FATAL) << "64 bit value stored in non-consecutive 4 bytes slots";
986    //          }
987    //          i += 1;
988    //        }
989    //      }
990    //    } else {
991    //      // If arriving in frame & promoted
992    //      if (v_map->core_location == kLocPhysReg) {
993    //        LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i),
994    //                     RegStorage::Solo32(v_map->core_reg));
995    //      }
996    //      if (v_map->fp_location == kLocPhysReg) {
997    //        LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), RegStorage::Solo32(v_map->fp_reg));
998    //      }
999  }
1000}
1001
1002/*
1003 * Load up to 5 arguments, the first three of which will be in
1004 * kArg1 .. kArg3.  On entry kArg0 contains the current method pointer,
1005 * and as part of the load sequence, it must be replaced with
1006 * the target method pointer.
1007 */
1008int Arm64Mir2Lir::GenDalvikArgsNoRange(CallInfo* info,
1009                                       int call_state, LIR** pcrLabel, NextCallInsn next_call_insn,
1010                                       const MethodReference& target_method,
1011                                       uint32_t vtable_idx, uintptr_t direct_code,
1012                                       uintptr_t direct_method, InvokeType type, bool skip_this) {
1013  return GenDalvikArgsRange(info,
1014                       call_state, pcrLabel, next_call_insn,
1015                       target_method,
1016                       vtable_idx, direct_code,
1017                       direct_method, type, skip_this);
1018}
1019
1020/*
1021 * May have 0+ arguments (also used for jumbo).  Note that
1022 * source virtual registers may be in physical registers, so may
1023 * need to be flushed to home location before copying.  This
1024 * applies to arg3 and above (see below).
1025 *
1026 * FIXME: update comments.
1027 *
1028 * Two general strategies:
1029 *    If < 20 arguments
1030 *       Pass args 3-18 using vldm/vstm block copy
1031 *       Pass arg0, arg1 & arg2 in kArg1-kArg3
1032 *    If 20+ arguments
1033 *       Pass args arg19+ using memcpy block copy
1034 *       Pass arg0, arg1 & arg2 in kArg1-kArg3
1035 *
1036 */
1037int Arm64Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state,
1038                                     LIR** pcrLabel, NextCallInsn next_call_insn,
1039                                     const MethodReference& target_method,
1040                                     uint32_t vtable_idx, uintptr_t direct_code,
1041                                     uintptr_t direct_method, InvokeType type, bool skip_this) {
1042  /* If no arguments, just return */
1043  if (info->num_arg_words == 0)
1044    return call_state;
1045
1046  const int start_index = skip_this ? 1 : 0;
1047
1048  InToRegStorageArm64Mapper mapper;
1049  InToRegStorageMapping in_to_reg_storage_mapping;
1050  in_to_reg_storage_mapping.Initialize(info->args, info->num_arg_words, &mapper);
1051  const int last_mapped_in = in_to_reg_storage_mapping.GetMaxMappedIn();
1052  int regs_left_to_pass_via_stack = info->num_arg_words - (last_mapped_in + 1);
1053
1054  // First of all, check whether it makes sense to use bulk copying.
1055  // Bulk copying is done only for the range case.
1056  // TODO: make a constant instead of 2
1057  if (info->is_range && regs_left_to_pass_via_stack >= 2) {
1058    // Scan the rest of the args - if in phys_reg flush to memory
1059    for (int next_arg = last_mapped_in + 1; next_arg < info->num_arg_words;) {
1060      RegLocation loc = info->args[next_arg];
1061      if (loc.wide) {
1062        loc = UpdateLocWide(loc);
1063        if (loc.location == kLocPhysReg) {
1064          ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
1065          StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile);
1066        }
1067        next_arg += 2;
1068      } else {
1069        loc = UpdateLoc(loc);
1070        if (loc.location == kLocPhysReg) {
1071          ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
1072          if (loc.ref) {
1073            StoreRefDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, kNotVolatile);
1074          } else {
1075            StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k32,
1076                          kNotVolatile);
1077          }
1078        }
1079        next_arg++;
1080      }
1081    }
1082
1083    // Logic below assumes that Method pointer is at offset zero from SP.
1084    DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0);
1085
1086    // The rest can be copied together
1087    int start_offset = SRegOffset(info->args[last_mapped_in + 1].s_reg_low);
1088    int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + 1,
1089                                                   cu_->instruction_set);
1090
1091    int current_src_offset = start_offset;
1092    int current_dest_offset = outs_offset;
1093
1094    // Only davik regs are accessed in this loop; no next_call_insn() calls.
1095    ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
1096    while (regs_left_to_pass_via_stack > 0) {
1097      /*
1098       * TODO: Improve by adding block copy for large number of arguments.  This
1099       * should be done, if possible, as a target-depending helper.  For now, just
1100       * copy a Dalvik vreg at a time.
1101       */
1102      // Moving 32-bits via general purpose register.
1103      size_t bytes_to_move = sizeof(uint32_t);
1104
1105      // Instead of allocating a new temp, simply reuse one of the registers being used
1106      // for argument passing.
1107      RegStorage temp = TargetReg(kArg3, kNotWide);
1108
1109      // Now load the argument VR and store to the outs.
1110      Load32Disp(TargetPtrReg(kSp), current_src_offset, temp);
1111      Store32Disp(TargetPtrReg(kSp), current_dest_offset, temp);
1112
1113      current_src_offset += bytes_to_move;
1114      current_dest_offset += bytes_to_move;
1115      regs_left_to_pass_via_stack -= (bytes_to_move >> 2);
1116    }
1117    DCHECK_EQ(regs_left_to_pass_via_stack, 0);
1118  }
1119
1120  // Now handle rest not registers if they are
1121  if (in_to_reg_storage_mapping.IsThereStackMapped()) {
1122    RegStorage regWide = TargetReg(kArg3, kWide);
1123    for (int i = start_index; i <= last_mapped_in + regs_left_to_pass_via_stack; i++) {
1124      RegLocation rl_arg = info->args[i];
1125      rl_arg = UpdateRawLoc(rl_arg);
1126      RegStorage reg = in_to_reg_storage_mapping.Get(i);
1127      if (!reg.Valid()) {
1128        int out_offset = StackVisitor::GetOutVROffset(i, cu_->instruction_set);
1129
1130        {
1131          ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
1132          if (rl_arg.wide) {
1133            if (rl_arg.location == kLocPhysReg) {
1134              StoreBaseDisp(TargetPtrReg(kSp), out_offset, rl_arg.reg, k64, kNotVolatile);
1135            } else {
1136              LoadValueDirectWideFixed(rl_arg, regWide);
1137              StoreBaseDisp(TargetPtrReg(kSp), out_offset, regWide, k64, kNotVolatile);
1138            }
1139          } else {
1140            if (rl_arg.location == kLocPhysReg) {
1141              if (rl_arg.ref) {
1142                StoreRefDisp(TargetPtrReg(kSp), out_offset, rl_arg.reg, kNotVolatile);
1143              } else {
1144                StoreBaseDisp(TargetPtrReg(kSp), out_offset, rl_arg.reg, k32, kNotVolatile);
1145              }
1146            } else {
1147              if (rl_arg.ref) {
1148                RegStorage regSingle = TargetReg(kArg2, kRef);
1149                LoadValueDirectFixed(rl_arg, regSingle);
1150                StoreRefDisp(TargetPtrReg(kSp), out_offset, regSingle, kNotVolatile);
1151              } else {
1152                RegStorage regSingle = TargetReg(kArg2, kNotWide);
1153                LoadValueDirectFixed(rl_arg, regSingle);
1154                StoreBaseDisp(TargetPtrReg(kSp), out_offset, regSingle, k32, kNotVolatile);
1155              }
1156            }
1157          }
1158        }
1159        call_state = next_call_insn(cu_, info, call_state, target_method,
1160                                    vtable_idx, direct_code, direct_method, type);
1161      }
1162      if (rl_arg.wide) {
1163        i++;
1164      }
1165    }
1166  }
1167
1168  // Finish with mapped registers
1169  for (int i = start_index; i <= last_mapped_in; i++) {
1170    RegLocation rl_arg = info->args[i];
1171    rl_arg = UpdateRawLoc(rl_arg);
1172    RegStorage reg = in_to_reg_storage_mapping.Get(i);
1173    if (reg.Valid()) {
1174      if (rl_arg.wide) {
1175        LoadValueDirectWideFixed(rl_arg, reg);
1176      } else {
1177        LoadValueDirectFixed(rl_arg, reg);
1178      }
1179      call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
1180                                  direct_code, direct_method, type);
1181    }
1182    if (rl_arg.wide) {
1183      i++;
1184    }
1185  }
1186
1187  call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
1188                           direct_code, direct_method, type);
1189  if (pcrLabel) {
1190    if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) {
1191      *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags);
1192    } else {
1193      *pcrLabel = nullptr;
1194      // In lieu of generating a check for kArg1 being null, we need to
1195      // perform a load when doing implicit checks.
1196      RegStorage tmp = AllocTemp();
1197      Load32Disp(TargetReg(kArg1, kRef), 0, tmp);
1198      MarkPossibleNullPointerException(info->opt_flags);
1199      FreeTemp(tmp);
1200    }
1201  }
1202  return call_state;
1203}
1204
1205}  // namespace art
1206