3d21bdf8894e780d349c481e5c9e29fe1556051c |
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22-Apr-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move mirror::ArtMethod to native Optimizing + quick tests are passing, devices boot. TODO: Test and fix bugs in mips64. Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS. Some of the savings are from removal of virtual methods and direct methods object arrays. Bug: 19264997 (cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33) Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d Fix some ArtMethod related bugs Added root visiting for runtime methods, not currently required since the GcRoots in these methods are null. Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes --trace run-tests 005, 044. Fixed optimizing compiler bug where we used a normal stack location instead of double on ARM64, this fixes the debuggable tests. TODO: Fix JDWP tests. Bug: 19264997 Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3 ART: Fix casts for 64-bit pointers on 32-bit compiler. Bug: 19264997 Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457 Fix JDWP tests after ArtMethod change Fixes Throwable::GetStackDepth for exception event detection after internal stack trace representation change. Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of proxy method. Bug: 19264997 Change-Id: I363e293796848c3ec491c963813f62d868da44d2 Fix accidental IMT and root marking regression Was always using the conflict trampoline. Also included fix for regression in GC time caused by extra roots. Most of the regression was IMT. Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to detached thread. EvaluateAndApplyChanges: From ~2500 -> ~1980 GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots Bug: 19264997 Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0 Fix bogus image test assert Previously we were comparing the size of the non moving space to size of the image file. Now we properly compare the size of the image space against the size of the image file. Bug: 19264997 Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a [MIPS64] Fix art_quick_invoke_stub argument offsets. ArtMethod reference's size got bigger, so we need to move other args and leave enough space for ArtMethod* and 'this' pointer. This fixes mips64 boot. Bug: 19264997 Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
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69a503050fb8a7b3a79b2cd2cdc2d8fbc594575d |
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14-Apr-2015 |
Zheng Xu <zheng.xu@arm.com> |
ARM64: Remove suspend register. It also clean up build/remove frame used by JNI compiler and generates stp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and optimizing compiler. Change-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d
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20f85597828194c12be10d3a927999def066555e |
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19-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Fixed layout for dex caches in boot image. Define a fixed layout for dex cache arrays (type, method, string and field arrays) for dex caches in the boot image. This gives those arrays fixed offsets from the boot image code and allows PC-relative addressing of their elements. Use the PC-relative load on arm64 for relevant instructions, i.e. invoke-static, invoke-direct, const-string, const-class, check-cast and instance-of. This reduces the arm64 boot.oat on Nexus 9 by 1.1MiB. This CL provides the infrastructure and shows on the arm64 the gains that we can achieve by having fixed dex cache arrays' layout. To fully use this for the boot images, we need to implement the PC-relative addressing for other architectures. To achieve similar gains for apps, we need to move the dex cache arrays to a .bss section of the oat file. These changes will be implemented in subsequent CLs. (Also remove some compiler_driver.h dependencies to reduce incremental build times.) Change-Id: Ib1859fa4452d01d983fd92ae22b611f45a85d69b
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f6737f7ed741b15cfd60c2530dab69f897540735 |
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23-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Clean up Mir2Lir codegen. Clean up WrapPointer()/UnwrapPointer() and OpPcRelLoad(). Change-Id: I1a91f01e1e779599c77f3f6efcac2a6ad34629cf
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a34e760fa5cc3102ce1998f10816d380c37f43aa |
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02-Feb-2015 |
Zheng Xu <zheng.xu@arm.com> |
ARM/ARM64: Dump thread offset. Dump thread offset in compiler verbose log for arm32/arm64 and oatdump for arm64. Before patch : 0x4e: ldr lr, [rSELF, #604] After patch : 0x4e: ldr lr, [rSELF, #604] ; pTestSuspend Change-Id: I514e69dc44b1cf4c8a8fa085b31f93cf6a1b7c91
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0b9203e7996ee1856f620f95d95d8a273c43a3df |
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23-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Some Quick cleanup Make several fields const in CompilationUnit. May benefit some Mir2Lir code that repeats tests, and in general immutability is good. Remove compiler_internals.h and refactor some other headers to reduce overly broad imports (and thus forced recompiles on changes). Change-Id: I898405907c68923581373b5981d8a85d2e5d185a
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bfe400bb1a28cde991cdb3e39bc27bae6b04b8c2 |
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19-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Fix running out of temps when storing invoke-interface result. On ARM, after emitting invoke-interface we didn't have any free temps to use for storing the result, so we would crash if the result was an unpromoted dalvik register with stack location too far from SP. Bug: 18769895 (cherry picked from commit d6bd06c713e8ec69de96510ef57bdf7adb4781ed) Change-Id: Id88f6f3788eaf6ecbc7bd68880b445423f6e4f94
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d6bd06c713e8ec69de96510ef57bdf7adb4781ed |
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19-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Fix running out of temps when storing invoke-interface result. On ARM, after emitting invoke-interface we didn't have any free temps to use for storing the result, so we would crash if the result was an unpromoted dalvik register with stack location too far from SP. Bug: 18769895 Change-Id: Ie6c131d68f1853a8317b305a22eab22faea80e90
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a262f7707330dccfb50af6345813083182b61043 |
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25-Nov-2014 |
Ningsheng Jian <ningsheng.jian@arm.com> |
ARM: Combine multiply accumulate operations. Try to combine integer multiply and add(sub) into a MAC operation. For AArch64, also try to combine long type multiply and add(sub). Change-Id: Ic85812e941eb5a66abc355cab81a4dd16de1b66e
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717a3e447c6f7a922cf9c3efe522747a187a045d |
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13-Nov-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Re-factor Quick ABI support Now every architecture must provide a mapper between VRs parameters and physical registers. Additionally as a helper function architecture can provide a bulk copy helper for GenDalvikArgs utility. All other things becomes a common code stuff: GetArgMappingToPhysicalReg, GenDalvikArgsNoRange, GenDalvikArgsRange, FlushIns. Mapper now uses shorty representation of input parameters. This is required due to location are not enough to detect the type of parameter (fp or core). For the details see https://android-review.googlesource.com/#/c/113936/. Change-Id: Ie762b921e0acaa936518ee6b63c9a9d25f83e434 Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
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6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f |
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31-Oct-2014 |
Ian Rogers <irogers@google.com> |
Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags. Fix associated errors about unused paramenters and implict sign conversions. For sign conversion this was largely in the area of enums, so add ostream operators for the effected enums and fix tools/generate-operator-out.py. Tidy arena allocation code and arena allocated data types, rather than fixing new and delete operators. Remove dead code. Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
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7c2ad5af0bdd3cc1069038f8e3422d99aeb5f44c |
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24-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
Implement method calls using relative BL on ARM64. Change-Id: I9e5d0b6c100b6cddd6bbb7ab07cff77ab104ea31
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4163c53ce38a0f1f88bf3e8d26de9914da38498b |
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15-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: address some outstanding TODOs. Fix comments in arm64_lir.h. Rename Arm* to A64* and replace FWIDE, FUNWIDE, ... with WIDE, UNWIDE, ... Change-Id: I4900902e28463ea5e00e34ea40ddfc15704c0bfa
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e39c54ea575ec710d5e84277fcdcc049f8acb3c9 |
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22-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
Deprecate GrowableArray, use ArenaVector instead. Purge GrowableArray from Quick and Portable. Remove GrowableArray<T>::Iterator. Change-Id: I92157d3a6ea5975f295662809585b2dc15caa1c6
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f77e977b04f1a73a52ea7965789cbda39d7734c4 |
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03-Sep-2014 |
buzbee <buzbee@google.com> |
Quick compiler, aarch64: Insane sanity checker Fix bit-mask generation used in the sanity checking code for long division by small constants via multiplication. The failing case was a 64-bit wide mask. The macro was using the desired width of the result as a shift count - and a left shift of a 64-bit integer by 64 bits is undefined. Note that the generated code is correct - it's just the sanity checking code that was wrong. Change-Id: Ic6654662f848d3caab2c3b1ef0d92fe2eb9673f4
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8d0d03e24325463f0060abfd05dba5598044e9b1 |
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07-Jun-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Change temporaries to positive names Changes compiler temporaries to have positive names. The numbering now puts them above the code VRs (locals + ins, in that order). The patch also introduces APIs to query the number of temporaries, locals and ins. The compiler temp infrastructure suffered from several issues which are also addressed by this patch: -There is no longer a queue of compiler temps. This would be polluted with Method* when post opts were called multiple times. -Sanity checks have been added to allow requesting of temps from BE and to prevent temps after frame is committed. -None of the structures holding temps can overflow because they are allocated to allow holding maximum temps. Thus temps can be requested by BE with no problem. -Since the queue of compiler temps is no longer maintained, it is no longer possible to refer to a temp that has invalid ssa (because it was requested before ssa was run). -The BE can now request temps after all ME allocations and it is guaranteed to actually receive them. -ME temps are now treated like normal VRs in all cases with no special handling. Only the BE temps are handled specially because there are no references to them from MIRs. -Deprecated and removed several fields in CompilationUnit that saved register information and updated callsites to call the new interface from MIRGraph. Change-Id: Ia8b1fec9384a1a83017800a59e5b0498dfb2698c Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
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53c913bb71b218714823c8c87a1f92830c336f61 |
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13-Aug-2014 |
Andreas Gampe <agampe@google.com> |
ART: Clean up compiler Clean up the compiler: less extern functions, dis-entangle compilers, hide some compiler specifics, lower global includes. Change-Id: Ibaf88d02505d86994d7845cf0075be5041cc8438
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5d7cdec7527f8043bf15e23a0041c40156727243 |
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18-Aug-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Add tbz/tbnz and tst. Since the branch offset supported by tbz/tbnz is quite small(-32k ~ +32k), it will be replaced by tst and beq/bneq in the fix-up stage if the branch offset is too large. Change-Id: I4cace06bec6425e0f2e1f5f7c471eec08d06bca6
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b551fdcda9eb128c80de37c4fb978968bec6d4b3 |
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25-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Clean up CalleeSaveMethod frame and the use of temp registers. CalleeSaveMethod frame size changes : SaveAll : 368 -> 176 RefOnly : 176 -> 96 RefsAndArgs : 304 -> 224 JNI register spill size changes : 160 -> 88 In the transition assembly, use registers following the rules: 1. x0-x7 as temp/argument registers. 2. IP0, IP1 as scratch registers. 3. After correct type of callee-save-frame has been setup, all registers are scratch-able(probably except xSELF and xSUSPEND). 4. When restore callee-save-frame, IP0 and IP1 should be untouched. 5. From C to managed code, we assume all callee save register in AAPCS will be restored by managed code except x19(SUSPEND). In quick compiler: 1. Use IP0, IP1 as scratch register. 2. Use IP1 as hidden argument register(IP0 will be scratched by trampoline.) Change-Id: I05ed9d418b01b9e87218a7608536f57e7a286e4c
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984305917bf57b3f8d92965e4715a0370cc5bcfb |
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28-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework quick entrypoint code in Mir2Lir, cleanup To reduce the complexity of calling trampolines in generic code, introduce an enumeration for entrypoints. Introduce a header that lists the entrypoint enum and exposes a templatized method that translates an enum value to the corresponding thread offset value. Call helpers are rewritten to have an enum parameter instead of the thread offset. Also rewrite LoadHelper and GenConversionCall this way. It is now LoadHelper's duty to select the right thread offset size. Introduce InvokeTrampoline virtual method to Mir2Lir. This allows to further simplify the call helpers, as well as make OpThreadMem specific to X86 only (removed from Mir2Lir). Make GenInlinedCharAt virtual, move a copy to X86 backend, and simplify both copies. Remove LoadBaseIndexedDisp and OpRegMem from Mir2Lir, as they are now specific to X86 only. Remove StoreBaseIndexedDisp from Mir2Lir, as it was only ever used in the X86 backend. Remove OpTlsCmp from Mir2Lir, as it was only ever used in the X86 backend. Remove OpLea from Mir2Lir, as it was only ever defined in the X86 backend. Remove GenImmedCheck from Mir2Lir as it was neither used nor implemented. Change-Id: If0a6182288c5d57653e3979bf547840a4c47626e
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147eb41b53729ec8d5c188d1cac90964a51afb8a |
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11-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Revert "Add implicit null and stack checks for x86"""" This reverts commit 0025a86411145eb7cd4971f9234fc21c7b4aced1. Bug: 16256184 Change-Id: Ie0760a0c293aa3b62e2885398a8c512b7a946a73 Conflicts: compiler/dex/quick/arm64/target_arm64.cc compiler/image_test.cc runtime/fault_handler.cc
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69dfe51b684dd9d510dbcb63295fe180f998efde |
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11-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Revert "Add implicit null and stack checks for x86"""" This reverts commit 0025a86411145eb7cd4971f9234fc21c7b4aced1. Bug: 16256184 Change-Id: Ie0760a0c293aa3b62e2885398a8c512b7a946a73
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d9cb8ae2ed78f957a773af61759432d7a7bf78af |
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09-Jul-2014 |
Douglas Leung <douglas@mips.com> |
Fix art test failures for Mips. This patch fixes the following art test failures for Mips: 003-omnibus-opcodes 030-bad-finalizer 041-narrowing 059-finalizer-throw Change-Id: I4e0e9ff75f949c92059dd6b8d579450dc15f4467 Signed-off-by: Douglas Leung <douglas@mips.com>
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ed7a0f2fb84b200ab6ef34e30dcbba4c0cf8d435 |
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10-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: improve usage of TargetReg() and friends. TargetReg(arg1) does now always return a 32-bit register. We also avoid using this function directly and rather use the two-arguments overload or TargetPtrReg(). Change-Id: I746b3c29a2a2553b399b5c3e7ee3887c7e7c52c3
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421efca6d71ffe348295872743317bf107a9a94a |
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11-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix def use. Add comment to GenPCUseDefEncoding(). Fix def-use flags for several instruction encodings. Change-Id: Ifc5a2484395486c01a64307a4acddc794026d46a
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af263df7f643e699abf622c64447d31bacc14c34 |
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12-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Change GenPCUseDefEncoding(), turn on Load Hoisting for ARM64 This defines the PC resource mask as empty, as the PC is not accessible on ARM64. Unify code paths with x86 in LoadStoreElimination and LoadHoisting. Change-Id: Iea8b9e666f306c7a6ff52b6c5bf7e05b35346b2c
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ccc60264229ac96d798528d2cb7dbbdd0deca993 |
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05-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework TargetReg(symbolic_reg, wide) Make the standard implementation in Mir2Lir and the specialized one in the x86 backend return a pair when wide = "true". Introduce WideKind enumeration to improve code readability. Simplify generic code based on this implementation. Change-Id: I670d45aa2572eedfdc77ac763e6486c83f8e26b4
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7fb36ded9cd5b1d254b63b3091f35c1e6471b90e |
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10-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Add implicit null and stack checks for x86"" Fixes x86_64 cross compile issue. Removes command line options and property to set implicit checks - this is hard coded now. This reverts commit 3d14eb620716e92c21c4d2c2d11a95be53319791. Change-Id: I5404473b5aaf1a9c68b7181f5952cb174d93a90d
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0025a86411145eb7cd4971f9234fc21c7b4aced1 |
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11-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Revert "Add implicit null and stack checks for x86""" Broke the build. This reverts commit 7fb36ded9cd5b1d254b63b3091f35c1e6471b90e. Change-Id: I9df0e7446ff0913a0e1276a558b2ccf6c8f4c949
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f101319480b1fe6575891043d0c3f0599292c25c |
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07-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: fix bug and enable register promotion. Iteration over arguments in invoke implementation was not correct for wide arguments. Change-Id: I46c7edcbfc9e32ded0e9a535fab3d333905bcf41
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b5860fb459f1ed71f39d8a87b45bee6727d79fe8 |
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22-Jun-2014 |
buzbee <buzbee@google.com> |
Register promotion support for 64-bit targets Not sufficiently tested for 64-bit targets, but should be fairly close. A significant amount of refactoring could stil be done, (in later CLs). With this change we are not making any changes to the vmap scheme. As a result, it is a requirement that if a vreg is promoted to both a 32-bit view and the low half of a 64-bit view it must share the same physical register. We may change this restriction later on to allow for more flexibility for 32-bit Arm. For example, if v4, v5, v4/v5 and v5/v6 are all hot enough to promote, we'd end up with something like: v4 (as an int) -> r10 v4/v5 (as a long) -> r10 v5 (as an int) -> r11 v5/v6 (as a long) -> r11 Fix a couple of ARM64 bugs on the way... Change-Id: I6a152b9c164d9f1a053622266e165428045362f3
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4b537a851b686402513a7c4a4e60f5457bb8d7c1 |
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01-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Quick compiler: More size checks, add TargetReg variants Add variants for TargetReg for requesting specific register usage, e.g., wide and ref. More register size checks. With code adapted from https://android-review.googlesource.com/#/c/98605/. Change-Id: I852d3be509d4dcd242c7283da702a2a76357278d
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baa7c88a34fdfd230a2a383c2e388945f4d907b6 |
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30-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Rename A64_/A32_ register prefix to x/w. A64/A32 look like architecture name, but they are all for arm64. Use lower-case to name the registers defined in "ARM ARM" which can also be directly used in assembly file. Use upper-case to name the registers which are other aliases. Change-Id: I0ac38ed75f977fdc362288b01179b84feaee5614
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949cd973513f1ae29280fcde7953b0f7e70172a7 |
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23-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Enable GenSpecialCase. With the following fixes: 1. Map reference register to 64-bit argument register. 2. Set max_mapped_in_ to the index of last in. (Originally it was the low part of the wide register) Change-Id: If41de654a004a0561396e349d1f150517a72ab2f
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de68676b24f61a55adc0b22fe828f036a5925c41 |
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24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter" This reverts commit 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d. Breaks the build. Change-Id: I9faad4e9a83b32f5f38b2ef95d6f9a33345efa33
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3c12c512faf6837844d5465b23b9410889e5eb11 |
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24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"" This reverts commit de68676b24f61a55adc0b22fe828f036a5925c41. Fixes an API comment, and differentiates between inserting and appending. Change-Id: I0e9a21bb1d25766e3cbd802d8b48633ae251a6bf
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2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d |
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23-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Split out more cases of Load/StoreRef, volatile as parameter Splits out more cases of ref registers being loaded or stored. For code clarity, adds volatile as a flag parameter instead of a separate method. On ARM64, continue cleanup. Add flags to print/fatal on size mismatches. Change-Id: I30ed88433a6b4ff5399aefffe44c14a5e6f4ca4e
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5655e84e8d71697d8ef3ea901a0b853af42c559e |
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18-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Implicit checks in the compiler are independent from Runtime When cross-compiling, those flags are independent. This is an initial CL that helps bypass fatal failures when cross-compiling, as not all architectures support (and have turned on) implicit checks. The actual transport for the target architecture when it is different from the runtime needs to be implemented in a follow-up CL. Bug: 15703710 Change-Id: Idc881a9a4abfd38643b862a491a5af9b8841f693
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33ae5583bdd69847a7316ab38a8fa8ccd63093ef |
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12-Jun-2014 |
buzbee <buzbee@google.com> |
Arm64 hard-float Basic enabling of hard-float for Arm64. In future CLs we'll consolidate the various targets - there is a lot of overlap. Compilation remains turned off in this CL, but I expect to enable a subset shortly. With compilation fully enabled (including the EXPERIMENTAL opcodes with the exception of REM and THROW), we get the following run-test results: 003-omnibus-opcode failures: Classes.checkCast Classes.arrayInstance UnresTest2 Haven't gone deep, but these appear to be related to throw/catch and/or stacktrace. For REM, the generated code looks reasonable to me - my guess is that we've got something wrong on the transition to the runtime. Haven't looked deeper yet, though. The bulk of the other failure also appear to be related to transitioning to the runtime system, or handling try/catch. run-test status: Status with optimizations disabled, REM_FLOAT/DOUBLE and THROW disabled: succeeded tests: 94 failed tests: 22 failed: 003-omnibus-opcodes failed: 004-annotations failed: 009-instanceof2 failed: 024-illegal-access failed: 025-access-controller failed: 031-class-attributes failed: 044-proxy failed: 045-reflect-array failed: 046-reflect failed: 058-enum-order failed: 062-character-encodings failed: 063-process-manager failed: 064-field-access failed: 068-classloader failed: 071-dexfile failed: 083-compiler-regressions failed: 084-class-init failed: 086-null-super failed: 087-gc-after-link failed: 100-reflect2 failed: 107-int-math2 failed: 201-built-in-exception-detail-messages Change-Id: Ib66209285cad8998d77a14781de300af02a96b15
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5487494e54e719d3bb4ead7a0b73e1d456fec8da |
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11-Jun-2014 |
Ian Rogers <irogers@google.com> |
Workaround frame size issues. x86 and x86-64 are exceeding the frame size for the switch interpreter. The SOMETIMES_INLINE hack doesn't work with GCC as inline and the noinline attribute are mutually exclusive. As a temporary solution move the effected code to the the interpreter_common.cc file. Bug: 14882674 Change-Id: Id5383ef5436046b36565cd1d76de8e3d59f42cff
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8dea81ca9c0201ceaa88086b927a5838a06a3e69 |
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06-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite use/def masks to support 128 bits. Reduce LIR memory usage by holding masks by pointers in the LIR rather than directly and using pre-defined const masks for the common cases, allocating very few on the arena. Change-Id: I0f6d27ef6867acd157184c8c74f9612cebfe6c16
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58994cdb00b323339bd83828eddc53976048006f |
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16-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Hard Float ABI support in QCG This patch shows our efforts on resolving the ART limitations: - passing "float"/"double" arguments via FPR - passing "long" arguments via single GPR, not pair - passing more than 3 agruments via GPR. Work done: - Extended SpecialTargetRegister enum with kARG4, kARG5, fARG4..fARG7. - Created initial LoadArgRegs/GenDalvikX/FlushIns version in X86Mir2Lir. - Unlimited number of long/double/float arguments support - Refactored (v2) Change-Id: I5deadd320b4341d5b2f50ba6fa4a98031abc3902 Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com> Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com> Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com> Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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089142cf1d0c028b5a7c703baf0b97f4a4ada3f7 |
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05-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Avoid register pool allocations on the heap. Create a helper template class ArrayRef and use it instead of std::vector<> for register pools in target_<arch>.cc to avoid these heap allocations during program startup. Change-Id: I4ab0205af9c1d28a239c0a105fcdc60ba800a70a
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511c8a653d5896e81428393a1c3d427da64e36f3 |
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03-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix cmp-long and method with long arguments. 1. Fix cmp-long. 2. Use single register to pass long argument. 3. Flush StackReference<ArtMethod> on arm64 the same as in common code. 3. Fix the mismatch in calculate reg offset. Change-Id: Ie2723260fb143512e4da6ee88d4f3aded80d3d5e
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a0cd2d701f29e0bc6275f1b13c0edfd4ec391879 |
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01-Jun-2014 |
buzbee <buzbee@google.com> |
Quick compiler: reference cleanup For 32-bit targets, object references are 32 bits wide both in Dalvik virtual registers and in core physical registers. Because of this, object references and non-floating point values were both handled as if they had the same register class (kCoreReg). However, for 64-bit systems, references are 32 bits in Dalvik vregs, but 64 bits in physical registers. Although the same underlying physical core registers will still be used for object reference and non-float values, different register class views will be used to represent them. For example, an object reference in arm64 might be held in x3 at some point, while the same underlying physical register, w3, would be used to hold a 32-bit int. This CL breaks apart the handling of object reference and non-float values to allow the proper register class (or register view) to be used. A new register class, kRefReg, is introduced which will map to a 32-bit core register on 32-bit targets, and 64-bit core registers on 64-bit targets. From this point on, object references should be allocated registers in the kRefReg class rather than kCoreReg. Change-Id: I6166827daa8a0ea3af326940d56a6a14874f5810
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ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
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03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE Merge ART from AOSP to lmp-preview-dev. Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
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0955f7e470fb733aef07096536e9fba7c99250aa |
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23-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fixing some assertions. Fixing some assertions while attempting to get libartd.so to work. Fixing also the shift logic in LoadBaseIndexed() and StoreBaseIndexed(). This commit only fixes a part of the assertion issues. Change-Id: I473194d4260dd59a8ee6d73114429728c977ee0e
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48241e786121e1c4c050d9cfad3d22de270a3e75 |
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23-May-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Add suspend check in managed code. TODO: Remove x19 in the frame in runtime, generic jni, compiled jni. Change-Id: Ibdc292c9e7adb3a5d3eff353c22f60ffc101f549
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ed65c5e982705defdb597d94d1aa3f2997239c9b |
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22-May-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable LONG_* and INT_* opcodes. This patch fixes some of the issues with LONG and INT opcodes. The patch has been tested and passes all the dalvik tests except for 018 and 107. Change-Id: Idd1923ed935ee8236ab0c7e5fa969eaefeea8708 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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b01bf15d18f9b08d77e7a3c6e2897af0e02bf8ca |
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14-May-2014 |
buzbee <buzbee@google.com> |
64-bit temp register support. Add a 64-bit temp register allocation path. The recent physical register handling rework supports multiple views of the same physical register (or, such as for Arm's float/double regs, different parts of the same physical register). This CL adds a 64-bit core register view for 64-bit targets. In short, each core register will have a 64-bit name, and a 32-bit name. The different views will be kept in separate register pools, but aliasing will be tracked. The core temp register allocation routines will be largely identical - except for 32-bit targets, which will continue to use pairs of 32-bit core registers for holding long values. Change-Id: I8f118e845eac7903ad8b6dcec1952f185023c053
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082833c8d577db0b2bebc100602f31e4e971613e |
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18-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler, out of registers fix It turns out that the register pool sanity checker was not working as expected, leaving some inconsistencies unreported. This could result in "out of registers" failures, as well as other more subtle problems. This CL fixes the sanity checker, adds a lot more check and cleans up the previously undetected episodes of insanity. Cherry-pick of internal change 468162 Change-Id: Id2da97e99105a4c272c5fd256205a94b904ecea8
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05d3aeb33683b16837741f9348d6fba9a8432068 |
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18-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler, out of registers fix Fixes b/15024623 It turns out that the register pool sanity checker was not working as expected, leaving some inconsistencies unreported. This CL fixes the sanity checker, adds a lot more check and cleans up the previously undetected episodes of insanity. Change-Id: I4d67db864ca5926a1975db251e7e631b65a86275
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bc6d197cdb02eeac0c98ec4ed37f530b003a4e7a |
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13-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fixes in A64 code generation. - Disabled special method compilation, as it requires hard-float ABI, - Disabled suspend checks, as runtime is not yet ready (e.g. trampolines are not setting the suspend register, etc), - Changing definition of zero register (the zero register has now 0x3f as its register number), - Fixing some issues with handling of cmp instructions in the assembler: we now use the shift-register rather than the extended-register variant of cmp and cmn, - Partially fixing register setup (register sN is now mapped to dN), - Fixing and completing implementation of register spills/unspills, - Fixing LoadBaseDispBody() and StoreBaseDispBody(). Change-Id: Ia49ba48b6ca0f782380066345b7a198cb6c1dc1d
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c830430ed65497c2268649d8e78121364e31b184 |
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15-May-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix quick compiler monitor implementation. Also with some small fixes : 1. Enable some dex byte code to compile. 2. Copy the register definition from runtime.cc. 3. A quick fix for "cmp Wn, Wm" in the assembler. 4. Optimise GenMoveException a bit by using xzr. 5. Fix improper use of StoreValueWide() on 32-bit value in FlushIns(). 6. Fix one debug assert in the assembler. It can pass all cases in run-all-test, except 044 which also fails with the interpreter. Change-Id: I9cc0253f1039c78d5100640235ac33e884b02560
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2f244e9faccfcca68af3c5484c397a01a1c3a342 |
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08-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Add more ThreadOffset in Mir2Lir and backends This duplicates all methods with ThreadOffset parameters, so that both ThreadOffset<4> and ThreadOffset<8> can be handled. Dynamic checks against the compilation unit's instruction set determine which pointer size to use and therefore which methods to call. Methods with unsupported pointer sizes should fatally fail, as this indicates an issue during method selection. Change-Id: Ifdb445b3732d3dc5e6a220db57374a55e91e1bf6
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674744e635ddbdfb311fbd25b5a27356560d30c3 |
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24-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Use atomic load/store for volatile IGET/IPUT/SGET/SPUT. Bug: 14112919 Change-Id: I79316f438dd3adea9b2653ffc968af83671ad282
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e45fb9e7976c8462b94a58ad60b006b0eacec49f |
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06-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Change arm64 backend to produce A64 code. The arm backend clone is changed to produce A64 code. At the moment this backend can only compile simple methods (both leaf and non-leaf). Most of the work on the assembler (assembler_arm64.cc) has been done. Some work on the LIR generation layer (functions such as OpRegRegImm & friends) is still necessary. The register allocator still needs to be adapted to the A64 instruction set (it is mostly unchanged from the arm backend). Offsets for helpers in gen_invoke.cc still need to be changed to work on 64-bit. Change-Id: I388f99eeb832857981c7d9d5cb5b71af64a4b921
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43ec8737d8356dbff0a90bee521fb0e73438da47 |
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31-Mar-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Added arm64 quick backend as an arm clone. Created a new directory arm64 under compiler/dex/quick which contains a copy of the 32-bit arm backend. In following CLs, this code will be replaced/modified to support Aarch64. Change-Id: I06c468db8d588e339eecf4d7d85276d5e334a17a
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