/art/compiler/linker/x86_64/ |
H A D | relative_patcher_x86_64.cc | 29 uint32_t displacement = target_offset - patch_offset; local 30 displacement -= kPcDisplacement; // The base PC is at the end of the 4-byte patch. 33 reinterpret_cast<unaligned_int32_t*>(&(*code)[patch.LiteralOffset()])[0] = displacement;
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/art/compiler/linker/x86/ |
H A D | relative_patcher_x86_base.cc | 41 uint32_t displacement = target_offset - patch_offset; local 42 displacement -= kPcDisplacement; // The base PC is at the end of the 4-byte patch. 45 reinterpret_cast<unaligned_int32_t*>(&(*code)[literal_offset])[0] = displacement;
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/art/compiler/linker/arm/ |
H A D | relative_patcher_arm_base.cc | 119 uint32_t displacement = target_offset - patch_offset; local 121 if (displacement > max_positive_displacement_ && displacement < -max_negative_displacement_) { 127 displacement = thunk_locations_[current_thunk_to_write_] - patch_offset; 132 displacement = thunk_locations_[current_thunk_to_write_ - 1] - patch_offset; 133 DCHECK(displacement >= -max_negative_displacement_); 136 return displacement;
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H A D | relative_patcher_thumb2.cc | 37 uint32_t displacement = CalculateDisplacement(patch_offset, target_offset & ~1u); local 38 displacement -= kPcDisplacement; // The base PC is at the end of the 4-byte patch. 39 DCHECK_EQ(displacement & 1u, 0u); 40 DCHECK((displacement >> 24) == 0u || (displacement >> 24) == 255u); // 25-bit signed. 41 uint32_t signbit = (displacement >> 31) & 0x1; 42 uint32_t i1 = (displacement >> 23) & 0x1; 43 uint32_t i2 = (displacement >> 22) & 0x1; 44 uint32_t imm10 = (displacement >> 12) & 0x03ff; 45 uint32_t imm11 = (displacement >> [all...] |
/art/compiler/jni/quick/ |
H A D | calling_convention.h | 57 // Place iterator at start of arguments. The displacement is applied to 60 void ResetIterator(FrameOffset displacement) { argument 61 displacement_ = displacement;
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/art/compiler/linker/arm64/ |
H A D | relative_patcher_arm64.cc | 139 uint32_t displacement = CalculateDisplacement(patch_offset, target_offset & ~1u); local 140 DCHECK_EQ(displacement & 3u, 0u); 141 DCHECK((displacement >> 27) == 0u || (displacement >> 27) == 31u); // 28-bit signed. 142 uint32_t insn = (displacement & 0x0fffffffu) >> 2; 251 // be negative yet passed as uint32_t. Therefore we limit the displacement 253 // the highest bit of the displacement. This is encoded in bit 23. 282 // LDR <Xt>, <label> is aligned iff the pc + displacement is a multiple of 8.
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/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64_test.cc | 1127 ssize_t displacement = static_cast<ssize_t>(frame_size) - (spill_regs.size() * 8 + 8); local 1128 str << "subq $" << displacement << ", %rsp\n"; local 1158 ssize_t displacement = static_cast<ssize_t>(frame_size) - spill_regs.size() * 8 - 8; local 1159 str << "addq $" << displacement << ", %rsp\n"; local
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/art/runtime/interpreter/ |
H A D | interpreter_goto_table_impl.cc | 2489 int32_t displacement = static_cast<int32_t>(found_dex_pc) - static_cast<int32_t>(dex_pc); local 2490 ADVANCE(displacement);
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/art/compiler/dex/quick/mips/ |
H A D | utility_mips.cc | 690 LIR* MipsMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, argument 693 * Load value from base + displacement. Optionally perform null check 704 bool short_form = IS_SIMM16(displacement); 717 DCHECK_EQ((displacement & 0x3), 0); 725 short_form = IS_SIMM16_2WORD(displacement); 739 DCHECK_EQ((displacement & 0x3), 0); 743 DCHECK_EQ((displacement & 0x1), 0); 747 DCHECK_EQ((displacement & 0x1), 0); 761 load = res = NewLIR3(opcode, r_dest.GetReg(), displacement, r_base.GetReg()); 764 res = OpRegRegImm(kOpAdd, r_tmp, r_base, displacement); 851 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument 875 StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size) argument 1004 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument [all...] |
H A D | target_mips.cc | 789 LIR* MipsMir2Lir::GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest) { argument 797 OpRegRegImm(kOpAdd, reg_ptr, r_base, displacement); 811 LIR* MipsMir2Lir::GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src) { argument 821 OpRegRegImm(kOpAdd, temp_ptr, r_base, displacement);
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/art/compiler/dex/quick/x86/ |
H A D | fp_x86.cc | 177 int displacement = is_double ? dest_v_reg_offset + LOWORD_OFFSET : dest_v_reg_offset; local 178 LIR *fstp = NewLIR2NoDest(opcode, rs_rX86_SP_32.GetReg(), displacement); 179 AnnotateDalvikRegAccess(fstp, displacement >> 2, false /* is_load */, is_double); 438 int displacement = dest_v_reg_offset + LOWORD_OFFSET; local 440 LIR *fst = NewLIR2NoDest(opcode, rs_rSP.GetReg(), displacement); 441 AnnotateDalvikRegAccess(fst, displacement >> 2, false /* is_load */, is_double /* is64bit */); 651 int displacement = SRegOffset(rl_dest.s_reg_low); local 653 LIR *lir = NewLIR3(kX86And32MI, rs_rX86_SP_32.GetReg(), displacement, 0x7fffffff); 654 AnnotateDalvikRegAccess(lir, displacement >> 2, false /*is_load */, false /* is_64bit */); 655 AnnotateDalvikRegAccess(lir, displacement >> 715 int displacement = SRegOffset(rl_dest.s_reg_low); local [all...] |
H A D | assemble_x86.cc | 640 int32_t raw_base, int32_t displacement) { 690 if (displacement != 0 || LowRegisterBits(raw_base) == rs_rBP.GetRegNum()) { 691 // BP requires an explicit displacement, even when it's 0. 701 size += IS_SIMM8(displacement) ? 1 : 4; 737 // Thread displacement size is always 32bit. 749 // Thread displacement size is always 32bit. 765 // Thread displacement size is always 32bit. 834 // Thread displacement size is always 32bit. 853 // Thread displacement size is always 32bit. 862 // Force the displacement siz 639 ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, int32_t raw_base, int32_t displacement) argument 1364 EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t displacement, int32_t raw_cl) argument [all...] |
H A D | utility_x86.cc | 400 int displacement = SRegOffset(rl_dest.s_reg_low); local 418 LIR *l = NewLIR3(opcode, rs_rX86_SP_32.GetReg(), displacement, r_value); 420 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); 421 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is64Bit /* is_64bit */); 429 int displacement = SRegOffset(rl_value.s_reg_low); local 444 LIR *l = NewLIR3(opcode, r_dest.GetReg(), rs_rX86_SP_32.GetReg(), displacement); 446 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); 644 int displacement, RegStorage r_dest, OpSize size) { 662 DCHECK_EQ((displacement & 0x3), 0); 680 DCHECK_EQ((displacement 643 LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_dest, OpSize size) argument 776 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument 791 StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_src, OpSize size, int opt_flags) argument 910 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument [all...] |
H A D | int_x86.cc | 1637 void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { argument 1649 LoadBaseDisp(rs_rSP, displacement, dest, k32, kNotVolatile); 1654 rs_rX86_SP_32.GetReg(), displacement, val); 1655 AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); 1773 int displacement = SRegOffset(rl_src1.s_reg_low); local 1781 GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); 1782 GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); 1795 LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP_32.GetReg(), displacement + LOWORD_OFFSET); 1796 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1877 int displacement local 1899 int displacement = SRegOffset(rl_src1.s_reg_low); local 1910 int displacement = SRegOffset(rl_src2.s_reg_low); local 1933 int displacement = SRegOffset(rl_src1.s_reg_low); local 1977 int displacement = SRegOffset(rl_src.s_reg_low); local 2020 int displacement = SRegOffset(rl_dest.s_reg_low); local 2257 int displacement = SRegOffset(rl_src.s_reg_low); local 2870 int displacement = SRegOffset(rl_dest.s_reg_low); local 2901 int displacement = SRegOffset(rl_dest.s_reg_low); local 3342 int displacement = SRegOffset(rl_src.s_reg_low); local [all...] |
H A D | target_x86.cc | 906 int displacement = SRegOffset(rl_dest.s_reg_low); local 909 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); 910 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 912 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); 913 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 1360 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); local 1362 Load32Disp(rs_rX86_SP_32, displacement, rs_rDI); 2228 int displacement = SRegOffset(rl_result.s_reg_low); local 2230 LIR *l = NewLIR4(extr_opcode, rs_rX86_SP_32.GetReg(), displacement, vector_src.GetReg(), 2232 AnnotateDalvikRegAccess(l, displacement >> [all...] |
/art/compiler/dex/quick/arm/ |
H A D | utility_arm.cc | 881 int displacement, RegStorage r_src_dest, 883 DCHECK_EQ(displacement & 3, 0); 885 int encoded_disp = (displacement & kOffsetMask) >> 2; // Within range of the instruction. 887 if ((displacement & ~kOffsetMask) != 0) { 889 // Add displacement & ~kOffsetMask to base, it's a single instruction for up to +-256KiB. 890 OpRegRegImm(kOpAdd, r_ptr, r_base, displacement & ~kOffsetMask); 899 if ((displacement & ~kOffsetMask) != 0 && !r_work.Valid()) { 906 * Load value from base + displacement. Optionally perform null check 910 LIR* ArmMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, argument 925 load = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2Vldrd, r_base, displacement, r_des 880 LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base, int displacement, RegStorage r_src_dest, RegStorage r_work) argument 1030 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument 1060 StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size) argument 1172 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument [all...] |
/art/disassembler/ |
H A D | disassembler_x86.cc | 1344 int32_t displacement; local 1346 displacement = *reinterpret_cast<const int8_t*>(instr); 1350 displacement = *reinterpret_cast<const int32_t*>(instr); 1353 args << StringPrintf("%+d (", displacement) 1354 << FormatInstructionPointer(instr + displacement)
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/art/compiler/dex/quick/arm64/ |
H A D | utility_arm64.cc | 1187 * Load value from base + displacement. Optionally perform null check 1191 LIR* Arm64Mir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, argument 1245 bool displacement_is_aligned = (displacement & ((1 << scale) - 1)) == 0; 1246 int scaled_disp = displacement >> scale; 1250 } else if (alt_opcode != kA64Brk1d && IS_SIGNED_IMM9(displacement)) { 1252 load = NewLIR3(alt_opcode, r_dest.GetReg(), r_base.GetReg(), displacement); 1255 // TODO: cleaner support for index/displacement registers? Not a reference, but must match width. 1257 LoadConstantWide(r_scratch, displacement); 1267 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit()); 1272 LIR* Arm64Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorag argument 1287 StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size) argument 1362 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument [all...] |
/art/compiler/dex/quick/ |
H A D | mir_to_lir.h | 976 LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { argument 977 return LoadBaseDisp(r_base, displacement, r_dest, kWord, kNotVolatile); 980 LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { argument 981 return LoadBaseDisp(r_base, displacement, r_dest, k32, kNotVolatile); 983 // Load a reference at base + displacement and decompress into register. 984 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, argument 986 return LoadBaseDisp(r_base, displacement, r_dest, kReference, is_volatile); 1005 LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { argument 1006 return StoreBaseDisp(r_base, displacement, r_src, kWord, kNotVolatile); 1009 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorag argument 1018 Store32Disp(RegStorage r_base, int displacement, RegStorage r_src) argument [all...] |