/art/compiler/dex/quick/arm64/ |
H A D | target_arm64.cc | 237 static void DecodeRegExtendOrShift(int operand, char *buf, size_t buf_size) { argument 238 if ((operand & (1 << 6)) == 0) { 239 const char *shift_name = shift_names[(operand >> 7) & 0x3]; 240 int amount = operand & 0x3f; 243 const char *extend_name = extend_names[(operand >> 3) & 0x7]; 244 int amount = operand & 0x7; 347 int operand; local 357 operand = lir->operands[nc-'0']; 364 if (LIKELY(operand == omittable)) { 367 DecodeRegExtendOrShift(operand, tbu [all...] |
H A D | assemble_arm64.cc | 71 * of the key, "p" is which numeric operand to use and "f" is the 96 * H -> operand shift 708 uint32_t operand = lir->operands[i]; local 715 bool is_zero = A64_REG_IS_ZR(operand); 764 RegStorage reg(operand | RegStorage::kValid); 789 << ". Expected " << expected << ", got 0x" << std::hex << operand; 792 << ". Expected " << expected << ", got 0x" << std::hex << operand; 797 // In the lines below, we rely on (operand & 0x1f) == 31 to be true for register sp 805 value = (operand << encoder->field_loc[i].start) & 818 DCHECK_EQ((operand [all...] |
/art/compiler/dex/quick/arm/ |
H A D | target_arm.cc | 362 int operand; local 372 operand = lir->operands[nc-'0']; 375 if (operand != 0) { 376 snprintf(tbuf, arraysize(tbuf), ", %s %d", shift_names[operand & 0x3], operand >> 2); 382 switch (operand) { 410 tbuf[i] += operand & 1; 411 operand >>= 1; 415 operand = ~ExpandImmediate(operand); [all...] |
H A D | assemble_arm.cc | 48 * of the key, "p" is which numeric operand to use and "f" is the 74 * H -> operand shift 1104 uint32_t operand; local 1106 operand = lir->operands[i]; 1109 value = (operand << encoder->field_loc[i].start) & 1115 value = (operand << encoder->field_loc[i].start) & 1121 value = (operand << encoder->field_loc[i].start) & 1133 value = ((operand & 0xF0) >> 4) << encoder->field_loc[i].end; 1134 value |= (operand & 0x0F) << encoder->field_loc[i].start; 1138 value = ((operand 1170 DCHECK(RegStorage::IsDouble(operand)) << ", Operand = 0x" << std::hex << operand; local 1180 DCHECK(RegStorage::IsSingle(operand)) << ", Operand = 0x" << std::hex << operand; local [all...] |
/art/compiler/dex/quick/mips/ |
H A D | target_mips.cc | 375 int operand; local 385 operand = lir->operands[nc-'0']; 390 tbuf[i] += operand & 1; 391 operand >>= 1; 395 snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand)); 398 DCHECK_EQ(RegStorage::RegNum(operand) & 1, 0); 399 snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand)); 402 snprintf(tbuf, arraysize(tbuf), "%04x", operand); 406 snprintf(tbuf, arraysize(tbuf), "%d", operand); 409 snprintf(tbuf, arraysize(tbuf), "%d", operand [all...] |
H A D | assemble_mips.cc | 50 * of the key, "p" is which numeric operand to use and "f" is the 795 uint32_t operand; local 797 operand = lir->operands[i]; 803 value = operand; 805 value = (operand << encoder->field_loc[i].start) & 811 value = (operand & 0x1f); 817 DCHECK(RegStorage::IsDouble(operand)) << ", Operand = 0x" << std::hex << operand; local 819 DCHECK_EQ((operand & 0x1), 0U); // May only use even numbered registers for mips32. 821 value = (RegStorage::RegNum(operand) << encode 827 DCHECK(RegStorage::IsSingle(operand)) << ", Operand = 0x" << std::hex << operand; local [all...] |
/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64.h | 156 // Get the operand encoding byte at the given index. 557 void shll(CpuRegister operand, CpuRegister shifter); 559 void shrl(CpuRegister operand, CpuRegister shifter); 561 void sarl(CpuRegister operand, CpuRegister shifter); 564 void shlq(CpuRegister operand, CpuRegister shifter); 566 void shrq(CpuRegister operand, CpuRegister shifter); 568 void sarq(CpuRegister operand, CpuRegister shifter); 779 void EmitOperand(uint8_t rm, const Operand& operand); 781 void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate); 787 void EmitGenericShift(bool wide, int rm, CpuRegister operand, CpuRegiste [all...] |
H A D | assembler_x86_64.cc | 654 // Emit a REX.W prefix if the operand size is 64 bits. 669 // Emit a REX.W prefix if the operand size is 64 bits. 689 // Emit a REX.W prefix if the operand size is 64 bits. 704 // Emit a REX.W prefix if the operand size is 64 bits. 764 // Emit a REX.W prefix if the operand size is 64 bits. 784 // Emit a REX.W prefix if the operand size is 64 bits. 1494 // W - 64-bit operand 1521 // W - 64-bit operand 1799 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) { argument 1800 EmitGenericShift(false, 4, operand, shifte 1804 shlq(CpuRegister operand, CpuRegister shifter) argument 1819 shrl(CpuRegister operand, CpuRegister shifter) argument 1824 shrq(CpuRegister operand, CpuRegister shifter) argument 1834 sarl(CpuRegister operand, CpuRegister shifter) argument 1844 sarq(CpuRegister operand, CpuRegister shifter) argument 2108 EmitOperand(uint8_t reg_or_opcode, const Operand& operand) argument 2136 EmitComplex(uint8_t reg_or_opcode, const Operand& operand, const Immediate& immediate) argument 2199 EmitGenericShift(bool wide, int reg_or_opcode, CpuRegister operand, CpuRegister shifter) argument 2258 EmitOptionalRex32(const Operand& operand) argument 2265 EmitOptionalRex32(CpuRegister dst, const Operand& operand) argument 2275 EmitOptionalRex32(XmmRegister dst, const Operand& operand) argument 2293 EmitRex64(const Operand& operand) argument 2311 EmitRex64(CpuRegister dst, const Operand& operand) argument 2319 EmitRex64(XmmRegister dst, const Operand& operand) argument 2333 EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) argument [all...] |
/art/compiler/dex/ |
H A D | global_value_numbering.cc | 212 uint16_t operand = lvns_[pred_id]->GetSregValue(pred_bb->last_mir_insn->ssa_rep->uses[0]); local 213 if (operand == cond) {
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H A D | local_value_numbering.cc | 1607 uint16_t operand = GetOperandValue(mir->ssa_rep->uses[0]); local 1609 res = gvn_->LookupValue(Instruction::INSTANCE_OF, operand, type, kNoValue); 1617 uint16_t operand = GetOperandValue(mir->ssa_rep->uses[0]); local 1619 uint16_t cond = gvn_->FindValue(Instruction::INSTANCE_OF, operand, type, kNoValue); 1732 // res = op + 1 operand 1743 // res = op + 1 wide operand 1755 // wide res = op + 1 wide operand 1766 // wide res = op + 1 operand 1862 // wide res = op + 1 wide operand + 1 operand [all...] |
/art/compiler/utils/x86/ |
H A D | assembler_x86.cc | 1299 void X86Assembler::shll(Register operand, Register shifter) { argument 1300 EmitGenericShift(4, Operand(operand), shifter); 1319 void X86Assembler::shrl(Register operand, Register shifter) { argument 1320 EmitGenericShift(5, Operand(operand), shifter); 1339 void X86Assembler::sarl(Register operand, Register shifter) { argument 1340 EmitGenericShift(7, Operand(operand), shifter); 1619 void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) { argument 1622 const int length = operand.length_; 1625 CHECK_EQ(operand.encoding_[0] & 0x38, 0); 1626 EmitUint8(operand 1639 EmitComplex(int reg_or_opcode, const Operand& operand, const Immediate& immediate) argument 1680 EmitGenericShift(int reg_or_opcode, const Operand& operand, const Immediate& imm) argument 1696 EmitGenericShift(int reg_or_opcode, const Operand& operand, Register shifter) argument [all...] |
H A D | assembler_x86.h | 122 // Get the operand encoding byte at the given index. 432 void shll(Register operand, Register shifter); 436 void shrl(Register operand, Register shifter); 440 void sarl(Register operand, Register shifter); 627 void EmitOperand(int rm, const Operand& operand); 629 void EmitComplex(int rm, const Operand& operand, const Immediate& immediate); 634 void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm); 635 void EmitGenericShift(int rm, const Operand& operand, Register shifter);
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/art/compiler/dex/quick/x86/ |
H A D | target_x86.cc | 376 int operand = lir->operands[operand_number]; local 379 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 380 buf += x86CondName[operand]; 383 buf += StringPrintf("%d", operand); 386 int64_t value = static_cast<int64_t>(static_cast<int64_t>(operand) << 32 | 392 const EmbeddedData* tab_rec = UnwrapPointer<EmbeddedData>(operand); 397 if (RegStorage::IsFloat(operand)) { 398 int fp_reg = RegStorage::RegNum(operand); 401 int reg_num = RegStorage::RegNum(operand); 408 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, [all...] |
/art/compiler/optimizing/ |
H A D | code_generator_arm.cc | 971 ShifterOperand operand; local 972 if (GetAssembler()->ShifterOperandCanHold(R0, left, CMP, value, &operand)) { 973 __ cmp(left, operand); 1050 ShifterOperand operand; local 1051 if (GetAssembler()->ShifterOperandCanHold(R0, left, CMP, value, &operand)) { 1052 __ cmp(left, operand); 1845 // immediate operand. Instead, use two 32-bit core 1907 // immediate operand. Instead, use two 32-bit core
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