/external/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 25 /// \note While the number of elements in DstVT type correct, the
28 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
argument 38 DstVT = MVT::v8i16;
43 DstVT = MVT::v16i16;
50 DstVT = MVT::v4i32;
55 DstVT = MVT::v8i32;
62 DstVT = MVT::v2i64;
67 DstVT = MVT::v4i64;
75 DstVT = MVT::v4i32;
80 DstVT 920 MVT SrcVT, DstVT; local [all...] |
/external/llvm/lib/Target/X86/Utils/ |
H A D | X86ShuffleDecode.cpp | 402 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT, SmallVectorImpl<int> &Mask) {
argument 403 unsigned NumDstElts = DstVT.getVectorNumElements();
405 unsigned DstScalarBits = DstVT.getScalarSizeInBits();
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/external/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 277 EVT DstVT = Dst.getValueType(); local 281 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 282 DAG.getConstant(Offset, DstVT)),
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H A D | X86FastISel.cpp | 95 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 520 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 522 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, argument 525 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, 1017 EVT DstVT = VA.getValVT(); local 1019 if (SrcVT != DstVT) { 1026 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); 1036 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, 1285 EVT DstVT = TLI.getValueType(I->getType()); local 1286 if (!TLI.isTypeLegal(DstVT)) 2151 EVT DstVT = TLI.getValueType(I->getType()); local 3223 EVT DstVT = TLI.getValueType(I->getType()); local [all...] |
H A D | X86ISelDAGToDAG.cpp | 506 MVT DstVT = N->getSimpleValueType(0); local 509 if (SrcVT.isVector() || DstVT.isVector()) 517 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); 535 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. 537 MemVT = SrcIsSSE ? SrcVT : DstVT; 547 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
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H A D | X86ISelLowering.cpp | 11751 MVT DstVT = Op.getSimpleValueType(); local 11752 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 11756 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) 11822 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 16880 MVT DstVT = Op.getSimpleValueType(); local 16884 if (DstVT != MVT::f64) 16912 assert((DstVT == MVT::i64 || 16913 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 16916 if (SrcVT==MVT::i64 && DstVT 17461 EVT DstVT = N->getValueType(0); local [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 482 VectorType *DstVT = dyn_cast<VectorType>(BCI.getDestTy()); local 484 if (!DstVT || !SrcVT) 487 unsigned DstNumElems = DstVT->getNumElements(); 496 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(), 502 Type *MidTy = VectorType::get(DstVT->getElementType(), FanOut); 528 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(),
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 1228 EVT DstVT = TLI.getValueType(I->getType()); local 1230 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || 1231 !DstVT.isSimple()) 1236 if (!TLI.isTypeLegal(DstVT)) 1250 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 1278 MVT DstVT = DstEVT.getSimpleVT(); local 1286 if (SrcVT == DstVT) { 1288 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); 1299 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); 1565 EVT DstVT local [all...] |
H A D | LegalizeIntegerTypes.cpp | 2735 EVT DstVT = N->getValueType(0); local 2736 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2739 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first; 2839 EVT DstVT = N->getValueType(0); local 2843 // treated as signed) is representable in DstVT. Check that the mantissa 2844 // size of DstVT is >= than the number of bits in SrcVT -1. 2845 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT); 2849 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2896 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2901 return DAG.getNode(ISD::FADD, dl, DstVT, SignedCon [all...] |
H A D | DAGCombiner.cpp | 5438 EVT DstVT = N->getValueType(0); local 5468 !N0.hasOneUse() || LN0->isVolatile() || !DstVT.isVector() || 5469 !DstVT.isPow2VectorType() || !TLI.isVectorLoadExtDesirable(SDValue(N, 0))) 5481 EVT SplitDstVT = DstVT; 5493 DstVT.getVectorNumElements() / SplitDstVT.getVectorNumElements(); 5517 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 970 EVT DstVT = N->getValueType(0); local 993 DstVT = MVT::i32; 997 if (DstVT == MVT::i64) 1003 InsertTo64 = DstVT == MVT::i64; 1006 DstVT = MVT::i32; 1010 if (DstVT == MVT::i64) 1016 InsertTo64 = DstVT == MVT::i64; 1019 DstVT = MVT::i32; 1035 SDNode *Res = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, DstVT,
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 964 MVT DstVT; local 966 if (!isTypeLegal(DstTy, DstVT)) 969 if (DstVT != MVT::f32 && DstVT != MVT::f64) 997 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT()) 1019 if (DstVT == MVT::f32) 1073 MVT DstVT, SrcVT; local 1075 if (!isTypeLegal(DstTy, DstVT)) 1078 if (DstVT != MVT::i32 && DstVT ! [all...] |
/external/llvm/lib/CodeGen/ |
H A D | CodeGenPrepare.cpp | 723 EVT DstVT = TLI.getValueType(CI->getType()); local 726 if (SrcVT.isInteger() != DstVT.isInteger()) 731 if (SrcVT.bitsLT(DstVT)) return false; 739 if (TLI.getTypeAction(CI->getContext(), DstVT) == 741 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); 744 if (SrcVT != DstVT)
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 4018 EVT DstVT = N->getValueType(0); local 4019 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 4023 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 4028 return DAG.getNode(ISD::BITCAST, dl, DstVT, 4033 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
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