| /external/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfExpression.cpp | 131 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8; local
134 SmallBitVector Coverage(RegSize, false);
143 SmallBitVector Intersection(RegSize, false);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 821 unsigned RegSize = TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize(); local
849 if (isMatchingUpdateInsn(MI, BaseReg, RegSize))
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| H A D | AArch64FastISel.cpp | 1599 unsigned RegSize; local
1610 RegSize = 32;
1616 RegSize = 64;
1620 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
1625 AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
3927 unsigned RegSize = Is64Bit ? 64 : 32; local
3974 unsigned ImmR = RegSize - Shift;
4034 unsigned RegSize = Is64Bit ? 64 : 32; local
4082 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4155 unsigned RegSize local
[all...] |
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 61 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
63 unsigned MFLoOpc, unsigned RegSize);
180 unsigned RegSize) {
188 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
199 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
205 unsigned RegSize) {
213 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
223 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
179 expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize) argument
203 expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, unsigned MFLoOpc, unsigned RegSize) argument
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 717 unsigned RegSize = RegisterVT.getSizeInBits(); local
721 if (NumZeroBits == RegSize) {
733 if (NumSignBits == RegSize)
735 else if (NumZeroBits >= RegSize-1)
737 else if (NumSignBits > RegSize-8)
739 else if (NumZeroBits >= RegSize-8)
741 else if (NumSignBits > RegSize-16)
743 else if (NumZeroBits >= RegSize-16)
745 else if (NumSignBits > RegSize-32)
747 else if (NumZeroBits >= RegSize
[all...] |
| /external/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes member in class:llvm::MCRegisterClass
82 unsigned getSize() const { return RegSize; }
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, argument
216 (RegSize != 64 && (Imm >> RegSize != 0 || Imm == ~0U)))
220 unsigned Size = RegSize;
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 632 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
634 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
636 explicit operator bool() const { return RegSize; }
638 unsigned RegSize, ImmLSB, ImmSize; member in struct:__anon10894::LogicOp
722 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
724 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
726 if (And.RegSize == 64) {
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 140 int RegSize; local
143 RegSize = 8;
147 RegSize = 4;
160 count += RegSize;
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| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 5183 unsigned RegSize = local
5186 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
5191 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
|