/external/llvm/lib/Target/BPF/ |
H A D | BPFISelDAGToDAG.cpp | 136 EVT VT = Node->getValueType(0); local 137 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT); 140 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI); 141 return CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI);
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/external/llvm/utils/TableGen/ |
H A D | CallingConvEmitter.cpp | 91 Record *VT = VTs->getElementAsRecord(i); local 93 O << "LocVT == " << getEnumName(getValueType(VT));
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H A D | DAGISelMatcher.cpp | 228 OS.indent(indent) << "EmitInteger " << Val << " VT=" << VT << '\n'; local 233 OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << VT << '\n'; local 242 OS << " VT=" << VT << '\n'; local 311 return HashString(Val) ^ VT;
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H A D | CodeGenTarget.cpp | 490 MVT::SimpleValueType VT; local 495 VT = OverloadedVTs[MatchTy]; 501 VT == MVT::iAny || VT == MVT::vAny) && 504 VT = getValueType(TyEl->getValueAsDef("VT")); 506 if (MVT(VT).isOverloaded()) { 507 OverloadedVTs.push_back(VT); 512 if (VT == MVT::isVoid) 515 IS.RetVTs.push_back(VT); 524 MVT::SimpleValueType VT; local [all...] |
/external/clang/include/clang/AST/ |
H A D | DeclContextInternals.h | 89 DeclsTy *VT = new DeclsTy(); local 91 VT->push_back(OldD); 92 Data = DeclsAndHasExternalTy(VT, true); 196 DeclsTy *VT = new DeclsTy(); local 197 VT->push_back(OldD); 198 Data = DeclsAndHasExternalTy(VT, false);
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/external/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 74 MVT ArgVT = Ins[i].VT; 92 MVT VT = Outs[i].VT; local 94 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) 106 MVT VT = Outs[i].VT; local 108 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { 111 << EVT(VT) 160 MVT VT = Ins[i].VT; local 174 AnalyzeCallResult(MVT VT, CCAssignFn Fn) argument 184 isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) argument 194 getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT, CCAssignFn Fn) argument [all...] |
/external/llvm/lib/IR/ |
H A D | ValueTypes.cpp | 29 EVT VT; local 30 VT.LLVMTy = IntegerType::get(Context, BitWidth); 31 assert(VT.isExtended() && "Type is not extended!"); 32 return VT; 35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, argument 38 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 53 EVT VT = MVT::i32; local 68 Loads[i] = DAG.getLoad(VT, dl, Chain, 102 VT = MVT::i16; 105 VT = MVT::i8; 109 Loads[i] = DAG.getLoad(VT, dl, Chain, 126 VT = MVT::i16; 129 VT = MVT::i8;
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/external/clang/lib/CodeGen/ |
H A D | CodeGenTypes.cpp | 471 const VectorType *VT = cast<VectorType>(Ty); local 472 ResultType = llvm::VectorType::get(ConvertType(VT->getElementType()), 473 VT->getNumElements());
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/external/guava/guava/src/com/google/common/base/ |
H A D | Ascii.java | 172 public static final byte VT = 11; field in class:Ascii
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/external/lldb/test/pexpect-2.4/ |
H A D | screen.py | 17 VT = 11 # Same as LF. variable
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 104 MVT VT = Node->getSimpleValueType(ResNo); local 107 if (TLI->isTypeLegal(VT)) 108 UseRC = TLI->getRegClassFor(VT); 127 MVT VT = Node->getSimpleValueType(Op.getResNo()); local 128 if (VT == MVT::Other || VT == MVT::Glue) 157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 163 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 166 DstRC = TLI->getRegClassFor(VT); 441 MVT VT, DebugLo [all...] |
H A D | ResourcePriorityQueue.cpp | 96 MVT VT = ScegN->getSimpleValueType(i); local 97 if (TLI->isTypeLegal(VT) 98 && (TLI->getRegClassFor(VT)->getID() == RCId)) { 134 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); local 135 if (TLI->isTypeLegal(VT) 136 && (TLI->getRegClassFor(VT)->getID() == RCId)) { 334 MVT VT = SU->getNode()->getSimpleValueType(i); local 335 if (TLI->isTypeLegal(VT) 336 && TLI->getRegClassFor(VT) 337 && TLI->getRegClassFor(VT) 343 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); local 486 MVT VT = ScegN->getSimpleValueType(i); local 497 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); local [all...] |
H A D | SelectionDAGPrinter.cpp | 94 EVT VT = Op.getValueType(); local 95 if (VT == MVT::Glue) 97 else if (VT == MVT::Other)
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16ISelDAGToDAG.cpp | 280 EVT VT = LHS.getValueType(); local 283 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops); 285 SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT, 288 SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
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/external/llvm/lib/Target/X86/Utils/ |
H A D | X86ShuffleDecode.cpp | 66 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) {
argument 67 unsigned NumElts = VT.getVectorNumElements();
74 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) {
argument 75 unsigned NumElts = VT.getVectorNumElements();
82 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) {
argument 83 unsigned VectorSizeInBits = VT.getSizeInBits();
84 unsigned ScalarSizeInBits = VT.getScalarSizeInBits();
85 unsigned NumElts = VT.getVectorNumElements();
96 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
argument 97 unsigned VectorSizeInBits = VT 110 DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 125 DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 146 DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 162 DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 178 DecodePSHUFLWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 197 DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 219 DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument 239 DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument 256 DecodeVPERM2X128Mask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 419 DecodeZeroMoveLowMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument 426 DecodeScalarMoveMask(MVT VT, bool IsLoad, SmallVectorImpl<int> &Mask) argument [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 106 EVT VT = Op.getValueType(); local 113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); 115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1)); 119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); 121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), 124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), 127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), 130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), 133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), 136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, O 154 EVT VT = Op.getValueType(); local 167 EVT VT = Op.getValueType(); local 184 EVT VT = Op.getValueType(); local [all...] |
H A D | R600ISelLowering.cpp | 277 EVT VT = Op.getValueType(); local 284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT); 288 return LowerImplicitParameter(DAG, VT, DL, 0); 290 return LowerImplicitParameter(DAG, VT, DL, 1); 292 return LowerImplicitParameter(DAG, VT, DL, 2); 294 return LowerImplicitParameter(DAG, VT, DL, 3); 296 return LowerImplicitParameter(DAG, VT, DL, 4); 298 return LowerImplicitParameter(DAG, VT, DL, 5); 300 return LowerImplicitParameter(DAG, VT, DL, 6); 302 return LowerImplicitParameter(DAG, VT, D 357 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, DebugLoc DL, unsigned DwordOffset) const argument 377 EVT VT = Op.getValueType(); local 390 EVT VT = Op.getValueType(); local [all...] |
H A D | SIISelLowering.cpp | 252 EVT SITargetLowering::getSetCCResultType(EVT VT) const 272 EVT VT = Op.getValueType(); local 276 AMDGPU::VGPR0, VT); 334 EVT VT = Op.getValueType(); local 351 unsigned TypeDwordWidth = VT.getSizeInBits() / 32; 370 VT)); 381 EVT VT = Op.getValueType(); local 385 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); 396 EVT VT = N->getValueType(0); local 408 && VT [all...] |
H A D | AMDILISelLowering.cpp | 106 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x]; local 110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); 111 setOperationAction(ISD::SUBE, VT, Expand); 112 setOperationAction(ISD::SUBC, VT, Expand); 113 setOperationAction(ISD::ADDE, VT, Expand); 114 setOperationAction(ISD::ADDC, VT, Expand); 115 setOperationAction(ISD::BRCOND, VT, Custom); 116 setOperationAction(ISD::BR_JT, VT, Expand); 117 setOperationAction(ISD::BRIND, VT, Expand); 119 setOperationAction(ISD::SREM, VT, Expan 127 MVT::SimpleValueType VT = (MVT::SimpleValueType)FloatTypes[x]; local 142 MVT::SimpleValueType VT = (MVT::SimpleValueType)IntTypes[x]; local 163 MVT::SimpleValueType VT = (MVT::SimpleValueType)VectorTypes[ii]; local 356 EVT VT = Op.getValueType(); local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.h | 41 bool operator==(EVT VT) const { 42 return !(*this != VT); 44 bool operator!=(EVT VT) const { 45 if (V.SimpleTy != VT.V.SimpleTy) 48 return LLVMTy != VT.LLVMTy; 69 /// length, where each element is of type VT. 70 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements) { argument 71 MVT M = MVT::getVectorVT(VT.V, NumElements); 74 return getExtendedVectorVT(Context, VT, NumElements); 88 "Simple vector VT no [all...] |
H A D | BasicTTIImpl.h | 156 EVT VT = getTLI()->getValueType(Ty); local 157 return getTLI()->isTypeLegal(VT); 194 EVT VT = TLI->getValueType(Ty); local 195 return TLI->isTypeLegal(VT) && 196 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
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H A D | CallingConvLower.h | 165 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT) argument 166 : VReg(VReg), PReg(PReg), VT(VT) {} 169 MVT VT; member in struct:llvm::ForwardedRegister 314 void AnalyzeCallResult(MVT VT, CCAssignFn Fn); 487 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
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/external/llvm/lib/Target/X86/ |
H A D | X86AsmPrinter.cpp | 213 MVT::SimpleValueType VT = (strcmp(Modifier+6,"64") == 0) ? local 216 Reg = getX86SubSuperRegister(Reg, VT);
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H A D | X86RegisterInfo.cpp | 584 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT, argument 586 switch (VT) { 587 default: llvm_unreachable("Unexpected VT");
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