/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 246 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { argument 247 addRegisterClass(Ty, RC); 295 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { argument 296 addRegisterClass(Ty, RC); 2749 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 2776 unsigned VR2 = RegInfo.createVirtualRegister(RC); 2782 unsigned VR1 = RegInfo.createVirtualRegister(RC); 2814 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 2843 unsigned RD1 = RegInfo.createVirtualRegister(RC); 2849 unsigned RD2 = RegInfo.createVirtualRegister(RC); 3203 const TargetRegisterClass *RC = &Mips::MSA128WRegClass; local 3232 const TargetRegisterClass *RC = &Mips::MSA128DRegClass; local [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.h | 103 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
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H A D | AMDGPUISelLowering.h | 204 const TargetRegisterClass *RC,
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/external/llvm/utils/TableGen/ |
H A D | DAGISelMatcherGen.cpp | 31 for (const auto &RC : T.getRegBank().getRegClasses()) { 32 if (!RC.contains(Reg)) 37 VT = RC.getValueTypeNum(0); 42 assert(VT == RC.getValueTypeNum(0));
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/external/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
H A D | SkPdfAppearanceCharacteristicsDictionary_autogen.cpp | 59 SkString SkPdfAppearanceCharacteristicsDictionary::RC(SkPdfNativeDoc* doc) { function in class:SkPdfAppearanceCharacteristicsDictionary 60 SkPdfNativeObject* ret = get("RC", ""); 68 return get("RC", "") != NULL;
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/external/llvm/lib/CodeGen/ |
H A D | MachineLICM.cpp | 890 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 892 RegClassWeight W = TRI->getRegClassWeight(RC); 906 const int *PS = TRI->getRegClassPressureSets(RC); 1256 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF); local 1258 unsigned Reg = MRI->createVirtualRegister(RC);
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H A D | MachineCSE.cpp | 145 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC, 155 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 156 if (!MRI->constrainRegClass(SrcReg, RC))
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H A D | PHIElimination.cpp | 263 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); local 264 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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H A D | StackMaps.cpp | 136 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg()); local 147 Location(Location::Register, RC->getSize(), RegNo, Offset));
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H A D | MachineBasicBlock.cpp | 343 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { argument 346 assert(RC && "Register class is required"); 360 if (!MRI.constrainRegClass(VirtReg, RC)) 366 unsigned VirtReg = MRI.createVirtualRegister(RC);
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H A D | RegAllocGreedy.cpp | 541 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); local 543 (Size / SlotIndex::InstrDist) > (2 * RC.getNumRegs()); 558 Prio |= RC.AllocationPriority << 24; 841 // Check of any registers in RC are below CostPerUseLimit. 842 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg); local 843 unsigned MinCost = RegClassInfo.getMinCost(RC); 845 DEBUG(dbgs() << TRI->getRegClassName(RC) << " minimum cost = " << MinCost 853 OrderLimit = RegClassInfo.getLastCostChange(RC);
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H A D | PeepholeOptimizer.cpp | 429 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); local 443 unsigned NewVR = MRI->createVirtualRegister(RC);
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H A D | RegAllocPBQP.cpp | 707 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg); local 708 PReg = RC.getRawAllocationOrder(MF).front();
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandCondsets.cpp | 655 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); local 656 switch (RC->getSize()) { 1151 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg); local 1152 if (RC == &Hexagon::IntRegsRegClass) { 1156 if (RC == &Hexagon::DoubleRegsRegClass) {
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/external/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 1416 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); 1418 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment(); 1420 SpillSlotOffset -= RC->getSize(); 1422 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset); 1424 MFI->ensureMaxAlignment(RC->getAlignment()); 1462 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1464 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC, 1494 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1495 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGRRList.cpp | 291 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); local 292 RegClass = RC->getID(); 300 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); local 301 RegClass = RC->getID(); 308 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); local 309 RegClass = RC->getID(); 1450 const TargetRegisterClass *RC = local 1452 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); 1454 // If cross copy register class is the same as RC, then it must be possible 1456 // If cross copy register class is not the same as RC, the [all...] |
H A D | ScheduleDAGSDNodes.cpp | 133 const TargetRegisterClass *RC = local 135 Cost = RC->getCopyCost();
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 2659 const TargetRegisterClass *RC; local 2667 RC = &PPC::GPRCRegClass; 2670 RC = &PPC::F4RCRegClass; 2674 RC = &PPC::VSFRCRegClass; 2676 RC = &PPC::F8RCRegClass; 2681 RC = &PPC::VRRCRegClass; 2684 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass; 2688 RC = &PPC::VSHRCRegClass; 2691 RC = &PPC::QFRCRegClass; 2694 RC 3164 const TargetRegisterClass *RC; local 7952 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass local 8065 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); local 8212 const TargetRegisterClass *RC = local 8668 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass local [all...] |
/external/clang/lib/Sema/ |
H A D | Sema.cpp | 1186 RawComment RC(SourceMgr, Comment, false, 1188 if (RC.isAlmostTrailingComment()) { 1192 switch (RC.getKind()) { 1206 Context.addComment(RC);
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineFunction.h | 328 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 999 const TargetRegisterClass *RC = &AArch64::GPR64RegClass; local 1000 int FI = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false);
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/external/clang/include/clang/AST/ |
H A D | ASTContext.h | 577 void setRaw(const RawComment *RC) { argument 578 Data.setPointer(RC); 614 void addComment(const RawComment &RC) { argument 616 !SourceMgr.isInSystemHeader(RC.getSourceRange().getBegin())); 617 Comments.addComment(RC, BumpAlloc);
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/external/llvm/lib/Target/R600/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 486 unsigned RC = getRegClass(IsVgpr, RegWidth); local 487 if (RegIndexInClass > TRC->getRegClass(RC).getNumRegs()) 489 RegNo = TRC->getRegClass(RC).getRegister(RegIndexInClass);
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/external/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 343 const MCRegisterClass *RC) const;
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/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 70 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { argument 73 return *(RegInfo->getRegClass(RC).begin() + RegNo);
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