| /external/libedit/src/ |
| H A D | keymacro.c | 628 #define ADDC(c) \ macro
644 ADDC(sep[0]);
647 ADDC('^');
648 ADDC('@');
665 ADDC(sep[1]);
667 ADDC('\0');
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 198 /// like ADDC/SUBC, which indicate the carry result is always false.
205 ADDC, SUBC, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 1057 case ISD::ADDC:
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 262 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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| H A D | MipsSEISelDAGToDAG.cpp | 235 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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| H A D | MipsSEISelLowering.cpp | 393 // ADDENode's second operand must be a flag output of an ADDC node in order
397 if (ADDCNode->getOpcode() != ISD::ADDC)
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| /external/pcre/dist/sljit/ |
| H A D | sljitNativeSPARC_32.c | 100 return push_inst(compiler, ADDC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst) | (flags & SET_FLAGS));
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| H A D | sljitNativePPC_32.c | 119 return push_inst(compiler, ADDC | OERC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2));
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| H A D | sljitNativePPC_64.c | 240 return push_inst(compiler, ADDC | OERC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2));
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| H A D | sljitNativeSPARC_common.c | 119 #define ADDC (OPC1(0x2) | OPC3(0x08)) macro
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDILISelLowering.cpp | 114 setOperationAction(ISD::ADDC, VT, Expand);
214 setOperationAction(ISD::ADDC, MVT::Other, Expand);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 210 case ISD::ADDC: return "addc";
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| H A D | LegalizeIntegerTypes.cpp | 1309 case ISD::ADDC:
1375 TLI.isOperationLegalOrCustom(ISD::ADDC,
1380 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1618 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1620 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1625 ISD::ADDC : ISD::SUBC,
1631 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1679 if (N->getOpcode() == ISD::ADDC) {
1680 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
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| H A D | DAGCombiner.cpp | 1307 case ISD::ADDC: return visitADDC(N);
1763 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1803 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
2771 APInt ADDC = ADDI->getAPIntValue(); local
2772 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2781 ADDC |= Mask;
2782 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2785 N0.getOperand(0), DAG.getConstant(ADDC, VT));
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 72 ADDC, // Add with carry enumerator in enum:llvm::ARMISD::NodeType
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| H A D | ARMISelLowering.cpp | 586 setTargetDAGCombine(ISD::ADDC);
684 setOperationAction(ISD::ADDC, MVT::i32, Custom);
1039 case ARMISD::ADDC: return "ARMISD::ADDC";
6137 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6316 case ISD::ADDC:
7863 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
7868 // ADDC | hiAdd
7873 assert(AddcNode->getOpcode() == ISD::ADDC
[all...] |
| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 126 setOperationAction(ISD::ADDC, MVT::i64, Expand);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1711 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1712 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1713 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1714 setOperationAction(ISD::ADDC, MVT::i64, Expand);
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| /external/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 71 setOperationAction(ISD::ADDC, MVT::i32, Legal);
833 SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue),
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| H A D | AMDGPUISelLowering.cpp | 338 setOperationAction(ISD::ADDC, VT, Expand);
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| H A D | R600ISelLowering.cpp | 185 setOperationAction(ISD::ADDC, VT, Expand);
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1461 setOperationAction(ISD::ADDC, MVT::i64, Custom);
2695 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2829 case ISD::ADDC:
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 95 setOperationAction(ISD::ADDC, MVT::i32, Expand);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 224 setOperationAction(ISD::ADDC, MVT::i32, Custom);
228 setOperationAction(ISD::ADDC, MVT::i64, Custom);
1457 case ISD::ADDC:
1950 case ISD::ADDC:
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 332 case ISD::ADDC:
|