Searched refs:MCID (Results 1 - 25 of 51) sorted by relevance

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/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h100 namespace MCID { namespace in namespace:llvm
214 return Flags & (1 << MCID::Variadic);
220 return Flags & (1 << MCID::HasOptionalDef);
227 return Flags & (1 << MCID::Pseudo);
232 return Flags & (1 << MCID::Return);
237 return Flags & (1 << MCID::Call);
244 return Flags & (1 << MCID::Barrier);
254 return Flags & (1 << MCID::Terminator);
262 return Flags & (1 << MCID::Branch);
268 return Flags & (1 << MCID
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/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrBuilder.h31 const MCInstrDesc &MCID = MI->getDesc(); local
33 if (MCID.mayLoad())
35 if (MCID.mayStore())
H A DSystemZInstrInfo.cpp195 const MCInstrDesc &MCID = MI->getDesc(); local
196 if ((MCID.TSFlags & Flag) &&
624 const MCInstrDesc &MCID = MI->getDesc(); local
625 return ((MCID.TSFlags & Flag) &&
1125 const MCInstrDesc &MCID = get(Opcode); local
1126 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1144 if (MCID.TSFlags & SystemZII::Has20BitOffset)
/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
32 if (!MCID)
35 if (!MCID->mayLoad())
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
58 if (!MCID)
61 if (!MCID->isBranch())
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, argument
92 unsigned IIC = MCID->getSchedClass();
125 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)
149 const MCInstrDesc *MCID local
176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); local
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H A DPPCHazardRecognizers.h33 bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots);
/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); local
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
26 unsigned Opcode = MCID.getOpcode();
43 const MCInstrDesc &MCID = MI->getDesc(); local
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
H A DThumb2SizeReduction.cpp214 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { argument
215 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
549 const MCInstrDesc &MCID = MI->getDesc(); local
550 if (MCID.hasOptionalDef() &&
551 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
698 const MCInstrDesc &MCID = MI->getDesc(); local
699 if (MCID.hasOptionalDef()) {
700 unsigned NumOps = MCID.getNumOperands();
726 unsigned NumOps = MCID.getNumOperands();
728 if (i < NumOps && MCID
762 const MCInstrDesc &MCID = MI->getDesc(); local
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H A DMLxExpansionPass.cpp187 const MCInstrDesc &MCID = MI->getDesc(); local
188 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
191 unsigned Opcode = MCID.getOpcode();
344 const MCInstrDesc &MCID = MI->getDesc(); local
352 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
362 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
H A DThumb2ITBlockPass.cpp142 const MCInstrDesc &MCID = MI->getDesc(); local
144 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h237 const MCInstrDesc &MCID) {
238 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
246 const MCInstrDesc &MCID,
248 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
259 const MCInstrDesc &MCID,
262 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
270 const MCInstrDesc &MCID,
273 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
281 const MCInstrDesc &MCID,
285 return BuildMI(BB, MII, DL, MCID, DestRe
235 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID) argument
244 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
256 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
267 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
278 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
296 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID) argument
306 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID) argument
316 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID) argument
333 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID) argument
343 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
355 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, bool IsIndirect, unsigned Reg, unsigned Offset, const MDNode *Variable, const MDNode *Expr) argument
383 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, bool IsIndirect, unsigned Reg, unsigned Offset, const MDNode *Variable, const MDNode *Expr) argument
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H A DMachineInstr.h71 const MCInstrDesc *MCID; // Instruction descriptor. member in class:llvm::MachineInstr
113 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
272 const MCInstrDesc &getDesc() const { return *MCID; }
276 int getOpcode() const { return MCID->Opcode; }
390 return hasProperty(MCID::Variadic, Type);
396 return hasProperty(MCID::HasOptionalDef, Type);
403 return hasProperty(MCID::Pseudo, Type);
407 return hasProperty(MCID::Return, Type);
411 return hasProperty(MCID::Call, Type);
418 return hasProperty(MCID
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/external/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
130 if (!MCID) {
134 unsigned idx = MCID->getSchedClass();
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
186 assert(MCID && "The scheduler must filter non-machineinstrs");
187 if (DAG->TII->isZeroCost(MCID->Opcode))
194 unsigned idx = MCID->getSchedClass();
H A DMachineInstr.cpp577 if (MCID->ImplicitDefs)
578 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
580 if (MCID->ImplicitUses)
581 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
590 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
596 if (unsigned NumOps = MCID->getNumOperands() +
597 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
609 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
677 assert(MCID
1209 const MCInstrDesc &MCID = getDesc(); local
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H A DTargetInstrInfo.cpp43 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, argument
46 if (OpNum >= MCID.getNumOperands())
49 short RegClass = MCID.OpInfo[OpNum].RegClass;
50 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
124 const MCInstrDesc &MCID = MI->getDesc(); local
125 bool HasDef = MCID.getNumDefs();
187 const MCInstrDesc &MCID = MI->getDesc(); local
188 if (!MCID.isCommutable())
192 SrcOpIdx1 = MCID.getNumDefs();
222 const MCInstrDesc &MCID local
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H A DMachineVerifier.cpp770 const MCInstrDesc &MCID = MI->getDesc(); local
771 if (MI->getNumOperands() < MCID.getNumOperands()) {
773 errs() << MCID.getNumOperands() << " operands expected, but "
814 const MCInstrDesc &MCID = MI->getDesc(); local
816 // The first MCID.NumDefs operands must be explicit register defines
817 if (MONum < MCID.getNumDefs()) {
818 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
825 } else if (MONum < MCID.getNumOperands()) {
826 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
830 !(MI->isVariadic() && MONum == MCID
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXReplaceImageHandles.cpp81 const MCInstrDesc &MCID = MI.getDesc(); local
83 if (MCID.TSFlags & NVPTXII::IsTexFlag) {
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) {
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) {
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1);
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) {
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) {
/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h153 const MCInstrDesc &MCID = MI->getDesc(); local
155 if (MCID.mayLoad())
157 if (MCID.mayStore())
/external/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp593 const MCInstrDesc &MCID = TII->get(Opc); local
596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
598 BuildMI(*Head, Head->end(), TermDL, MCID)
605 TII->getRegClass(MCID, 1, TRI, *MF));
650 const MCInstrDesc &MCID = TII->get(Opc); local
652 TII->getRegClass(MCID, 0, TRI, *MF));
655 TII->getRegClass(MCID, 1, TRI, *MF));
657 BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
H A DAArch64RegisterInfo.cpp341 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); local
343 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
346 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
/external/skia/experimental/PdfViewer/pdfparser/native/pdfapi/
H A DSkPdfMarkedContentReferenceDictionary_autogen.cpp59 int64_t SkPdfMarkedContentReferenceDictionary::MCID(SkPdfNativeDoc* doc) { function in class:SkPdfMarkedContentReferenceDictionary
60 SkPdfNativeObject* ret = get("MCID", "");
68 return get("MCID", "") != NULL;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp258 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
259 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
260 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
265 if (MCID.isCommutable())
441 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
442 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
443 NumRes = MCID.getNumDefs();
444 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
520 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); local
521 if (!MCID
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H A DInstrEmitter.cpp324 const MCInstrDesc &MCID = MIB->getDesc(); local
325 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
326 MCID.OpInfo[IIOpNum].isOptionalDef();
361 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
854 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
855 UsedRegs.append(MCID.getImplicitUses(),
856 MCID.getImplicitUses() + MCID.getNumImplicitUses());
H A DScheduleDAGSDNodes.cpp299 const MCInstrDesc &MCID = TII->get(Opc);
300 if (MCID.mayLoad())
434 const MCInstrDesc &MCID = TII->get(Opc);
435 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
436 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
441 if (MCID.isCommutable())
/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp102 const MCInstrDesc &MCID = get(Opc); local
103 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1236 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); local
1240 if (MCID.isBranch() || MCID.isCall()) {
1258 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1284 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
1296 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
1329 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1349 assert(MCID.getNumOperands() == 4 && "unexpected number of operands");
1373 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1386 if (MCID
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