/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 342 ISD::SELECT_CC, 403 // We need all the operands of SELECT_CC to have the same value type, so if 406 // SELECT_CC node. 420 assert(!"Unhandled operand type parings in SELECT_CC"); 431 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); 466 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); 472 // this SELECT_CC, s [all...] |
H A D | SIISelLowering.cpp | 56 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 59 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 60 setTargetDAGCombine(ISD::SELECT_CC); 267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 400 case ISD::SELECT_CC: {
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H A D | AMDILISelLowering.cpp | 170 setOperationAction(ISD::SELECT_CC, VT, Expand); 289 case ISD::SELECT_CC:
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/external/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.h | 29 SELECT_CC, enumerator in enum:llvm::BPFISD::__anon10714
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H A D | BPFISelLowering.cpp | 108 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 180 case ISD::SELECT_CC: 508 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); 519 case BPFISD::SELECT_CC: 520 return "BPFISD::SELECT_CC";
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 348 SELECT_CC, enumerator in enum:llvm::ISD::NodeType 541 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 60 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 62 SELECT_CC, enumerator in enum:llvm::MSP430ISD::__anon10754
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H A D | MSP430ISelLowering.cpp | 116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 198 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 985 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 1004 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 1153 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
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/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 163 setTargetDAGCombine(ISD::SELECT_CC); 590 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1168 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); 1225 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, 1233 // this SELECT_CC, so we must lower it. 1247 // Lower this unsupported SELECT_CC into a combination of two supported 1248 // SELECT_CC operations. 1249 SDValue Cond = DAG.getNode(ISD::SELECT_CC, D [all...] |
H A D | SIISelLowering.cpp | 97 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 98 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 99 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 100 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 173 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); 214 setTargetDAGCombine(ISD::SELECT_CC);
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H A D | AMDGPUISelLowering.cpp | 302 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 344 setOperationAction(ISD::SELECT_CC, VT, Expand); 383 setOperationAction(ISD::SELECT_CC, VT, Expand); 393 setTargetDAGCombine(ISD::SELECT_CC);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeFloatTypes.cpp | 102 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break; 609 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), 689 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break; 876 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1378 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; 1400 /// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1615 case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break; 1675 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), 1769 case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break; 1974 // Construct a new SELECT_CC nod [all...] |
H A D | LegalizeTypesGeneric.cpp | 545 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), 547 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0),
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H A D | SelectionDAGDumper.cpp | 201 case ISD::SELECT_CC: return "select_cc";
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H A D | LegalizeDAG.cpp | 1209 case ISD::SELECT_CC: 1212 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 1220 if (Node->getOpcode() == ISD::SELECT_CC) 3860 // illegal; expand it into a SELECT_CC. 3872 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3878 case ISD::SELECT_CC: { 3892 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be " 3900 // SELECT_CC is legal, so the condition code must not be. 3928 assert(Legalized && "Can't legalize SELECT_CC with legal condition!"); 3936 // condition code, create a new SELECT_CC nod [all...] |
H A D | LegalizeIntegerTypes.cpp | 72 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 561 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), 851 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 889 /// shared among BR_CC, SELECT_CC, and SETCC handlers. 1231 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 2522 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 2556 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
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H A D | LegalizeVectorTypes.cpp | 65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 337 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(), 585 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1735 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 2517 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
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H A D | DAGCombiner.cpp | 668 if (N.getOpcode() != ISD::SELECT_CC || 1339 case ISD::SELECT_CC: return visitSELECT_CC(N); 3920 case ISD::SELECT_CC: 4850 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) || 4851 TLI.isOperationLegal(ISD::SELECT_CC, VT)) 4852 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, 5271 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(), 7960 // The next optimizations are desirable only if SELECT_CC can be lowered. 7961 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) { 7971 return DAG.getNode(ISD::SELECT_CC, SDLo [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 838 setTargetDAGCombine(ISD::SELECT_CC); 7686 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 9149 N->getOpcode() == ISD::SELECT_CC) { 9192 N->getOperand(0).getOpcode() != ISD::SELECT_CC && 9199 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) && 9204 N->getOperand(1).getOpcode() != ISD::SELECT_CC && 9244 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3) 9257 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC || [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 141 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 143 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); 144 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand); 145 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand); 146 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 147 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1646 // Lower SELECT_CC to SETCC and SELECT. 1647 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); 1648 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 1649 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 1659 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 1660 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 1664 // Hexagon has no select or setcc: expand to SELECT_CC.
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1435 // Sparc has no select or setcc: expand to SELECT_CC. 1455 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1456 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 1457 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 1458 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); 1470 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 2806 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, 2844 default: llvm_unreachable("Unknown SELECT_CC!"); 2911 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 177 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 181 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 186 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 224 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
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H A D | MipsISelLowering.cpp | 259 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 260 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 307 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 308 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 844 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 140 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 141 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 142 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 143 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 181 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); 287 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); 356 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand); 389 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand); 543 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand); 663 setOperationAction(ISD::SELECT_CC, V [all...] |