/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 105 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 108 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 110 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 112 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 114 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 116 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 118 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 120 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 122 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 124 { ISD::SINT_TO_FP, MV [all...] |
H A D | ARMISelLowering.cpp | 109 setOperationAction(ISD::SINT_TO_FP, VT, Custom); 114 setOperationAction(ISD::SINT_TO_FP, VT, Expand); 528 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 532 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 618 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 3835 case ISD::SINT_TO_FP: 3837 Opc = ISD::SINT_TO_FP; 3855 if (Op.getOpcode() == ISD::SINT_TO_FP) 5961 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); 5962 Y = DAG.getNode(ISD::SINT_TO_FP, d [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 473 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 474 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 475 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 476 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 482 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 483 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 }, 484 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 485 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 519 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 520 { ISD::SINT_TO_FP, MV [all...] |
H A D | X86ISelLowering.cpp | 177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 211 setOperationAction(ISD::SINT_TO_FP , MV [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 192 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 194 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 200 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 201 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, 202 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, 208 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, 209 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 214 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 215 { ISD::SINT_TO_FP, MV [all...] |
H A D | AArch64ISelLowering.cpp | 192 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 193 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 194 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); 478 setTargetDAGCombine(ISD::SINT_TO_FP); 548 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); 557 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote); 559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote); 562 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote); 564 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote); 567 setOperationAction(ISD::SINT_TO_FP, MV [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 384 SINT_TO_FP, enumerator in enum:llvm::ISD::NodeType
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 329 case ISD::SINT_TO_FP: 370 case ISD::SINT_TO_FP: 933 // Make sure that the SINT_TO_FP and SRL instructions are available. 934 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || 960 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); 962 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
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H A D | SelectionDAGDumper.cpp | 238 case ISD::SINT_TO_FP: return "sint_to_fp";
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H A D | LegalizeDAG.cpp | 1192 case ISD::SINT_TO_FP: 2472 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2506 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); 2515 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); 2558 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2607 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2623 // If the target supports SINT_TO_FP of this type, use it. 2624 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2625 OpToUse = ISD::SINT_TO_FP; 3036 case ISD::SINT_TO_FP [all...] |
H A D | LegalizeFloatTypes.cpp | 103 case ISD::SINT_TO_FP: 637 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; 914 case ISD::SINT_TO_FP: 1279 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; 1282 // First do an SINT_TO_FP, whether the original was signed or unsigned. 1291 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); 1311 // Unsigned - fix up the SINT_TO_FP value just calculated. 1771 case ISD::SINT_TO_FP:
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H A D | LegalizeVectorTypes.cpp | 96 case ISD::SINT_TO_FP: 432 case ISD::SINT_TO_FP: 637 case ISD::SINT_TO_FP: 1317 case ISD::SINT_TO_FP: 1788 case ISD::SINT_TO_FP: 2640 case ISD::SINT_TO_FP:
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H A D | FastISel.cpp | 243 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, 1560 return selectCast(I, ISD::SINT_TO_FP);
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H A D | LegalizeIntegerTypes.cpp | 854 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 2524 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 2738 "Don't know how to expand this SINT_TO_FP!"); 2847 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2849 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
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H A D | DAGCombiner.cpp | 1356 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 7949 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); 7951 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 7953 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 8004 // but SINT_TO_FP is legal on this target, try to convert. 8006 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 8007 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 8009 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); 8035 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) 8040 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; [all...] |
H A D | SelectionDAG.cpp | 2752 case ISD::SINT_TO_FP: { 2756 Opcode==ISD::SINT_TO_FP, 2865 case ISD::SINT_TO_FP: {
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H A D | SelectionDAGBuilder.cpp | 3035 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N)); 3942 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3958 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 527 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia); 530 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
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H A D | R600ISelLowering.cpp | 414 ConversionOp = ISD::SINT_TO_FP;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1454 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); 1459 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); 1464 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); 1469 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); 1474 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal); 1487 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 299 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 328 setOperationAction(ISD::SINT_TO_FP, VT, Expand); 618 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 1550 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; 2153 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); 106 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, 112 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); 256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 499 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 608 setOperationAction(ISD::SINT_TO_FP, MV [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1422 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 1424 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 2798 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, 3205 case ISD::SINT_TO_FP: 3212 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
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/external/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1559 case SIToFP: return ISD::SINT_TO_FP;
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 281 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); 1833 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
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