cddc3e03e4ec99c0268c03a126195173e519ed58 |
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04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229 http://b/26987366 (cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383) Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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4c5e43da7792f75567b693105cc53e3f1992ad98 |
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08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350 Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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ebe69fe11e48d322045d5949c83283927a0d790b |
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23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699. Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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37ed9c199ca639565f6ce88105f9e39e898d82d0 |
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01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494. Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712). Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a. Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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ef8c4ca252f1289ca8d0a1e6cfd96ca17fe3c5a8 |
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07-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove getEHExceptionRegister and getEHHandlerRegister. They haven't been used for a long time. Patch by MathOnNapkins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753d |
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17-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Implement base pointer and stack realignment This builds on some frame-lowering code that has existed since 2005 (r24224) but was disabled in 2008 (r48188) because it needed base pointer support to function correctly. This implementation follows the strategy suggested by Dale Johannesen in r48188 where the following comment was added: This does not currently work, because the delta between old and new stack pointers is added to offsets that reference incoming parameters after the prolog is generated, and the code that does that doesn't handle a variable delta. You don't want to do that anyway; a better approach is to reserve another register that retains to the incoming stack pointer, and reference parameters relative to that. And now we do exactly that. If we don't need a frame pointer, then we use r31 as a base pointer. If we do need a frame pointer, then we use r30 as a base pointer. The base pointer retains the value of the stack pointer before it was decremented in the prologue. We then use the base pointer to resolve all negative frame indicies. The basic scheme follows that for base pointers in the X86 backend. We use a base pointer when we need to dynamically realign the incoming stack pointer. This currently applies only to static objects (dynamic allocas with large alignments, and base-pointer support in SjLj lowering will come in future commits). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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80ada583f3b40ffb201e54cd57c42f9518039c9e |
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07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because the internals of TargetMachine could change. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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f6f8198d85f278ff03aaf32c9db6ae0b3826395c |
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09-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use virtual base registers on PPC On PowerPC, non-vector loads and stores have r+i forms; however, in functions with large stack frames these were not being used to access slots far from the stack pointer because such slots were out of range for the signed 16-bit immediate offset field. This increases register pressure because we need a separate register for each offset (when the r+r form is used). By enabling virtual base registers, we can deal with large stack frames without unduly increasing register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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4345e8040f14781d20fd5fa2f7ee3c75fa611fa1 |
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31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfo ImmToIdxMap should be a DenseMap (not a std::map) because there is no ordering requirement. Also, we don't need a separate list of instructions for noImmForm in eliminateFrameIndex, because this list is essentially the complement of the keys in ImmToIdxMap. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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02327fefd8a4b7d9f4dc90e066ba70b1d6253c27 |
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23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup some unused reg. scavenger parameters in PPCRegisterInfo These spilling functions will eventually make use of the register scavenger, however, they'll do so by taking advantage of PEI's virtual-register-based delayed scavenging mechanism. As a result, these function parameters will not be used, and can be removed. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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7ee74a663a3b4d4ee6b55d23362f347ed1d390c2 |
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21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement builtin_{setjmp/longjmp} on PPC This implements SJLJ lowering on PPC, making the Clang functions __builtin_{setjmp/longjmp} functional on PPC platforms. The implementation strategy is similar to that on X86, with the exception that a branch-and-link variant is used to get the right jump address. Credit goes to Bill Schmidt for suggesting the use of the unconditional bcl form (instead of the regular bl instruction) to limit return-address-cache pollution. Benchmarking the speed at -O3 of: static jmp_buf env_sigill; void foo() { __builtin_longjmp(env_sigill,1); } main() { ... for (int i = 0; i < c; ++i) { if (__builtin_setjmp(env_sigill)) { goto done; } else { foo(); } done:; } ... } vs. the same code using the libc setjmp/longjmp functions on a P7 shows that this builtin implementation is ~4x faster with Altivec enabled and ~7.25x faster with Altivec disabled. This comparison is somewhat unfair because the libc version must also save/restore the VSX registers which we don't yet support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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10f7f2a222d0e83dc0c33ad506a7686190c2f7a2 |
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21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add support for spilling VRSAVE on PPC Although there is only one Altivec VRSAVE register, it is a member of a register class, and we need the ability to spill it. Because this register is normally callee-preserved and handled by special code this has never before been necessary. However, this capability will be required by a forthcoming commit adding SjLj support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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ce638c8248355452cb7892c9c27807a92176a7b2 |
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16-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove PPC avoidWriteAfterWrite callback As a follow-up to r158719, remove PPCRegisterInfo::avoidWriteAfterWrite. Jakob pointed out in response to r158719 that this callback is currently unused and so this has no effect (and the speedups that I thought that I had observed as a result of implementing this function must have been noise). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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1c6c61a6089fb2bef47de5ee9a5f4acc34047600 |
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14-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use frame-index scavenging for PPC register spilling Make requiresFrameIndexScavenging return true, and create virtual registers in the spilling code instead of using the register scavenger directly. This makes the target-level code simpler, and importantly, delays the scavenging until after callee-saved register processing (which will be important for later changes). Also cleans up trackLivenessAfterRegAlloc (makes it inline in the header with the other related functions). This makes it clear that it always returns true. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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7285e8d98c9a44b7efe792462188cfe713dd9641 |
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12-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC should always use the register scavenger for CR spilling This removes the -disable-ppc[32|64]-regscavenger options; the code that uses the register scavenger has been working well (and has been the default) for some time, and we don't need options to enable the old (broken) CR spilling code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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4edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4 |
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24-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR14364. This removes a const_cast hack from PPCRegisterInfo::hasReservedSpillSlot(). The proper place to save the frame index for the CR spill slot is in the PPCFunctionInfo object, not the PPCRegisterInfo object. No new test cases, as this just reimplements existing function. Existing tests such as test/CodeGen/PowerPC/crsave.ll are sufficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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700ed80d3da5e98e05ceb90e9bfb66058581a6db |
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21-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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108fb3202af6f500073cdbb7be32c25d7a273a2e |
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31-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
[PEI] Pass the frame index operand number to the eliminateFrameIndex function. Each target implementation was needlessly recomputing the index. Part of rdar://13076458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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6ffb4024d875570a01d6b8db900a0385a491403b |
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16-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Change unsigned to uint32_t to match base class declaration and other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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9d760ae5c6bc1d1482e2824efcf9cb11db1cc16f |
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12-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
This patch corrects logic in PPCFrameLowering for save and restore of nonvolatile condition register fields across calls under the SVR4 ABIs. * With the 64-bit ABI, the save location is at a fixed offset of 8 from the stack pointer. The frame pointer cannot be used to access this portion of the stack frame since the distance from the frame pointer may change with alloca calls. * With the 32-bit ABI, the save location is just below the general register save area, and is accessed via the frame pointer like the rest of the save areas. This is an optional slot, so it must only be created if any of CR2, CR3, and CR4 were modified. * For both ABIs, save/restore logic is generated only if one of the nonvolatile CR fields were modified. I also took this opportunity to clean up an extra FIXME in PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless for the 64-bit ABI, so I removed them for correctness and efficiency. Fixes PR13708 and partially also PR13623. It lets us enable exception handling on PPC64. Patch by William J. Schmidt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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fe5b65827f20a61bef817c6421f32b7e05d65caf |
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19-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Mark most PPC register classes to avoid write-after-write. For processors with the G5-like instruction-grouping scheme, this helps avoid early group termination due to a write-after-write dependency within the group. It should also help on pipelined embedded cores. On POWER7, over the test suite, this gives an average 0.5% speedup. The largest speedups are: SingleSource/Benchmarks/Stanford/Quicksort - 33% MultiSource/Applications/d/make_dparser - 21% MultiSource/Benchmarks/FreeBench/analyzer/analyzer - 12% MultiSource/Benchmarks/MiBench/telecomm-FFT/telecomm-fft - 12% Largest slowdowns: SingleSource/Benchmarks/Stanford/Bubblesort - 23% MultiSource/Benchmarks/Prolangs-C++/city/city - 21% MultiSource/Benchmarks/BitBench/uuencode/uuencode - 16% MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode - 13% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 |
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08-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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6a8c7bf8e72338e55f0f9583e1828f62da165d4a |
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23-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch fixes a problem which arose when using the Post-RA scheduler on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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e46137f498fa81a088f13d24c79242eed3ff45a7 |
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06-Mar-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Convert PowerPC to register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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015f228861ef9b337366f92f637d4e8d624bb006 |
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04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers in callee saved register tables to reduce size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
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18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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d21e930eac3d99dd77ee33ea5826700b4bc97ae8 |
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06-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
add RESTORE_CR and support CR unspills git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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768c65f677af3f05c2e94982043f90a1bfaceda5 |
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22-Nov-2011 |
Hal Finkel <hfinkel@anl.gov> |
add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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966aeb5788c242cfaca35c56c0ddc0ff778d4376 |
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25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Refactor PPC target to separate MC routines from Target routines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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0e6a052331f674dd70e28af41f654a7874405eab |
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18-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 |
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27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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6e032942cf58d1c41f88609a1cec74eb74940ecd |
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30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use the dwarf->llvm mapping to print register names in the cfi directives. Fixes PR9826. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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94c5ae08750f314bc3cf1bf882b686244a3927d9 |
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28-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move more PEI-related hooks to TFI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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d9e3385ced2dc887e2fe8e1c071bd2611e4d3ede |
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19-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move getInitialFrameState() to TargetFrameInfo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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d0c38176690e9602a93a20a43f1bd084564a8116 |
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18-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move hasFP() and few related hooks to TargetFrameInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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33464912237efaa0ed7060829e66b59055bdd48b |
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15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341a |
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27-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify eliminateFrameIndex() interface back down now that PEI doesn't need to try to re-use scavenged frame index reference registers. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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6f07bd6ae8c2b11e78f351d7751d1e9b32f38a75 |
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02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
cleanup git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630 |
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09-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the Value argument to eliminateFrameIndex to a type-tagged value. This is preparatory to having PEI's scavenged frame index value reuse logic properly distinguish types of frame values (e.g., whether the value is stack-pointer relative or frame-pointer relative). No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
b9c2fd964ee7dd7823ac71db8443055e4d0f1c15 |
|
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Make the MachineFunction argument of getFrameRegister const. This also fixes a build error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
b58f498f7502e7e1833decbbbb4df771367c7341 |
|
07-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Add register-reuse to frame-index register scavenging. When a target uses a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
2cfd52c507bd5790457a171eb9bcb39019cc6860 |
|
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Give getPointerRegClass() a "kind" value so that targets can support multiple different pointer register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
ffd0200abfd63177257f949a3674b91dcf87bf23 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Implement the SVR4 ABI for PowerPC. Implement LowerFORMAL_ARGUMENTS_SVR4(). Implement LowerCALL_SVR4(). Add support for split arguments. Implement by value parameter passing for aggregates. Add support for variable argument lists. Create the spill area for argument registers of variable argument functions no longer at a fixed offset. Make sure callee saved registers are spilled to the correct stack offsets. Change allocation order of non-volatile floating-point registers. Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls. Add support for variable argument calls with Vector arguments. Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers. Stop creating illegal i8 values in LowerVASTART(). Add memory access width hints. Make sure to reserve space on the stack for the frame pointer. When using the SVR4 ABI, reserve r13 for the Small Data Area pointer. Assure that the frame pointer is spilled to the correct location on the stack. Some FP registers were not marked as volatile. Make sure the i64 words from a long double are passed either both in registers or both on the stack. Only put integer arguments in registers which are not marked with the inreg flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
770bcc7b15adbc978800db70dbb1c3c22913b52c |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
ca1267c02b025cc719190b05f9e1a5d174a9caf7 |
|
31-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
7194aaf738a1b89441635340403f1c5b06ae18ef |
|
03-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
This is the initial check-in for adding register scavenging to PPC. (Currently, PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
43dbe05279b753aabda571d9c83eaeb36987001a |
|
07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
f6372aa1cc568df19da7c5023e83c75aa9404a07 |
|
01-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more instruction creation methods from RegisterInfo into InstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
73944fb22270697e75408cba52cca276be371a1f |
|
08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
refactor some code to avoid overloading the name 'usesLR' in different places to mean different things. Document what the one in PPCFunctionInfo means and when it is valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
8c24e74b02bea8681eac497075e6c27ef15aa2ea |
|
05-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added canFoldMemoryOperand for PPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
d64b5c82b97ad1b74eb9fd2f23257a7899b0c307 |
|
05-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether the stored register is killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
aee4af68ae2016afc5b4ec0c430e539c5810a766 |
|
02-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove redundant foldMemoryOperand variants and other code clean up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
e62f97c094dba44e4c259d20135167fa91912eea |
|
01-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
b97aec663b1591e71c9ddee6dbb327d1b827eda5 |
|
13-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Add parameter to getDwarfRegNum to permit targets to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
f191c80cd79ee35e47b5a4feed98d687782dfe85 |
|
11-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use TableGen to emit information for dwarf register numbers. This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
f0a0cddbcda344a90b7217b744c78dccec71851c |
|
19-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
58184e6878fdab651bc7c9a59dab2687ca82ede2 |
|
18-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
66f0f640820b61cf9db814b6d187bae9faf7279c |
|
05-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added a few target hooks to generate load / store instructions from / to any address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
9efce638d307b2c71bd7f0258d47501661434c27 |
|
26-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow copyRegToReg to emit cross register classes copies. Tested with "make check"! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
35b35c5c320a71e4611fe2101452da685f8eeda0 |
|
30-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
64d80e3387f328d21cd9cc06464b5de7861e3f27 |
|
19-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
2365f51ed03afe6993bae962fdc2e5a956a64cd5 |
|
14-Jul-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Long live the exception handling! This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
97de9138217d6f76f25100df272ec1a3c4d31aad |
|
01-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
eliminateFrameIndex() change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
bf2c8b3c96f5c885095a10b0fcb29438f92d73c2 |
|
20-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added MRegisterInfo hook to re-materialize an instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
28b3c45109153bc50d3d9e97dccb25ffd043fa50 |
|
06-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Minor interface change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
5e6df4647e15c50daea9a8a4e7f4f417a266335c |
|
28-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
PEI now passes a RegScavenger ptr to eliminateFrameIndex. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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d313a9b1484c52e3f784de5064ce86bdbd9b26dc |
|
27-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Duplicate use of LR, take 2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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3d3d6275134f3c6d35a97a028a8556fd2e62243a |
|
27-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrapping to infinite loop: PPCMachineFunctionInfo.h updated: 1.2 -> 1.3 PPCRegisterInfo.cpp updated: 1.110 -> 1.111 PPCRegisterInfo.h updated: 1.28 -> 1.29 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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2a27a7598b90359696e31cb665914206f369d1f0 |
|
23-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Don't spill LR as a callee saved register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34533 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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62819f31440fe1b1415473a89b8683b5b690d5fa |
|
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support to provide exception and selector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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b371f457b0ea4a652a9f526ba4375c80ae542252 |
|
19-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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a284cbf667e11660840dc7bae3ee9eeaa3c7cbd2 |
|
19-Feb-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1207: Revert patches that caused the problem. Evan, please investigate and reapply when you've discovered the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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eceada67286f0d8081c23aedd242f4deeffa85ad |
|
17-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added getReservedRegs(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
99403b6964aead64c1039a8f4007437ef96dfd88 |
|
25-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Tell PEI that PPC will handle stack frame rounding itself. - Do not round up to max. alignment of stack object if it is > stack alignment. It will have to be handled with dynamic aligning code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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5e73d5bd2e98afda12fa69a7ea83050c69be0d34 |
|
24-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves by value so that clean up is less confusing (these vectors tend to be small.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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dc77540d9506dc151d79b94bae88bd841880ef37 |
|
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
hasFP() is now a virtual method of MRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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c2b861da18c54a4252fecba866341e1513fa18cc |
|
02-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix naming inconsistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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51fe9d9aa432cbde6497cad4ea5c8f0276c67b82 |
|
06-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Make it easier for gdb to find the return address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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c0f64ffab93d11fb27a3b8a0707b77400918a20e |
|
28-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead of opcode and number of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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2f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173 |
|
16-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
This is a general clean up of the PowerPC ABI. Address several problems and bugs including making sure that the TOS links back to the previous frame, that the maximum call frame size is not included twice when using frame pointers, no longer growing the frame on calls, double storing of SP and a cleaner/faster dynamic alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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7ce45783531cfa81bfd7be561ea7e4738e8c6ca8 |
|
14-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Matches MachineInstr changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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804e06704261f233111913a047ef7f7dec1b8725 |
|
11-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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0f3ac8d8d4ce23eb2ae6f9d850f389250874eea5 |
|
18-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
|
369503f8412bba4a0138074c97107c09cc4513e0 |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Move some knowledge about registers out of the code emitter into the register info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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4188699f80c233a20b6ddc61570a8a8c1804cb85 |
|
07-Apr-2006 |
Jim Laskey <jlaskey@mac.com> |
Foundation for call frame information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27491 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4 |
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28-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Expose base register for DwarfWriter. Refactor code accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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f1d78e83356a412e525c30ac90dabf090a8cfc99 |
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23-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Add support to locate local variables in frames (early version.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26994 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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408396014742a05cad1c91949d2226169e3f9d80 |
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02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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21e463b2bf864671a87ebe386cb100ef9349a540 |
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16-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
More PPC32 -> PPC changes, as well as merging some classes that were redundant after the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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2668959b8879097db368aec7d76c455260abc75b |
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15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PowerPC*.h to PPC*.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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4c7b43b43fdf943c7298718e15ab5d6dfe345be7 |
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15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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0ffb1a56ff8439604556afd09ee0774655d7197c |
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30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
these methods get extra args git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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6a78c2157ad1ca9608ebdb33a8cc9f86f4a74f2c |
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17-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Implement hook for ppc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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f38df04c3a0c2aa766fa50b254d2d0fc743f8152 |
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09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a problem that Nate noticed, where spill code was not getting coallesced with copies, leading to code like this: lwz r4, 380(r1) or r10, r4, r4 ;; Last use of r4 By teaching the PPC backend how to fold spills into copies, we now get this code: lwz r10, 380(r1) wow. :) This reduces a testcase nate sent me from 1505 instructions to 1484. Note that this could handle FP values but doesn't currently, for reasons mentioned in the patch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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0b1e641b8217e10b04e767bd0b70933c70cc17d3 |
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19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Now that the simple isels are dead, so is this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0 |
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22-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove trailing whitespace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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f2ccb77ee9d8ab35866dae111fa36929689c7511 |
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17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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