/external/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 204 SmallVector<CCValAssign, 16> ArgLocs; local 205 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 208 for (auto &VA : ArgLocs) { 280 SmallVector<CCValAssign, 16> ArgLocs; local 281 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 310 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 311 CCValAssign &VA = ArgLocs[i];
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/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 365 SmallVector<CCValAssign, 16> ArgLocs; local 366 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 380 CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(), 403 assert(ArgLocs[ValNo].getValNo() == ValNo && 404 "ArgLocs should remain in order and only hold varargs args"); 405 unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 280 SmallVectorImpl<CCValAssign> &ArgLocs, 334 SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal; 437 SmallVector<CCValAssign, 16> ArgLocs; local 438 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 440 AnalyzeArguments(CCInfo, ArgLocs, Ins); 448 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 449 CCValAssign &VA = ArgLocs[i]; 584 SmallVector<CCValAssign, 16> ArgLocs; local 585 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 587 AnalyzeArguments(CCInfo, ArgLocs, Out 279 AnalyzeArguments(CCState &State, SmallVectorImpl<CCValAssign> &ArgLocs, const SmallVectorImpl<ArgT> &Args) argument [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 1645 SmallVector<CCValAssign, 16> ArgLocs; local 1646 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1658 CCValAssign &VA = ArgLocs[i]; 1697 unsigned ValBase = ArgLocs[In.getOrigArgIndex()].getLocMemOffset();
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H A D | SIISelLowering.cpp | 637 SmallVector<CCValAssign, 16> ArgLocs; local 638 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 685 CCValAssign &VA = ArgLocs[ArgIdx++]; 742 Reg = ArgLocs[ArgIdx++].getLocReg();
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/external/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 1077 SmallVector<CCValAssign, 16> ArgLocs; local 1078 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context); 1089 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1090 CCValAssign &VA = ArgLocs[i];
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H A D | MipsISelLowering.cpp | 2592 SmallVector<CCValAssign, 16> ArgLocs; local 2594 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2639 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2641 CCValAssign &VA = ArgLocs[i]; 2958 SmallVector<CCValAssign, 16> ArgLocs; local 2959 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 2976 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2977 CCValAssign &VA = ArgLocs[i]; 3065 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 1273 SmallVector<CCValAssign, 16> ArgLocs; local 1274 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context); 1283 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { 1284 CCValAssign &VA = ArgLocs[I]; 1321 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { 1322 CCValAssign &VA = ArgLocs[I];
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H A D | PPCISelLowering.cpp | 2835 SmallVector<CCValAssign, 16> ArgLocs; local 2836 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 2845 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2846 CCValAssign &VA = ArgLocs[i]; 4536 SmallVector<CCValAssign, 16> ArgLocs; local 4537 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 4618 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 4621 CCValAssign &VA = ArgLocs[i];
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 877 SmallVector<CCValAssign, 16> ArgLocs; local 878 SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 883 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { 885 CCValAssign &VA = ArgLocs[I]; 990 SmallVectorImpl<CCValAssign> &ArgLocs) { 993 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { 994 CCValAssign &VA = ArgLocs[I]; 1029 SmallVector<CCValAssign, 16> ArgLocs; local 1030 SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 1035 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs)) 989 canUseSiblingCall(const CCState &ArgCCInfo, SmallVectorImpl<CCValAssign> &ArgLocs) argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1132 SmallVector<CCValAssign, 16> ArgLocs; local 1133 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1160 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1161 CCValAssign &VA = ArgLocs[i]; 1298 SmallVector<CCValAssign, 16> ArgLocs; local 1299 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1323 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1325 CCValAssign &VA = ArgLocs[i];
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/external/clang/lib/Sema/ |
H A D | SemaTemplateInstantiateDecl.cpp | 2520 SmallVector<TemplateArgumentLoc, 4> ArgLocs; local 2522 ArgLocs.push_back(Loc.getArgLoc(I)); 2523 if (SemaRef.Subst(ArgLocs.data(), ArgLocs.size(),
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1885 SmallVector<CCValAssign, 16> ArgLocs; local 1886 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context); 1892 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1893 CCValAssign &VA = ArgLocs[i]; 1907 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) 1942 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1943 CCValAssign &VA = ArgLocs[i]; 1991 CCValAssign &NextVA = ArgLocs[++i];
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H A D | ARMISelLowering.cpp | 1596 SmallVector<CCValAssign, 16> ArgLocs; local 1597 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1624 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1627 CCValAssign &VA = ArgLocs[i]; 1659 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1661 VA = ArgLocs[++i]; // skip ahead to next loc 1664 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1672 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 2167 SmallVector<CCValAssign, 16> ArgLocs; local 2168 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs, 3072 SmallVector<CCValAssign, 16> ArgLocs; local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 677 SmallVector<CCValAssign, 16> ArgLocs; local 678 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 696 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 697 CCValAssign &VA = ArgLocs[i]; 719 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 720 CCValAssign &VA = ArgLocs[i]; 1040 SmallVector<CCValAssign, 16> ArgLocs; local 1041 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1056 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1057 CCValAssign &VA = ArgLocs[ [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 397 SmallVector<CCValAssign, 16> ArgLocs; local 398 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 406 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) { 407 CCValAssign &VA = ArgLocs[i]; 431 CCValAssign &NextVA = ArgLocs[++i]; 603 SmallVector<CCValAssign, 16> ArgLocs; local 604 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 611 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 612 CCValAssign &VA = ArgLocs[i]; 752 SmallVector<CCValAssign, 16> ArgLocs; local 1064 fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, ArrayRef<ISD::OutputArg> Outs) argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 2930 SmallVector<CCValAssign, 16> ArgLocs; local 2931 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, CLI.RetTy->getContext()); 2949 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2950 CCValAssign const &VA = ArgLocs[i];
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H A D | X86ISelLowering.cpp | 2679 SmallVector<CCValAssign, 16> ArgLocs; local 2680 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext()); 2690 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2691 CCValAssign &VA = ArgLocs[i]; 2768 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3115 SmallVector<CCValAssign, 16> ArgLocs; local 3116 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext()); 3155 if (!ArgLocs.back().isMemLoc()) 3158 if (ArgLocs.back().getLocMemOffset() != 0) 3180 for (unsigned i = 0, e = ArgLocs 3798 SmallVector<CCValAssign, 16> ArgLocs; local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2907 SmallVector<CCValAssign, 16> ArgLocs; local 2908 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context); 2920 for (CCValAssign &VA : ArgLocs) {
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H A D | AArch64ISelLowering.cpp | 2373 SmallVector<CCValAssign, 16> ArgLocs; local 2374 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 2408 assert(ArgLocs.size() == Ins.size()); 2410 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2411 CCValAssign &VA = ArgLocs[i]; 2752 SmallVector<CCValAssign, 16> ArgLocs; local 2753 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs, 2757 for (const CCValAssign &ArgLoc : ArgLocs) 2796 SmallVector<CCValAssign, 16> ArgLocs; 2797 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs, 2894 SmallVector<CCValAssign, 16> ArgLocs; local [all...] |