| /external/llvm/lib/Target/X86/InstPrinter/ |
| H A D | X86ATTInstPrinter.cpp | 190 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); local
204 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
211 if (IndexReg.getReg() || BaseReg.getReg()) {
216 if (IndexReg.getReg()) {
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| H A D | X86IntelInstPrinter.cpp | 161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); local
179 if (IndexReg.getReg()) {
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
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| /external/llvm/lib/Target/X86/ |
| H A D | X86AsmPrinter.cpp | 246 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); local
256 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
276 assert(IndexReg.getReg() != X86::ESP &&
283 if (IndexReg.getReg()) {
312 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); local
330 if (IndexReg.getReg()) {
343 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| H A D | X86InstrBuilder.h | 49 unsigned IndexReg; member in struct:llvm::X86AddressMode
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
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| H A D | X86MCInstLower.cpp | 797 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; local
798 Opc = IndexReg = Displacement = SegmentReg = 0;
807 IndexReg = X86::RAX; break;
809 IndexReg = X86::RAX; break;
812 IndexReg = X86::RAX; break;
814 IndexReg = X86::RAX; break;
816 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
835 .addImm(ScaleVal).addReg(IndexReg)
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| H A D | X86FastISel.cpp | 252 /// IndexReg field of the addressing mode will be updated to match in this case.
257 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg,
596 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
615 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
677 if (AM.IndexReg == 0) {
679 AM.IndexReg = getRegForValue(V);
680 return AM.IndexReg != 0;
764 unsigned IndexReg = AM.IndexReg; local
3590 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), local
[all...] |
| H A D | X86ISelDAGToDAG.cpp | 62 SDValue IndexReg; member in struct:__anon12383::X86ISelAddressMode
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
113 << "IndexReg ";
114 if (IndexReg.getNode())
115 IndexReg.getNode()->dump();
255 Index = AM.IndexReg;
846 AM.Base_Reg = AM.IndexReg;
858 AM.IndexReg.getNode() == nullptr &&
889 !AM.IndexReg
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 56 unsigned IndexReg; member in struct:llvm::X86Operand::MemOp
121 return Mem.IndexReg;
503 Res->Mem.IndexReg = 0;
516 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
521 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
530 Res->Mem.IndexReg = IndexReg;
515 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(), void *OpDecl = nullptr) argument
|
| H A D | X86AsmParser.cpp | 266 unsigned BaseReg, IndexReg, TmpReg, Scale; member in class:__anon12355::X86AsmParser::IntelExprStateMachine
276 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
281 unsigned getIndexReg() { return IndexReg; }
384 // If we already have a BaseReg, then assume this is the IndexReg with
389 assert (!IndexReg && "BaseReg/IndexReg already set!");
390 IndexReg = TmpReg;
421 // If we already have a BaseReg, then assume this is the IndexReg with
426 assert (!IndexReg && "BaseReg/IndexReg alread
833 CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg, StringRef &ErrMsg) argument
1067 CreateMemForInlineAsm( unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, InlineAsmIdentifierInfo &Info) argument
1341 int IndexReg = SM.getIndexReg(); local
1955 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; local
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); local
69 (IndexReg.getReg() != 0 &&
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
227 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
231 (IndexReg.getReg() != 0 &&
232 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
242 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
246 (IndexReg.getReg() != 0 &&
247 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
371 const MCOperand &IndexReg local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 162 unsigned &IndexReg);
419 unsigned &IndexReg) {
441 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
442 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
506 unsigned IndexReg = 0; local
507 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
570 .addReg(Addr.Base.Reg).addReg(IndexReg);
642 unsigned IndexReg = 0; local
643 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
709 if (IndexReg)
418 PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, unsigned &IndexReg) argument
[all...] |