| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 425 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
446 Op0IsKill, Imm, VT.getSimpleVT());
458 ISDOpcode, Op0, Op0IsKill, CF);
473 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);
1299 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1316 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1679 bool /*Op0IsKill*/) {
1684 bool /*Op0IsKill*/, unsigned /*Op1*/,
1699 bool /*Op0IsKill*/, uint64_t /*Imm*/) {
1704 bool /*Op0IsKill*/,
1719 fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument
1792 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument
1813 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
1837 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
1865 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
1887 fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument
1931 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
1973 fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument
1987 fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) argument
[all...] |
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 167 unsigned Op0, bool Op0IsKill,
174 unsigned Op0, bool Op0IsKill, uint64_t imm1,
1855 unsigned Op0, bool Op0IsKill,
1869 .addReg(Op0, getKillRegState(Op0IsKill))
1876 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
173 fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t imm1, uint64_t imm2, unsigned Op3, bool Op3IsKill) argument
1853 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 116 unsigned Op0, bool Op0IsKill,
120 unsigned Op0, bool Op0IsKill);
123 unsigned Op0, bool Op0IsKill,
2294 unsigned Op0, bool Op0IsKill,
2306 Op0, Op0IsKill, Imm);
2314 unsigned Op0, bool Op0IsKill) {
2319 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2327 unsigned Op0, bool Op0IsKill,
2333 return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2292 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
2312 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill) argument
2325 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 108 unsigned Op0, bool Op0IsKill);
111 unsigned Op0, bool Op0IsKill,
115 unsigned Op0, bool Op0IsKill,
120 unsigned Op0, bool Op0IsKill,
124 unsigned Op0, bool Op0IsKill,
286 unsigned Op0, bool Op0IsKill) {
295 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
298 .addReg(Op0, Op0IsKill * RegState::Kill));
308 unsigned Op0, bool Op0IsKill,
321 .addReg(Op0, Op0IsKill * RegStat
284 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument
306 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
334 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
366 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
392 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 194 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
212 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
214 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
216 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
218 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
220 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
222 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
224 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
226 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
228 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1486 emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm) argument
3835 emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
3855 emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
3865 emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
3875 emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
3901 emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
3981 emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
4008 emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4102 emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
4129 emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
[all...] |