| /external/boringssl/src/ssl/test/runner/poly1305/ |
| H A D | poly1305_arm.s | 17 // Warning: the linker may use R11 to synthesize certain instructions. Please
21 MOVM.DB.W [R4-R11], (R13)
27 MOVW R4>>14, R11
31 ORR R5<<18, R11, R11
36 AND R11, R5, R5
47 MOVM.IA.W (R13), [R4-R11]
61 MOVM.DB.W [R4, R5, R6, R7, R8, R9, g, R11, R14], (R13)
93 MOVW R1>>20, R11
98 ORR R2<<12, R11, R1
[all...] |
| H A D | poly1305_amd64.s | 17 MOVQ SP,R11
23 MOVQ R11,32(SP)
489 MOVQ 32(SP),R11
496 MOVQ R11,SP
|
| /external/boringssl/src/ssl/test/runner/curve25519/ |
| H A D | freeze_amd64.s | 14 MOVQ SP,R11
20 MOVQ R11,0(SP)
35 MOVQ $3,R11
58 SUBQ $1,R11
62 CMOVQLT R11,R12
64 CMOVQNE R11,R12
66 CMOVQNE R11,R12
68 CMOVQNE R11,R12
70 CMOVQNE R11,R12
84 MOVQ 0(SP),R11
[all...] |
| H A D | mul_amd64.s | 16 MOVQ SP,R11
22 MOVQ R11,0(SP)
50 MOVQ DX,R11
66 ADCQ DX,R11
105 ADCQ DX,R11
117 ADCQ DX,R11
129 ADCQ DX,R11
141 SHLQ $13,R11:R10
146 ADDQ R11,R12
181 MOVQ 0(SP),R11
[all...] |
| H A D | square_amd64.s | 15 MOVQ SP,R11
21 MOVQ R11,0(SP)
40 MOVQ AX,R11
54 ADDQ AX,R11
93 ADDQ AX,R11
106 SHLQ $13,R12:R11
107 ANDQ SI,R11
108 ADDQ R10,R11
123 ADDQ R11,DX
143 MOVQ 0(SP),R11
[all...] |
| H A D | ladderstep_amd64.s | 14 MOVQ SP,R11
20 MOVQ R11,0(SP)
34 MOVQ CX,R11
39 ADDQ ยท_2P1234(SB),R11
49 SUBQ 96(DI),R11
59 MOVQ R11,112(SP)
75 MOVQ DX,R11
89 ADCQ DX,R11
128 ADCQ DX,R11
140 SHLQ $13,R11
[all...] |
| /external/llvm/test/MC/Hexagon/ |
| H A D | dcfetch.s | 12 R13:12 = VALIGNB(R11:10,R9:8,P2)
|
| /external/strace/linux/x86_64/ |
| H A D | userent.h | 7 XLAT(8*R11),
|
| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| H A D | ptrace-abi.h | 39 #define R11 48 macro
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 27 // are still a few places that R11 and R10 are hard wired.
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
|
| H A D | HexagonRegisterInfo.cpp | 61 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
|
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430RegisterInfo.cpp | 44 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
49 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
54 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
60 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
|
| /external/libunwind/src/x86_64/ |
| H A D | unwind_i.h | 50 #define R11 11 macro
|
| H A D | init.h | 60 c->dwarf.loc[R11] = REG_INIT_LOC(c, r11, R11);
|
| H A D | Gregs.c | 116 case UNW_X86_64_R11: loc = c->dwarf.loc[R11]; break;
|
| H A D | Gos-freebsd.c | 122 c->dwarf.loc[R11] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R11, 0);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 41 case R8: case R9: case R10: case R11: case R12:
52 case R8: case R9: case R10: case R11: case R12:
|
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFMCTargetDesc.cpp | 45 InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */);
|
| /external/llvm/lib/Target/BPF/ |
| H A D | BPFRegisterInfo.cpp | 40 Reserved.set(BPF::R11); // R11 is pseudo stack pointer
|
| /external/valgrind/coregrind/m_sigframe/ |
| H A D | sigframe-amd64-darwin.c | 96 SC2(__r11,R11);
124 SC2(R11,__r11);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 638 Value *R11,*R12; local
640 if (decomposeBitTestICmp(RHS, RHSCC, R11, R12, R2)) {
641 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) {
642 A = R11; D = R12;
644 A = R12; D = R11;
650 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) {
653 R11
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 684 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
721 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
757 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
793 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
794 return X86::R11;
|
| /external/libhevc/decoder/arm/ |
| H A D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 143 SUB R11,R7,R3
437 ADD R1,R1,R11 @// adjust u pointer
|
| /external/google-breakpad/src/common/android/ |
| H A D | breakpad_getcontext_unittest.cc | 124 CHECK_REG(R11);
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCAsmPrinter.cpp | 1362 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MFLR).addReg(PPC::R11));
1366 .addReg(PPC::R11)
1367 .addReg(PPC::R11)
1378 .addReg(PPC::R11));
1421 .addReg(PPC::R11)
1431 .addReg(PPC::R11));
|