| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 356 SmallVectorImpl<CCValAssign> &RVLocs,
362 std::reverse(RVLocs.begin(), RVLocs.end());
528 SmallVector<CCValAssign, 16> RVLocs; local
535 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
539 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
545 for (unsigned i = 0; i != RVLocs.size(); ++i) {
546 CCValAssign &VA = RVLocs[i];
719 SmallVector<CCValAssign, 16> RVLocs; local
720 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
355 AnalyzeReturnValues(CCState &State, SmallVectorImpl<CCValAssign> &RVLocs, const SmallVectorImpl<ArgT> &Args) argument
[all...] |
| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 394 SmallVector<CCValAssign, 16> RVLocs; local
398 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
413 for (unsigned i = 0; i != RVLocs.size(); ++i) {
414 CCValAssign &VA = RVLocs[i];
442 SmallVector<CCValAssign, 16> RVLocs; local
443 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
454 for (auto &Val : RVLocs) {
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1076 const SmallVectorImpl<CCValAssign> &RVLocs,
1081 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1082 const CCValAssign &VA = RVLocs[i];
1142 SmallVector<CCValAssign, 16> RVLocs; local
1144 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1247 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
1456 SmallVector<CCValAssign, 16> RVLocs; local
1457 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1478 SmallVector<CCValAssign, 16> RVLocs; local
1481 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1075 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2034 SmallVector<CCValAssign, 16> RVLocs; local
2035 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2039 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2042 MVT DestVT = RVLocs[0].getValVT();
2047 .addReg(RVLocs[0].getLocReg())
2048 .addReg(RVLocs[1].getLocReg()));
2050 UsedRegs.push_back(RVLocs[0].getLocReg());
2051 UsedRegs.push_back(RVLocs[1].getLocReg());
2056 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2057 MVT CopyVT = RVLocs[
2200 SmallVector<CCValAssign, 16> RVLocs; local
2311 SmallVector<CCValAssign, 16> RVLocs; local
[all...] |
| H A D | ARMISelLowering.cpp | 1431 SmallVector<CCValAssign, 16> RVLocs; local
1432 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1439 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1440 CCValAssign VA = RVLocs[i];
1458 VA = RVLocs[++i]; // skip ahead to next loc
1472 VA = RVLocs[++i]; // skip ahead to next loc
1476 VA = RVLocs[++i]; // skip ahead to next loc
2221 SmallVector<CCValAssign, 16> RVLocs; local
2222 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2268 SmallVector<CCValAssign, 16> RVLocs; local
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 213 SmallVector<CCValAssign, 16> RVLocs; local
216 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
229 i != RVLocs.size();
231 CCValAssign &VA = RVLocs[i];
251 VA = RVLocs[++i]; // skip ahead to next loc
296 SmallVector<CCValAssign, 16> RVLocs; local
299 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
313 for (unsigned i = 0; i != RVLocs.size(); ++i) {
314 CCValAssign &VA = RVLocs[i];
342 if (i+1 < RVLocs
994 SmallVector<CCValAssign, 16> RVLocs; local
1313 SmallVector<CCValAssign, 16> RVLocs; local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1393 SmallVector<CCValAssign, 16> RVLocs; local
1394 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1396 CCValAssign &VA = RVLocs[0];
1397 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1482 SmallVector<CCValAssign, 16> RVLocs; local
1483 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1485 if (RVLocs.size() > 1)
|
| H A D | PPCISelLowering.cpp | 4318 SmallVector<CCValAssign, 16> RVLocs; local
4319 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4324 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4325 CCValAssign &VA = RVLocs[i];
5771 SmallVector<CCValAssign, 16> RVLocs; local
5772 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5783 SmallVector<CCValAssign, 16> RVLocs; local
5784 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5792 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5793 CCValAssign &VA = RVLocs[
[all...] |
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1212 SmallVector<CCValAssign, 16> RVLocs; local
1213 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1217 if (RVLocs.size() != 1)
1220 MVT CopyVT = RVLocs[0].getValVT();
1230 ResultReg).addReg(RVLocs[0].getLocReg());
1231 CLI.InRegs.push_back(RVLocs[0].getLocReg());
|
| H A D | MipsISelLowering.cpp | 2824 SmallVector<CCValAssign, 16> RVLocs; local
2825 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2830 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2831 CCValAssign &VA = RVLocs[i];
2834 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2835 RVLocs[i].getLocVT(), InFlag);
3104 SmallVector<CCValAssign, 16> RVLocs; local
3105 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3138 SmallVector<CCValAssign, 16> RVLocs; local
3142 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DA
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 564 SmallVector<CCValAssign, 16> RVLocs; local
567 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
577 for (unsigned i = 0; i != RVLocs.size(); ++i) {
578 CCValAssign &VA = RVLocs[i];
622 SmallVector<CCValAssign, 16> RVLocs; local
624 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
630 for (unsigned i = 0; i != RVLocs.size(); ++i) {
632 RVLocs[i].getLocReg(),
633 RVLocs[i].getValVT(), InFlag).getValue(1);
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 3164 SmallVector<CCValAssign, 16> RVLocs; local
3165 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs,
3171 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3172 CCValAssign &VA = RVLocs[i];
3213 CLI.NumResultRegs = RVLocs.size();
|
| H A D | X86ISelLowering.cpp | 2179 SmallVector<CCValAssign, 16> RVLocs; local
2180 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2201 SmallVector<CCValAssign, 16> RVLocs; local
2202 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2213 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2214 CCValAssign &VA = RVLocs[i];
2384 SmallVector<CCValAssign, 16> RVLocs; local
2386 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2391 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2392 CCValAssign &VA = RVLocs[
3750 SmallVector<CCValAssign, 16> RVLocs; local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 3004 SmallVector<CCValAssign, 16> RVLocs; local
3005 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
3009 if (RVLocs.size() != 1)
3013 MVT CopyVT = RVLocs[0].getValVT();
3022 .addReg(RVLocs[0].getLocReg());
3023 CLI.InRegs.push_back(RVLocs[0].getLocReg());
|
| H A D | AArch64ISelLowering.cpp | 2650 SmallVector<CCValAssign, 16> RVLocs; local
2651 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2656 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2657 CCValAssign VA = RVLocs[i];
3225 SmallVector<CCValAssign, 16> RVLocs; local
3226 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3239 SmallVector<CCValAssign, 16> RVLocs; local
3240 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3247 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
3249 CCValAssign &VA = RVLocs[
[all...] |