Searched refs:SRL (Results 1 - 25 of 62) sorted by relevance

123

/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp102 // normally expanded to the sequence SRA + SRL + ADD + SRA.
136 { ISD::SRL, MVT::v16i32, 1 },
139 { ISD::SRL, MVT::v8i64, 1 },
152 { ISD::SRL, MVT::v4i32, 1 },
155 { ISD::SRL, MVT::v8i32, 1 },
158 { ISD::SRL, MVT::v2i64, 1 },
160 { ISD::SRL, MVT::v4i64, 1 },
179 { ISD::SRL, MVT::v16i8, 2 },
182 { ISD::SRL, MVT::v8i16, 2 },
185 { ISD::SRL, MV
[all...]
/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp630 if (InOp.getOpcode() == ISD::SRL &&
638 Opc = ISD::SRL;
678 InnerOp.getOpcode() == ISD::SRL &&
705 case ISD::SRL:
730 unsigned Opc = ISD::SRL;
763 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
803 TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0),
813 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1011 case ISD::SRL:
1012 // Shrink SRL b
[all...]
H A DLegalizeIntegerTypes.cpp87 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
315 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
328 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
684 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
783 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
915 case ISD::SRL:
1385 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1456 DAG.getNode(ISD::SRL, DL, NVT, InL,
1462 if (N->getOpcode() == ISD::SRL) {
1466 Lo = DAG.getNode(ISD::SRL, D
[all...]
H A DLegalizeVectorOps.cpp75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
280 case ISD::SRL:
577 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
917 !TLI.isOperationLegalOrCustom(ISD::SRL, VT) ||
977 // Make sure that the SINT_TO_FP and SRL instructions are available.
979 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
999 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
H A DLegalizeDAG.cpp416 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
828 ISD::SRL, dl, Value.getValueType(), Value,
840 ISD::SRL, dl, Value.getValueType(), Value,
1358 case ISD::SRL:
2602 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2623 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2659 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2825 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2845 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2850 Tmp2 = DAG.getNode(ISD::SRL, d
[all...]
H A DDAGCombiner.cpp1116 else if (Opc == ISD::SRL)
1387 case ISD::SRL: return visitSRL(N);
1486 case ISD::SRL:
2281 SDValue SRL = local
2282 DAG.getNode(ISD::SRL, DL, VT, SGN,
2285 SDValue ADD = DAG.getNode(ISD::ADD, DL, VT, N0, SRL);
2286 AddToWorklist(SRL.getNode());
2347 return DAG.getNode(ISD::SRL, DL, VT, N0,
2362 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
2505 N1 = DAG.getNode(ISD::SRL, D
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp179 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, local
181 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
H A DSystemZInstrInfo.cpp460 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
461 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
464 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
482 eraseIfDead(SRL, MRI);
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
H A DMSP430ISelLowering.cpp93 setOperationAction(ISD::SRL, MVT::i8, Custom);
96 setOperationAction(ISD::SRL, MVT::i16, Custom);
187 case ISD::SRL:
753 case ISD::SRL:
754 return DAG.getNode(MSP430ISD::SRL, dl,
765 if (Opc == ISD::SRL && ShiftAmount) {
970 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
1154 case MSP430ISD::SRL: return "MSP430ISD::SRL";
/external/pcre/dist/sljit/
H A DsljitNativeSPARC_32.c71 return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst));
130 FAIL_IF(push_inst(compiler, SRL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
H A DsljitNativeMIPS_32.c135 FAIL_IF(push_inst(compiler, SRL | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG));
271 return push_inst(compiler, SRL | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG);
332 EMIT_SHIFT(SRL, SRLV);
H A DsljitNativeMIPS_64.c227 FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG));
363 return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG);
427 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV);
/external/valgrind/none/tests/mips64/
H A Dshift_instructions.c10 SRA, SRAV, SRL, SRLV enumerator in enum:__anon20152
189 case SRL:
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h336 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp699 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
1946 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1947 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1996 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1997 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2107 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2109 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2148 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2150 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2241 SDValue SRL local
[all...]
H A DMipsFastISel.cpp1359 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1380 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1381 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1735 Opcode = Mips::SRL;
/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp495 } else if (Opcode == ISD::SRL) {
542 Op0.getOperand(0).getOpcode() == ISD::SRL) {
544 Op1.getOperand(0).getOpcode() != ISD::SRL) {
550 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
552 Op1.getOperand(0).getOpcode() != ISD::SRL) {
563 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
577 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
954 case ISD::SRL:
1975 case ISD::SRL:
2614 if (Val.getOpcode() == ISD::SRL
[all...]
H A DPPCISelLowering.h94 SRL, SRA, SHL,
/external/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1007 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
1008 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
1048 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1049 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
1052 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1281 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr,
1338 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1364 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1488 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1534 DAG.getNode(ISD::SRL, D
[all...]
H A DAMDGPUISelDAGToDAG.cpp505 case ISD::SRL:
1309 if (N->getOperand(0).getOpcode() == ISD::SRL) {
1329 case ISD::SRL:
/external/v8/src/mips/
H A Dconstants-mips.h400 SRL = ((0U << 3) + 2),
914 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(SRA) |
/external/v8/src/mips64/
H A Dconstants-mips64.h396 SRL = ((0U << 3) + 2),
963 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(DSRL) |
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp318 case ISD::SRL:
1460 // Handle the SRL + ANY_EXTEND case.
1462 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, Srl_imm)) {
1463 // Extend the incoming operand of the SRL to 64-bit.
1469 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL,
1474 // Use the type of SRL node.
1476 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, Srl_imm)) {
1519 // SRL Value2, ShiftImm
1528 if (N->getOpcode() != ISD::SRL)
1560 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL)
[all...]

Completed in 1689 milliseconds

123