Searched refs:ZeroReg (Results 1 - 11 of 11) sorted by relevance
| /external/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyLowerBrUnless.cpp | 109 unsigned ZeroReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); local
110 MFI.stackifyVReg(ZeroReg);
111 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::CONST_I32), ZeroReg)
117 .addReg(ZeroReg);
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 88 unsigned DstReg = 0, ZeroReg = 0; local
95 ZeroReg = Mips::ZERO;
100 ZeroReg = Mips::ZERO_64;
106 // Replace uses with ZeroReg.
120 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
123 MO.setReg(ZeroReg);
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| H A D | MipsSEInstrInfo.cpp | 83 unsigned Opc = 0, ZeroReg = 0; local
91 Opc = Mips::OR, ZeroReg = Mips::ZERO;
144 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
175 if (ZeroReg)
176 MIB.addReg(ZeroReg);
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| H A D | MipsAsmPrinter.cpp | 122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; local
123 TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2465 unsigned MulOpc, unsigned ZeroReg) {
2480 if (MI->getOperand(3).getReg() != ZeroReg)
2756 unsigned BitSize, OrrOpc, ZeroReg;
2761 ZeroReg = AArch64::WZR;
2768 ZeroReg = AArch64::XZR;
2784 .addReg(ZeroReg)
2800 unsigned SubOpc, ZeroReg;
2804 ZeroReg = AArch64::WZR;
2810 ZeroReg = AArch64::XZR;
2818 .addReg(ZeroReg)
[all...] |
| H A D | AArch64FastISel.cpp | 346 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; local
349 ResultReg).addReg(ZeroReg, getKillRegState(true));
4767 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; local
4770 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true,
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2175 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); local
2194 SrcReg = ZeroReg;
2216 emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, Instructions);
2241 emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, Instructions);
2270 emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, Instructions);
2932 unsigned ZeroReg; local
2936 ZeroReg = Mips::ZERO_64;
2939 ZeroReg = Mips::ZERO;
2950 emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Instructions);
2967 emitRRI(Mips::TEQ, RtReg, ZeroReg,
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 505 // ZeroReg = 0
508 // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
548 ZeroReg = InProlog ? (unsigned)X86::RCX
594 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
595 .addReg(ZeroReg, RegState::Undef)
596 .addReg(ZeroReg, RegState::Undef);
603 .addReg(ZeroReg);
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1238 unsigned ZeroReg; local
1241 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1243 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1248 UseMI->getOperand(UseIdx).setReg(ZeroReg);
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| H A D | PPCISelLowering.cpp | 8221 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; local
8282 if (ptrA != ZeroReg) {
8312 .addReg(ZeroReg).addReg(PtrReg);
8323 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8976 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; local
9009 if (ptrA != ZeroReg) {
9046 .addReg(ZeroReg).addReg(PtrReg);
9062 .addReg(ZeroReg).addReg(PtrReg);
9071 .addReg(ZeroReg).addReg(PtrReg);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1495 unsigned ZeroReg = fastMaterializeConstant(Zero); local
1498 .addReg(ZeroReg).addImm(1)
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