1//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "MCTargetDesc/PPCPredicates.h"
16#include "PPC.h"
17#include "PPCHazardRecognizers.h"
18#include "PPCInstrBuilder.h"
19#include "PPCMachineFunctionInfo.h"
20#include "PPCTargetMachine.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/CodeGen/LiveIntervalAnalysis.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunctionPass.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/PseudoSourceValue.h"
30#include "llvm/CodeGen/ScheduleDAG.h"
31#include "llvm/CodeGen/SlotIndexes.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCInst.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/TargetRegistry.h"
39#include "llvm/Support/raw_ostream.h"
40
41using namespace llvm;
42
43#define DEBUG_TYPE "ppc-instr-info"
44
45#define GET_INSTRMAP_INFO
46#define GET_INSTRINFO_CTOR_DTOR
47#include "PPCGenInstrInfo.inc"
48
49static cl::
50opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
51            cl::desc("Disable analysis for CTR loops"));
52
53static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
54cl::desc("Disable compare instruction optimization"), cl::Hidden);
55
56static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
57cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
58cl::Hidden);
59
60static cl::opt<bool>
61UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
62  cl::desc("Use the old (incorrect) instruction latency calculation"));
63
64// Pin the vtable to this file.
65void PPCInstrInfo::anchor() {}
66
67PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
68    : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
69      Subtarget(STI), RI(STI.getTargetMachine()) {}
70
71/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
72/// this target when scheduling the DAG.
73ScheduleHazardRecognizer *
74PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
75                                           const ScheduleDAG *DAG) const {
76  unsigned Directive =
77      static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
78  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
79      Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
80    const InstrItineraryData *II =
81        static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
82    return new ScoreboardHazardRecognizer(II, DAG);
83  }
84
85  return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
86}
87
88/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
89/// to use for this target when scheduling the DAG.
90ScheduleHazardRecognizer *
91PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
92                                                 const ScheduleDAG *DAG) const {
93  unsigned Directive =
94      DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
95
96  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
97    return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
98
99  // Most subtargets use a PPC970 recognizer.
100  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
101      Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
102    assert(DAG->TII && "No InstrInfo?");
103
104    return new PPCHazardRecognizer970(*DAG);
105  }
106
107  return new ScoreboardHazardRecognizer(II, DAG);
108}
109
110unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
111                                       const MachineInstr *MI,
112                                       unsigned *PredCost) const {
113  if (!ItinData || UseOldLatencyCalc)
114    return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
115
116  // The default implementation of getInstrLatency calls getStageLatency, but
117  // getStageLatency does not do the right thing for us. While we have
118  // itinerary, most cores are fully pipelined, and so the itineraries only
119  // express the first part of the pipeline, not every stage. Instead, we need
120  // to use the listed output operand cycle number (using operand 0 here, which
121  // is an output).
122
123  unsigned Latency = 1;
124  unsigned DefClass = MI->getDesc().getSchedClass();
125  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
126    const MachineOperand &MO = MI->getOperand(i);
127    if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
128      continue;
129
130    int Cycle = ItinData->getOperandCycle(DefClass, i);
131    if (Cycle < 0)
132      continue;
133
134    Latency = std::max(Latency, (unsigned) Cycle);
135  }
136
137  return Latency;
138}
139
140int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
141                                    const MachineInstr *DefMI, unsigned DefIdx,
142                                    const MachineInstr *UseMI,
143                                    unsigned UseIdx) const {
144  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
145                                                   UseMI, UseIdx);
146
147  if (!DefMI->getParent())
148    return Latency;
149
150  const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
151  unsigned Reg = DefMO.getReg();
152
153  bool IsRegCR;
154  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
155    const MachineRegisterInfo *MRI =
156      &DefMI->getParent()->getParent()->getRegInfo();
157    IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
158              MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
159  } else {
160    IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
161              PPC::CRBITRCRegClass.contains(Reg);
162  }
163
164  if (UseMI->isBranch() && IsRegCR) {
165    if (Latency < 0)
166      Latency = getInstrLatency(ItinData, DefMI);
167
168    // On some cores, there is an additional delay between writing to a condition
169    // register, and using it from a branch.
170    unsigned Directive = Subtarget.getDarwinDirective();
171    switch (Directive) {
172    default: break;
173    case PPC::DIR_7400:
174    case PPC::DIR_750:
175    case PPC::DIR_970:
176    case PPC::DIR_E5500:
177    case PPC::DIR_PWR4:
178    case PPC::DIR_PWR5:
179    case PPC::DIR_PWR5X:
180    case PPC::DIR_PWR6:
181    case PPC::DIR_PWR6X:
182    case PPC::DIR_PWR7:
183    case PPC::DIR_PWR8:
184      Latency += 2;
185      break;
186    }
187  }
188
189  return Latency;
190}
191
192// This function does not list all associative and commutative operations, but
193// only those worth feeding through the machine combiner in an attempt to
194// reduce the critical path. Mostly, this means floating-point operations,
195// because they have high latencies (compared to other operations, such and
196// and/or, which are also associative and commutative, but have low latencies).
197bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
198  switch (Inst.getOpcode()) {
199  // FP Add:
200  case PPC::FADD:
201  case PPC::FADDS:
202  // FP Multiply:
203  case PPC::FMUL:
204  case PPC::FMULS:
205  // Altivec Add:
206  case PPC::VADDFP:
207  // VSX Add:
208  case PPC::XSADDDP:
209  case PPC::XVADDDP:
210  case PPC::XVADDSP:
211  case PPC::XSADDSP:
212  // VSX Multiply:
213  case PPC::XSMULDP:
214  case PPC::XVMULDP:
215  case PPC::XVMULSP:
216  case PPC::XSMULSP:
217  // QPX Add:
218  case PPC::QVFADD:
219  case PPC::QVFADDS:
220  case PPC::QVFADDSs:
221  // QPX Multiply:
222  case PPC::QVFMUL:
223  case PPC::QVFMULS:
224  case PPC::QVFMULSs:
225    return true;
226  default:
227    return false;
228  }
229}
230
231bool PPCInstrInfo::getMachineCombinerPatterns(
232    MachineInstr &Root,
233    SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
234  // Using the machine combiner in this way is potentially expensive, so
235  // restrict to when aggressive optimizations are desired.
236  if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
237    return false;
238
239  // FP reassociation is only legal when we don't need strict IEEE semantics.
240  if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
241    return false;
242
243  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
244}
245
246// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
247bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
248                                         unsigned &SrcReg, unsigned &DstReg,
249                                         unsigned &SubIdx) const {
250  switch (MI.getOpcode()) {
251  default: return false;
252  case PPC::EXTSW:
253  case PPC::EXTSW_32_64:
254    SrcReg = MI.getOperand(1).getReg();
255    DstReg = MI.getOperand(0).getReg();
256    SubIdx = PPC::sub_32;
257    return true;
258  }
259}
260
261unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
262                                           int &FrameIndex) const {
263  // Note: This list must be kept consistent with LoadRegFromStackSlot.
264  switch (MI->getOpcode()) {
265  default: break;
266  case PPC::LD:
267  case PPC::LWZ:
268  case PPC::LFS:
269  case PPC::LFD:
270  case PPC::RESTORE_CR:
271  case PPC::RESTORE_CRBIT:
272  case PPC::LVX:
273  case PPC::LXVD2X:
274  case PPC::QVLFDX:
275  case PPC::QVLFSXs:
276  case PPC::QVLFDXb:
277  case PPC::RESTORE_VRSAVE:
278    // Check for the operands added by addFrameReference (the immediate is the
279    // offset which defaults to 0).
280    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
281        MI->getOperand(2).isFI()) {
282      FrameIndex = MI->getOperand(2).getIndex();
283      return MI->getOperand(0).getReg();
284    }
285    break;
286  }
287  return 0;
288}
289
290unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
291                                          int &FrameIndex) const {
292  // Note: This list must be kept consistent with StoreRegToStackSlot.
293  switch (MI->getOpcode()) {
294  default: break;
295  case PPC::STD:
296  case PPC::STW:
297  case PPC::STFS:
298  case PPC::STFD:
299  case PPC::SPILL_CR:
300  case PPC::SPILL_CRBIT:
301  case PPC::STVX:
302  case PPC::STXVD2X:
303  case PPC::QVSTFDX:
304  case PPC::QVSTFSXs:
305  case PPC::QVSTFDXb:
306  case PPC::SPILL_VRSAVE:
307    // Check for the operands added by addFrameReference (the immediate is the
308    // offset which defaults to 0).
309    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
310        MI->getOperand(2).isFI()) {
311      FrameIndex = MI->getOperand(2).getIndex();
312      return MI->getOperand(0).getReg();
313    }
314    break;
315  }
316  return 0;
317}
318
319MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr *MI,
320                                                   bool NewMI,
321                                                   unsigned OpIdx1,
322                                                   unsigned OpIdx2) const {
323  MachineFunction &MF = *MI->getParent()->getParent();
324
325  // Normal instructions can be commuted the obvious way.
326  if (MI->getOpcode() != PPC::RLWIMI &&
327      MI->getOpcode() != PPC::RLWIMIo)
328    return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
329  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
330  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
331  // changing the relative order of the mask operands might change what happens
332  // to the high-bits of the mask (and, thus, the result).
333
334  // Cannot commute if it has a non-zero rotate count.
335  if (MI->getOperand(3).getImm() != 0)
336    return nullptr;
337
338  // If we have a zero rotate count, we have:
339  //   M = mask(MB,ME)
340  //   Op0 = (Op1 & ~M) | (Op2 & M)
341  // Change this to:
342  //   M = mask((ME+1)&31, (MB-1)&31)
343  //   Op0 = (Op2 & ~M) | (Op1 & M)
344
345  // Swap op1/op2
346  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
347         "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
348  unsigned Reg0 = MI->getOperand(0).getReg();
349  unsigned Reg1 = MI->getOperand(1).getReg();
350  unsigned Reg2 = MI->getOperand(2).getReg();
351  unsigned SubReg1 = MI->getOperand(1).getSubReg();
352  unsigned SubReg2 = MI->getOperand(2).getSubReg();
353  bool Reg1IsKill = MI->getOperand(1).isKill();
354  bool Reg2IsKill = MI->getOperand(2).isKill();
355  bool ChangeReg0 = false;
356  // If machine instrs are no longer in two-address forms, update
357  // destination register as well.
358  if (Reg0 == Reg1) {
359    // Must be two address instruction!
360    assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
361           "Expecting a two-address instruction!");
362    assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
363    Reg2IsKill = false;
364    ChangeReg0 = true;
365  }
366
367  // Masks.
368  unsigned MB = MI->getOperand(4).getImm();
369  unsigned ME = MI->getOperand(5).getImm();
370
371  // We can't commute a trivial mask (there is no way to represent an all-zero
372  // mask).
373  if (MB == 0 && ME == 31)
374    return nullptr;
375
376  if (NewMI) {
377    // Create a new instruction.
378    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
379    bool Reg0IsDead = MI->getOperand(0).isDead();
380    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
381      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
382      .addReg(Reg2, getKillRegState(Reg2IsKill))
383      .addReg(Reg1, getKillRegState(Reg1IsKill))
384      .addImm((ME+1) & 31)
385      .addImm((MB-1) & 31);
386  }
387
388  if (ChangeReg0) {
389    MI->getOperand(0).setReg(Reg2);
390    MI->getOperand(0).setSubReg(SubReg2);
391  }
392  MI->getOperand(2).setReg(Reg1);
393  MI->getOperand(1).setReg(Reg2);
394  MI->getOperand(2).setSubReg(SubReg1);
395  MI->getOperand(1).setSubReg(SubReg2);
396  MI->getOperand(2).setIsKill(Reg1IsKill);
397  MI->getOperand(1).setIsKill(Reg2IsKill);
398
399  // Swap the mask around.
400  MI->getOperand(4).setImm((ME+1) & 31);
401  MI->getOperand(5).setImm((MB-1) & 31);
402  return MI;
403}
404
405bool PPCInstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
406                                         unsigned &SrcOpIdx2) const {
407  // For VSX A-Type FMA instructions, it is the first two operands that can be
408  // commuted, however, because the non-encoded tied input operand is listed
409  // first, the operands to swap are actually the second and third.
410
411  int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
412  if (AltOpc == -1)
413    return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
414
415  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
416  // and SrcOpIdx2.
417  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
418}
419
420void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
421                              MachineBasicBlock::iterator MI) const {
422  // This function is used for scheduling, and the nop wanted here is the type
423  // that terminates dispatch groups on the POWER cores.
424  unsigned Directive = Subtarget.getDarwinDirective();
425  unsigned Opcode;
426  switch (Directive) {
427  default:            Opcode = PPC::NOP; break;
428  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
429  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
430  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
431  }
432
433  DebugLoc DL;
434  BuildMI(MBB, MI, DL, get(Opcode));
435}
436
437/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
438void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
439  NopInst.setOpcode(PPC::NOP);
440}
441
442// Branch analysis.
443// Note: If the condition register is set to CTR or CTR8 then this is a
444// BDNZ (imm == 1) or BDZ (imm == 0) branch.
445bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
446                                 MachineBasicBlock *&FBB,
447                                 SmallVectorImpl<MachineOperand> &Cond,
448                                 bool AllowModify) const {
449  bool isPPC64 = Subtarget.isPPC64();
450
451  // If the block has no terminators, it just falls into the block after it.
452  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
453  if (I == MBB.end())
454    return false;
455
456  if (!isUnpredicatedTerminator(I))
457    return false;
458
459  // Get the last instruction in the block.
460  MachineInstr *LastInst = I;
461
462  // If there is only one terminator instruction, process it.
463  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
464    if (LastInst->getOpcode() == PPC::B) {
465      if (!LastInst->getOperand(0).isMBB())
466        return true;
467      TBB = LastInst->getOperand(0).getMBB();
468      return false;
469    } else if (LastInst->getOpcode() == PPC::BCC) {
470      if (!LastInst->getOperand(2).isMBB())
471        return true;
472      // Block ends with fall-through condbranch.
473      TBB = LastInst->getOperand(2).getMBB();
474      Cond.push_back(LastInst->getOperand(0));
475      Cond.push_back(LastInst->getOperand(1));
476      return false;
477    } else if (LastInst->getOpcode() == PPC::BC) {
478      if (!LastInst->getOperand(1).isMBB())
479        return true;
480      // Block ends with fall-through condbranch.
481      TBB = LastInst->getOperand(1).getMBB();
482      Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
483      Cond.push_back(LastInst->getOperand(0));
484      return false;
485    } else if (LastInst->getOpcode() == PPC::BCn) {
486      if (!LastInst->getOperand(1).isMBB())
487        return true;
488      // Block ends with fall-through condbranch.
489      TBB = LastInst->getOperand(1).getMBB();
490      Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
491      Cond.push_back(LastInst->getOperand(0));
492      return false;
493    } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
494               LastInst->getOpcode() == PPC::BDNZ) {
495      if (!LastInst->getOperand(0).isMBB())
496        return true;
497      if (DisableCTRLoopAnal)
498        return true;
499      TBB = LastInst->getOperand(0).getMBB();
500      Cond.push_back(MachineOperand::CreateImm(1));
501      Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
502                                               true));
503      return false;
504    } else if (LastInst->getOpcode() == PPC::BDZ8 ||
505               LastInst->getOpcode() == PPC::BDZ) {
506      if (!LastInst->getOperand(0).isMBB())
507        return true;
508      if (DisableCTRLoopAnal)
509        return true;
510      TBB = LastInst->getOperand(0).getMBB();
511      Cond.push_back(MachineOperand::CreateImm(0));
512      Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
513                                               true));
514      return false;
515    }
516
517    // Otherwise, don't know what this is.
518    return true;
519  }
520
521  // Get the instruction before it if it's a terminator.
522  MachineInstr *SecondLastInst = I;
523
524  // If there are three terminators, we don't know what sort of block this is.
525  if (SecondLastInst && I != MBB.begin() &&
526      isUnpredicatedTerminator(--I))
527    return true;
528
529  // If the block ends with PPC::B and PPC:BCC, handle it.
530  if (SecondLastInst->getOpcode() == PPC::BCC &&
531      LastInst->getOpcode() == PPC::B) {
532    if (!SecondLastInst->getOperand(2).isMBB() ||
533        !LastInst->getOperand(0).isMBB())
534      return true;
535    TBB =  SecondLastInst->getOperand(2).getMBB();
536    Cond.push_back(SecondLastInst->getOperand(0));
537    Cond.push_back(SecondLastInst->getOperand(1));
538    FBB = LastInst->getOperand(0).getMBB();
539    return false;
540  } else if (SecondLastInst->getOpcode() == PPC::BC &&
541      LastInst->getOpcode() == PPC::B) {
542    if (!SecondLastInst->getOperand(1).isMBB() ||
543        !LastInst->getOperand(0).isMBB())
544      return true;
545    TBB =  SecondLastInst->getOperand(1).getMBB();
546    Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
547    Cond.push_back(SecondLastInst->getOperand(0));
548    FBB = LastInst->getOperand(0).getMBB();
549    return false;
550  } else if (SecondLastInst->getOpcode() == PPC::BCn &&
551      LastInst->getOpcode() == PPC::B) {
552    if (!SecondLastInst->getOperand(1).isMBB() ||
553        !LastInst->getOperand(0).isMBB())
554      return true;
555    TBB =  SecondLastInst->getOperand(1).getMBB();
556    Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
557    Cond.push_back(SecondLastInst->getOperand(0));
558    FBB = LastInst->getOperand(0).getMBB();
559    return false;
560  } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
561              SecondLastInst->getOpcode() == PPC::BDNZ) &&
562      LastInst->getOpcode() == PPC::B) {
563    if (!SecondLastInst->getOperand(0).isMBB() ||
564        !LastInst->getOperand(0).isMBB())
565      return true;
566    if (DisableCTRLoopAnal)
567      return true;
568    TBB = SecondLastInst->getOperand(0).getMBB();
569    Cond.push_back(MachineOperand::CreateImm(1));
570    Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
571                                             true));
572    FBB = LastInst->getOperand(0).getMBB();
573    return false;
574  } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
575              SecondLastInst->getOpcode() == PPC::BDZ) &&
576      LastInst->getOpcode() == PPC::B) {
577    if (!SecondLastInst->getOperand(0).isMBB() ||
578        !LastInst->getOperand(0).isMBB())
579      return true;
580    if (DisableCTRLoopAnal)
581      return true;
582    TBB = SecondLastInst->getOperand(0).getMBB();
583    Cond.push_back(MachineOperand::CreateImm(0));
584    Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
585                                             true));
586    FBB = LastInst->getOperand(0).getMBB();
587    return false;
588  }
589
590  // If the block ends with two PPC:Bs, handle it.  The second one is not
591  // executed, so remove it.
592  if (SecondLastInst->getOpcode() == PPC::B &&
593      LastInst->getOpcode() == PPC::B) {
594    if (!SecondLastInst->getOperand(0).isMBB())
595      return true;
596    TBB = SecondLastInst->getOperand(0).getMBB();
597    I = LastInst;
598    if (AllowModify)
599      I->eraseFromParent();
600    return false;
601  }
602
603  // Otherwise, can't handle this.
604  return true;
605}
606
607unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
608  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
609  if (I == MBB.end())
610    return 0;
611
612  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
613      I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
614      I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
615      I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
616    return 0;
617
618  // Remove the branch.
619  I->eraseFromParent();
620
621  I = MBB.end();
622
623  if (I == MBB.begin()) return 1;
624  --I;
625  if (I->getOpcode() != PPC::BCC &&
626      I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
627      I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
628      I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
629    return 1;
630
631  // Remove the branch.
632  I->eraseFromParent();
633  return 2;
634}
635
636unsigned
637PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
638                           MachineBasicBlock *FBB,
639                           ArrayRef<MachineOperand> Cond,
640                           DebugLoc DL) const {
641  // Shouldn't be a fall through.
642  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
643  assert((Cond.size() == 2 || Cond.size() == 0) &&
644         "PPC branch conditions have two components!");
645
646  bool isPPC64 = Subtarget.isPPC64();
647
648  // One-way branch.
649  if (!FBB) {
650    if (Cond.empty())   // Unconditional branch
651      BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
652    else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
653      BuildMI(&MBB, DL, get(Cond[0].getImm() ?
654                              (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
655                              (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
656    else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
657      BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
658    else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
659      BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
660    else                // Conditional branch
661      BuildMI(&MBB, DL, get(PPC::BCC))
662        .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
663    return 1;
664  }
665
666  // Two-way Conditional Branch.
667  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
668    BuildMI(&MBB, DL, get(Cond[0].getImm() ?
669                            (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
670                            (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
671  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
672    BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
673  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
674    BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
675  else
676    BuildMI(&MBB, DL, get(PPC::BCC))
677      .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
678  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
679  return 2;
680}
681
682// Select analysis.
683bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
684                ArrayRef<MachineOperand> Cond,
685                unsigned TrueReg, unsigned FalseReg,
686                int &CondCycles, int &TrueCycles, int &FalseCycles) const {
687  if (!Subtarget.hasISEL())
688    return false;
689
690  if (Cond.size() != 2)
691    return false;
692
693  // If this is really a bdnz-like condition, then it cannot be turned into a
694  // select.
695  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
696    return false;
697
698  // Check register classes.
699  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
700  const TargetRegisterClass *RC =
701    RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
702  if (!RC)
703    return false;
704
705  // isel is for regular integer GPRs only.
706  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
707      !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
708      !PPC::G8RCRegClass.hasSubClassEq(RC) &&
709      !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
710    return false;
711
712  // FIXME: These numbers are for the A2, how well they work for other cores is
713  // an open question. On the A2, the isel instruction has a 2-cycle latency
714  // but single-cycle throughput. These numbers are used in combination with
715  // the MispredictPenalty setting from the active SchedMachineModel.
716  CondCycles = 1;
717  TrueCycles = 1;
718  FalseCycles = 1;
719
720  return true;
721}
722
723void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
724                                MachineBasicBlock::iterator MI, DebugLoc dl,
725                                unsigned DestReg, ArrayRef<MachineOperand> Cond,
726                                unsigned TrueReg, unsigned FalseReg) const {
727  assert(Cond.size() == 2 &&
728         "PPC branch conditions have two components!");
729
730  assert(Subtarget.hasISEL() &&
731         "Cannot insert select on target without ISEL support");
732
733  // Get the register classes.
734  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
735  const TargetRegisterClass *RC =
736    RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
737  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
738
739  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
740                 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
741  assert((Is64Bit ||
742          PPC::GPRCRegClass.hasSubClassEq(RC) ||
743          PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
744         "isel is for regular integer GPRs only");
745
746  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
747  unsigned SelectPred = Cond[0].getImm();
748
749  unsigned SubIdx;
750  bool SwapOps;
751  switch (SelectPred) {
752  default: llvm_unreachable("invalid predicate for isel");
753  case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
754  case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
755  case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
756  case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
757  case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
758  case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
759  case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
760  case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
761  case PPC::PRED_BIT_SET:   SubIdx = 0; SwapOps = false; break;
762  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
763  }
764
765  unsigned FirstReg =  SwapOps ? FalseReg : TrueReg,
766           SecondReg = SwapOps ? TrueReg  : FalseReg;
767
768  // The first input register of isel cannot be r0. If it is a member
769  // of a register class that can be r0, then copy it first (the
770  // register allocator should eliminate the copy).
771  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
772      MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
773    const TargetRegisterClass *FirstRC =
774      MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
775        &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
776    unsigned OldFirstReg = FirstReg;
777    FirstReg = MRI.createVirtualRegister(FirstRC);
778    BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
779      .addReg(OldFirstReg);
780  }
781
782  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
783    .addReg(FirstReg).addReg(SecondReg)
784    .addReg(Cond[1].getReg(), 0, SubIdx);
785}
786
787static unsigned getCRBitValue(unsigned CRBit) {
788  unsigned Ret = 4;
789  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
790      CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
791      CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
792      CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
793    Ret = 3;
794  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
795      CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
796      CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
797      CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
798    Ret = 2;
799  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
800      CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
801      CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
802      CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
803    Ret = 1;
804  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
805      CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
806      CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
807      CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
808    Ret = 0;
809
810  assert(Ret != 4 && "Invalid CR bit register");
811  return Ret;
812}
813
814void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
815                               MachineBasicBlock::iterator I, DebugLoc DL,
816                               unsigned DestReg, unsigned SrcReg,
817                               bool KillSrc) const {
818  // We can end up with self copies and similar things as a result of VSX copy
819  // legalization. Promote them here.
820  const TargetRegisterInfo *TRI = &getRegisterInfo();
821  if (PPC::F8RCRegClass.contains(DestReg) &&
822      PPC::VSRCRegClass.contains(SrcReg)) {
823    unsigned SuperReg =
824      TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
825
826    if (VSXSelfCopyCrash && SrcReg == SuperReg)
827      llvm_unreachable("nop VSX copy");
828
829    DestReg = SuperReg;
830  } else if (PPC::VRRCRegClass.contains(DestReg) &&
831             PPC::VSRCRegClass.contains(SrcReg)) {
832    unsigned SuperReg =
833      TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
834
835    if (VSXSelfCopyCrash && SrcReg == SuperReg)
836      llvm_unreachable("nop VSX copy");
837
838    DestReg = SuperReg;
839  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
840             PPC::VSRCRegClass.contains(DestReg)) {
841    unsigned SuperReg =
842      TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
843
844    if (VSXSelfCopyCrash && DestReg == SuperReg)
845      llvm_unreachable("nop VSX copy");
846
847    SrcReg = SuperReg;
848  } else if (PPC::VRRCRegClass.contains(SrcReg) &&
849             PPC::VSRCRegClass.contains(DestReg)) {
850    unsigned SuperReg =
851      TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
852
853    if (VSXSelfCopyCrash && DestReg == SuperReg)
854      llvm_unreachable("nop VSX copy");
855
856    SrcReg = SuperReg;
857  }
858
859  // Different class register copy
860  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
861      PPC::GPRCRegClass.contains(DestReg)) {
862    unsigned CRReg = getCRFromCRBit(SrcReg);
863    BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
864       .addReg(CRReg), getKillRegState(KillSrc);
865    // Rotate the CR bit in the CR fields to be the least significant bit and
866    // then mask with 0x1 (MB = ME = 31).
867    BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
868       .addReg(DestReg, RegState::Kill)
869       .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
870       .addImm(31)
871       .addImm(31);
872    return;
873  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
874      PPC::G8RCRegClass.contains(DestReg)) {
875    BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg)
876       .addReg(SrcReg), getKillRegState(KillSrc);
877    return;
878  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
879      PPC::GPRCRegClass.contains(DestReg)) {
880    BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
881       .addReg(SrcReg), getKillRegState(KillSrc);
882    return;
883   }
884
885  unsigned Opc;
886  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
887    Opc = PPC::OR;
888  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
889    Opc = PPC::OR8;
890  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
891    Opc = PPC::FMR;
892  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
893    Opc = PPC::MCRF;
894  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
895    Opc = PPC::VOR;
896  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
897    // There are two different ways this can be done:
898    //   1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
899    //      issue in VSU pipeline 0.
900    //   2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
901    //      can go to either pipeline.
902    // We'll always use xxlor here, because in practically all cases where
903    // copies are generated, they are close enough to some use that the
904    // lower-latency form is preferable.
905    Opc = PPC::XXLOR;
906  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
907           PPC::VSSRCRegClass.contains(DestReg, SrcReg))
908    Opc = PPC::XXLORf;
909  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
910    Opc = PPC::QVFMR;
911  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
912    Opc = PPC::QVFMRs;
913  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
914    Opc = PPC::QVFMRb;
915  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
916    Opc = PPC::CROR;
917  else
918    llvm_unreachable("Impossible reg-to-reg copy");
919
920  const MCInstrDesc &MCID = get(Opc);
921  if (MCID.getNumOperands() == 3)
922    BuildMI(MBB, I, DL, MCID, DestReg)
923      .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
924  else
925    BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
926}
927
928// This function returns true if a CR spill is necessary and false otherwise.
929bool
930PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
931                                  unsigned SrcReg, bool isKill,
932                                  int FrameIdx,
933                                  const TargetRegisterClass *RC,
934                                  SmallVectorImpl<MachineInstr*> &NewMIs,
935                                  bool &NonRI, bool &SpillsVRS) const{
936  // Note: If additional store instructions are added here,
937  // update isStoreToStackSlot.
938
939  DebugLoc DL;
940  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
941      PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
942    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
943                                       .addReg(SrcReg,
944                                               getKillRegState(isKill)),
945                                       FrameIdx));
946  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
947             PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
948    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
949                                       .addReg(SrcReg,
950                                               getKillRegState(isKill)),
951                                       FrameIdx));
952  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
953    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
954                                       .addReg(SrcReg,
955                                               getKillRegState(isKill)),
956                                       FrameIdx));
957  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
958    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
959                                       .addReg(SrcReg,
960                                               getKillRegState(isKill)),
961                                       FrameIdx));
962  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
963    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
964                                       .addReg(SrcReg,
965                                               getKillRegState(isKill)),
966                                       FrameIdx));
967    return true;
968  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
969    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
970                                       .addReg(SrcReg,
971                                               getKillRegState(isKill)),
972                                       FrameIdx));
973    return true;
974  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
975    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
976                                       .addReg(SrcReg,
977                                               getKillRegState(isKill)),
978                                       FrameIdx));
979    NonRI = true;
980  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
981    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
982                                       .addReg(SrcReg,
983                                               getKillRegState(isKill)),
984                                       FrameIdx));
985    NonRI = true;
986  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
987    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX))
988                                       .addReg(SrcReg,
989                                               getKillRegState(isKill)),
990                                       FrameIdx));
991    NonRI = true;
992  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
993    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX))
994                                       .addReg(SrcReg,
995                                               getKillRegState(isKill)),
996                                       FrameIdx));
997    NonRI = true;
998  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
999    assert(Subtarget.isDarwin() &&
1000           "VRSAVE only needs spill/restore on Darwin");
1001    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
1002                                       .addReg(SrcReg,
1003                                               getKillRegState(isKill)),
1004                                       FrameIdx));
1005    SpillsVRS = true;
1006  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1007    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
1008                                       .addReg(SrcReg,
1009                                               getKillRegState(isKill)),
1010                                       FrameIdx));
1011    NonRI = true;
1012  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1013    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
1014                                       .addReg(SrcReg,
1015                                               getKillRegState(isKill)),
1016                                       FrameIdx));
1017    NonRI = true;
1018  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1019    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
1020                                       .addReg(SrcReg,
1021                                               getKillRegState(isKill)),
1022                                       FrameIdx));
1023    NonRI = true;
1024  } else {
1025    llvm_unreachable("Unknown regclass!");
1026  }
1027
1028  return false;
1029}
1030
1031void
1032PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1033                                  MachineBasicBlock::iterator MI,
1034                                  unsigned SrcReg, bool isKill, int FrameIdx,
1035                                  const TargetRegisterClass *RC,
1036                                  const TargetRegisterInfo *TRI) const {
1037  MachineFunction &MF = *MBB.getParent();
1038  SmallVector<MachineInstr*, 4> NewMIs;
1039
1040  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1041  FuncInfo->setHasSpills();
1042
1043  bool NonRI = false, SpillsVRS = false;
1044  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1045                          NonRI, SpillsVRS))
1046    FuncInfo->setSpillsCR();
1047
1048  if (SpillsVRS)
1049    FuncInfo->setSpillsVRSAVE();
1050
1051  if (NonRI)
1052    FuncInfo->setHasNonRISpills();
1053
1054  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1055    MBB.insert(MI, NewMIs[i]);
1056
1057  const MachineFrameInfo &MFI = *MF.getFrameInfo();
1058  MachineMemOperand *MMO = MF.getMachineMemOperand(
1059      MachinePointerInfo::getFixedStack(MF, FrameIdx),
1060      MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
1061      MFI.getObjectAlignment(FrameIdx));
1062  NewMIs.back()->addMemOperand(MF, MMO);
1063}
1064
1065bool
1066PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
1067                                   unsigned DestReg, int FrameIdx,
1068                                   const TargetRegisterClass *RC,
1069                                   SmallVectorImpl<MachineInstr*> &NewMIs,
1070                                   bool &NonRI, bool &SpillsVRS) const{
1071  // Note: If additional load instructions are added here,
1072  // update isLoadFromStackSlot.
1073
1074  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1075      PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1076    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1077                                               DestReg), FrameIdx));
1078  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1079             PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1080    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1081                                       FrameIdx));
1082  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1083    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1084                                       FrameIdx));
1085  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1086    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1087                                       FrameIdx));
1088  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1089    NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1090                                               get(PPC::RESTORE_CR), DestReg),
1091                                       FrameIdx));
1092    return true;
1093  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1094    NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1095                                               get(PPC::RESTORE_CRBIT), DestReg),
1096                                       FrameIdx));
1097    return true;
1098  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1099    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1100                                       FrameIdx));
1101    NonRI = true;
1102  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1103    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg),
1104                                       FrameIdx));
1105    NonRI = true;
1106  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1107    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg),
1108                                       FrameIdx));
1109    NonRI = true;
1110  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1111    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg),
1112                                       FrameIdx));
1113    NonRI = true;
1114  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1115    assert(Subtarget.isDarwin() &&
1116           "VRSAVE only needs spill/restore on Darwin");
1117    NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1118                                               get(PPC::RESTORE_VRSAVE),
1119                                               DestReg),
1120                                       FrameIdx));
1121    SpillsVRS = true;
1122  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1123    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1124                                       FrameIdx));
1125    NonRI = true;
1126  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1127    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1128                                       FrameIdx));
1129    NonRI = true;
1130  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1131    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1132                                       FrameIdx));
1133    NonRI = true;
1134  } else {
1135    llvm_unreachable("Unknown regclass!");
1136  }
1137
1138  return false;
1139}
1140
1141void
1142PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1143                                   MachineBasicBlock::iterator MI,
1144                                   unsigned DestReg, int FrameIdx,
1145                                   const TargetRegisterClass *RC,
1146                                   const TargetRegisterInfo *TRI) const {
1147  MachineFunction &MF = *MBB.getParent();
1148  SmallVector<MachineInstr*, 4> NewMIs;
1149  DebugLoc DL;
1150  if (MI != MBB.end()) DL = MI->getDebugLoc();
1151
1152  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1153  FuncInfo->setHasSpills();
1154
1155  bool NonRI = false, SpillsVRS = false;
1156  if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1157                           NonRI, SpillsVRS))
1158    FuncInfo->setSpillsCR();
1159
1160  if (SpillsVRS)
1161    FuncInfo->setSpillsVRSAVE();
1162
1163  if (NonRI)
1164    FuncInfo->setHasNonRISpills();
1165
1166  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1167    MBB.insert(MI, NewMIs[i]);
1168
1169  const MachineFrameInfo &MFI = *MF.getFrameInfo();
1170  MachineMemOperand *MMO = MF.getMachineMemOperand(
1171      MachinePointerInfo::getFixedStack(MF, FrameIdx),
1172      MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
1173      MFI.getObjectAlignment(FrameIdx));
1174  NewMIs.back()->addMemOperand(MF, MMO);
1175}
1176
1177bool PPCInstrInfo::
1178ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1179  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1180  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1181    Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1182  else
1183    // Leave the CR# the same, but invert the condition.
1184    Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1185  return false;
1186}
1187
1188bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1189                             unsigned Reg, MachineRegisterInfo *MRI) const {
1190  // For some instructions, it is legal to fold ZERO into the RA register field.
1191  // A zero immediate should always be loaded with a single li.
1192  unsigned DefOpc = DefMI->getOpcode();
1193  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1194    return false;
1195  if (!DefMI->getOperand(1).isImm())
1196    return false;
1197  if (DefMI->getOperand(1).getImm() != 0)
1198    return false;
1199
1200  // Note that we cannot here invert the arguments of an isel in order to fold
1201  // a ZERO into what is presented as the second argument. All we have here
1202  // is the condition bit, and that might come from a CR-logical bit operation.
1203
1204  const MCInstrDesc &UseMCID = UseMI->getDesc();
1205
1206  // Only fold into real machine instructions.
1207  if (UseMCID.isPseudo())
1208    return false;
1209
1210  unsigned UseIdx;
1211  for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
1212    if (UseMI->getOperand(UseIdx).isReg() &&
1213        UseMI->getOperand(UseIdx).getReg() == Reg)
1214      break;
1215
1216  assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
1217  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1218
1219  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1220
1221  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1222  // register (which might also be specified as a pointer class kind).
1223  if (UseInfo->isLookupPtrRegClass()) {
1224    if (UseInfo->RegClass /* Kind */ != 1)
1225      return false;
1226  } else {
1227    if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1228        UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1229      return false;
1230  }
1231
1232  // Make sure this is not tied to an output register (or otherwise
1233  // constrained). This is true for ST?UX registers, for example, which
1234  // are tied to their output registers.
1235  if (UseInfo->Constraints != 0)
1236    return false;
1237
1238  unsigned ZeroReg;
1239  if (UseInfo->isLookupPtrRegClass()) {
1240    bool isPPC64 = Subtarget.isPPC64();
1241    ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1242  } else {
1243    ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1244              PPC::ZERO8 : PPC::ZERO;
1245  }
1246
1247  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1248  UseMI->getOperand(UseIdx).setReg(ZeroReg);
1249
1250  if (DeleteDef)
1251    DefMI->eraseFromParent();
1252
1253  return true;
1254}
1255
1256static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1257  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1258       I != IE; ++I)
1259    if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1260      return true;
1261  return false;
1262}
1263
1264// We should make sure that, if we're going to predicate both sides of a
1265// condition (a diamond), that both sides don't define the counter register. We
1266// can predicate counter-decrement-based branches, but while that predicates
1267// the branching, it does not predicate the counter decrement. If we tried to
1268// merge the triangle into one predicated block, we'd decrement the counter
1269// twice.
1270bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1271                     unsigned NumT, unsigned ExtraT,
1272                     MachineBasicBlock &FMBB,
1273                     unsigned NumF, unsigned ExtraF,
1274                     BranchProbability Probability) const {
1275  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1276}
1277
1278
1279bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
1280  // The predicated branches are identified by their type, not really by the
1281  // explicit presence of a predicate. Furthermore, some of them can be
1282  // predicated more than once. Because if conversion won't try to predicate
1283  // any instruction which already claims to be predicated (by returning true
1284  // here), always return false. In doing so, we let isPredicable() be the
1285  // final word on whether not the instruction can be (further) predicated.
1286
1287  return false;
1288}
1289
1290bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1291  if (!MI->isTerminator())
1292    return false;
1293
1294  // Conditional branch is a special case.
1295  if (MI->isBranch() && !MI->isBarrier())
1296    return true;
1297
1298  return !isPredicated(MI);
1299}
1300
1301bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
1302                                        ArrayRef<MachineOperand> Pred) const {
1303  unsigned OpC = MI->getOpcode();
1304  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1305    if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1306      bool isPPC64 = Subtarget.isPPC64();
1307      MI->setDesc(get(Pred[0].getImm() ?
1308                      (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1309                      (isPPC64 ? PPC::BDZLR8  : PPC::BDZLR)));
1310    } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1311      MI->setDesc(get(PPC::BCLR));
1312      MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1313        .addReg(Pred[1].getReg());
1314    } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1315      MI->setDesc(get(PPC::BCLRn));
1316      MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1317        .addReg(Pred[1].getReg());
1318    } else {
1319      MI->setDesc(get(PPC::BCCLR));
1320      MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1321        .addImm(Pred[0].getImm())
1322        .addReg(Pred[1].getReg());
1323    }
1324
1325    return true;
1326  } else if (OpC == PPC::B) {
1327    if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1328      bool isPPC64 = Subtarget.isPPC64();
1329      MI->setDesc(get(Pred[0].getImm() ?
1330                      (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1331                      (isPPC64 ? PPC::BDZ8  : PPC::BDZ)));
1332    } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1333      MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1334      MI->RemoveOperand(0);
1335
1336      MI->setDesc(get(PPC::BC));
1337      MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1338        .addReg(Pred[1].getReg())
1339        .addMBB(MBB);
1340    } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1341      MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1342      MI->RemoveOperand(0);
1343
1344      MI->setDesc(get(PPC::BCn));
1345      MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1346        .addReg(Pred[1].getReg())
1347        .addMBB(MBB);
1348    } else {
1349      MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1350      MI->RemoveOperand(0);
1351
1352      MI->setDesc(get(PPC::BCC));
1353      MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1354        .addImm(Pred[0].getImm())
1355        .addReg(Pred[1].getReg())
1356        .addMBB(MBB);
1357    }
1358
1359    return true;
1360  } else if (OpC == PPC::BCTR  || OpC == PPC::BCTR8 ||
1361             OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1362    if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1363      llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1364
1365    bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1366    bool isPPC64 = Subtarget.isPPC64();
1367
1368    if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1369      MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1370                                (setLR ? PPC::BCCTRL  : PPC::BCCTR)));
1371      MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1372        .addReg(Pred[1].getReg());
1373      return true;
1374    } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1375      MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1376                                (setLR ? PPC::BCCTRLn  : PPC::BCCTRn)));
1377      MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1378        .addReg(Pred[1].getReg());
1379      return true;
1380    }
1381
1382    MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1383                              (setLR ? PPC::BCCCTRL  : PPC::BCCCTR)));
1384    MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1385      .addImm(Pred[0].getImm())
1386      .addReg(Pred[1].getReg());
1387    return true;
1388  }
1389
1390  return false;
1391}
1392
1393bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1394                                     ArrayRef<MachineOperand> Pred2) const {
1395  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1396  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1397
1398  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1399    return false;
1400  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1401    return false;
1402
1403  // P1 can only subsume P2 if they test the same condition register.
1404  if (Pred1[1].getReg() != Pred2[1].getReg())
1405    return false;
1406
1407  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1408  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1409
1410  if (P1 == P2)
1411    return true;
1412
1413  // Does P1 subsume P2, e.g. GE subsumes GT.
1414  if (P1 == PPC::PRED_LE &&
1415      (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1416    return true;
1417  if (P1 == PPC::PRED_GE &&
1418      (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1419    return true;
1420
1421  return false;
1422}
1423
1424bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1425                                    std::vector<MachineOperand> &Pred) const {
1426  // Note: At the present time, the contents of Pred from this function is
1427  // unused by IfConversion. This implementation follows ARM by pushing the
1428  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1429  // predicate, instructions defining CTR or CTR8 are also included as
1430  // predicate-defining instructions.
1431
1432  const TargetRegisterClass *RCs[] =
1433    { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1434      &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1435
1436  bool Found = false;
1437  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1438    const MachineOperand &MO = MI->getOperand(i);
1439    for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1440      const TargetRegisterClass *RC = RCs[c];
1441      if (MO.isReg()) {
1442        if (MO.isDef() && RC->contains(MO.getReg())) {
1443          Pred.push_back(MO);
1444          Found = true;
1445        }
1446      } else if (MO.isRegMask()) {
1447        for (TargetRegisterClass::iterator I = RC->begin(),
1448             IE = RC->end(); I != IE; ++I)
1449          if (MO.clobbersPhysReg(*I)) {
1450            Pred.push_back(MO);
1451            Found = true;
1452          }
1453      }
1454    }
1455  }
1456
1457  return Found;
1458}
1459
1460bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1461  unsigned OpC = MI->getOpcode();
1462  switch (OpC) {
1463  default:
1464    return false;
1465  case PPC::B:
1466  case PPC::BLR:
1467  case PPC::BLR8:
1468  case PPC::BCTR:
1469  case PPC::BCTR8:
1470  case PPC::BCTRL:
1471  case PPC::BCTRL8:
1472    return true;
1473  }
1474}
1475
1476bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1477                                  unsigned &SrcReg, unsigned &SrcReg2,
1478                                  int &Mask, int &Value) const {
1479  unsigned Opc = MI->getOpcode();
1480
1481  switch (Opc) {
1482  default: return false;
1483  case PPC::CMPWI:
1484  case PPC::CMPLWI:
1485  case PPC::CMPDI:
1486  case PPC::CMPLDI:
1487    SrcReg = MI->getOperand(1).getReg();
1488    SrcReg2 = 0;
1489    Value = MI->getOperand(2).getImm();
1490    Mask = 0xFFFF;
1491    return true;
1492  case PPC::CMPW:
1493  case PPC::CMPLW:
1494  case PPC::CMPD:
1495  case PPC::CMPLD:
1496  case PPC::FCMPUS:
1497  case PPC::FCMPUD:
1498    SrcReg = MI->getOperand(1).getReg();
1499    SrcReg2 = MI->getOperand(2).getReg();
1500    return true;
1501  }
1502}
1503
1504bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
1505                                        unsigned SrcReg, unsigned SrcReg2,
1506                                        int Mask, int Value,
1507                                        const MachineRegisterInfo *MRI) const {
1508  if (DisableCmpOpt)
1509    return false;
1510
1511  int OpC = CmpInstr->getOpcode();
1512  unsigned CRReg = CmpInstr->getOperand(0).getReg();
1513
1514  // FP record forms set CR1 based on the execption status bits, not a
1515  // comparison with zero.
1516  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1517    return false;
1518
1519  // The record forms set the condition register based on a signed comparison
1520  // with zero (so says the ISA manual). This is not as straightforward as it
1521  // seems, however, because this is always a 64-bit comparison on PPC64, even
1522  // for instructions that are 32-bit in nature (like slw for example).
1523  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1524  // for equality checks (as those don't depend on the sign). On PPC64,
1525  // we are restricted to equality for unsigned 64-bit comparisons and for
1526  // signed 32-bit comparisons the applicability is more restricted.
1527  bool isPPC64 = Subtarget.isPPC64();
1528  bool is32BitSignedCompare   = OpC ==  PPC::CMPWI || OpC == PPC::CMPW;
1529  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1530  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1531
1532  // Get the unique definition of SrcReg.
1533  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1534  if (!MI) return false;
1535  int MIOpC = MI->getOpcode();
1536
1537  bool equalityOnly = false;
1538  bool noSub = false;
1539  if (isPPC64) {
1540    if (is32BitSignedCompare) {
1541      // We can perform this optimization only if MI is sign-extending.
1542      if (MIOpC == PPC::SRAW  || MIOpC == PPC::SRAWo ||
1543          MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1544          MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1545          MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1546          MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1547        noSub = true;
1548      } else
1549        return false;
1550    } else if (is32BitUnsignedCompare) {
1551      // We can perform this optimization, equality only, if MI is
1552      // zero-extending.
1553      if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1554          MIOpC == PPC::SLW    || MIOpC == PPC::SLWo ||
1555          MIOpC == PPC::SRW    || MIOpC == PPC::SRWo) {
1556        noSub = true;
1557        equalityOnly = true;
1558      } else
1559        return false;
1560    } else
1561      equalityOnly = is64BitUnsignedCompare;
1562  } else
1563    equalityOnly = is32BitUnsignedCompare;
1564
1565  if (equalityOnly) {
1566    // We need to check the uses of the condition register in order to reject
1567    // non-equality comparisons.
1568    for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg),
1569         IE = MRI->use_instr_end(); I != IE; ++I) {
1570      MachineInstr *UseMI = &*I;
1571      if (UseMI->getOpcode() == PPC::BCC) {
1572        unsigned Pred = UseMI->getOperand(0).getImm();
1573        if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1574          return false;
1575      } else if (UseMI->getOpcode() == PPC::ISEL ||
1576                 UseMI->getOpcode() == PPC::ISEL8) {
1577        unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1578        if (SubIdx != PPC::sub_eq)
1579          return false;
1580      } else
1581        return false;
1582    }
1583  }
1584
1585  MachineBasicBlock::iterator I = CmpInstr;
1586
1587  // Scan forward to find the first use of the compare.
1588  for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1589       I != EL; ++I) {
1590    bool FoundUse = false;
1591    for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg),
1592         JE = MRI->use_instr_end(); J != JE; ++J)
1593      if (&*J == &*I) {
1594        FoundUse = true;
1595        break;
1596      }
1597
1598    if (FoundUse)
1599      break;
1600  }
1601
1602  // There are two possible candidates which can be changed to set CR[01].
1603  // One is MI, the other is a SUB instruction.
1604  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1605  MachineInstr *Sub = nullptr;
1606  if (SrcReg2 != 0)
1607    // MI is not a candidate for CMPrr.
1608    MI = nullptr;
1609  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1610  // same BB as the comparison. This is to allow the check below to avoid calls
1611  // (and other explicit clobbers); instead we should really check for these
1612  // more explicitly (in at least a few predecessors).
1613  else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1614    // PPC does not have a record-form SUBri.
1615    return false;
1616  }
1617
1618  // Search for Sub.
1619  const TargetRegisterInfo *TRI = &getRegisterInfo();
1620  --I;
1621
1622  // Get ready to iterate backward from CmpInstr.
1623  MachineBasicBlock::iterator E = MI,
1624                              B = CmpInstr->getParent()->begin();
1625
1626  for (; I != E && !noSub; --I) {
1627    const MachineInstr &Instr = *I;
1628    unsigned IOpC = Instr.getOpcode();
1629
1630    if (&*I != CmpInstr && (
1631        Instr.modifiesRegister(PPC::CR0, TRI) ||
1632        Instr.readsRegister(PPC::CR0, TRI)))
1633      // This instruction modifies or uses the record condition register after
1634      // the one we want to change. While we could do this transformation, it
1635      // would likely not be profitable. This transformation removes one
1636      // instruction, and so even forcing RA to generate one move probably
1637      // makes it unprofitable.
1638      return false;
1639
1640    // Check whether CmpInstr can be made redundant by the current instruction.
1641    if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1642         OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1643        (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1644        ((Instr.getOperand(1).getReg() == SrcReg &&
1645          Instr.getOperand(2).getReg() == SrcReg2) ||
1646        (Instr.getOperand(1).getReg() == SrcReg2 &&
1647         Instr.getOperand(2).getReg() == SrcReg))) {
1648      Sub = &*I;
1649      break;
1650    }
1651
1652    if (I == B)
1653      // The 'and' is below the comparison instruction.
1654      return false;
1655  }
1656
1657  // Return false if no candidates exist.
1658  if (!MI && !Sub)
1659    return false;
1660
1661  // The single candidate is called MI.
1662  if (!MI) MI = Sub;
1663
1664  int NewOpC = -1;
1665  MIOpC = MI->getOpcode();
1666  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1667    NewOpC = MIOpC;
1668  else {
1669    NewOpC = PPC::getRecordFormOpcode(MIOpC);
1670    if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1671      NewOpC = MIOpC;
1672  }
1673
1674  // FIXME: On the non-embedded POWER architectures, only some of the record
1675  // forms are fast, and we should use only the fast ones.
1676
1677  // The defining instruction has a record form (or is already a record
1678  // form). It is possible, however, that we'll need to reverse the condition
1679  // code of the users.
1680  if (NewOpC == -1)
1681    return false;
1682
1683  SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1684  SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1685
1686  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1687  // needs to be updated to be based on SUB.  Push the condition code
1688  // operands to OperandsToUpdate.  If it is safe to remove CmpInstr, the
1689  // condition code of these operands will be modified.
1690  bool ShouldSwap = false;
1691  if (Sub) {
1692    ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1693      Sub->getOperand(2).getReg() == SrcReg;
1694
1695    // The operands to subf are the opposite of sub, so only in the fixed-point
1696    // case, invert the order.
1697    ShouldSwap = !ShouldSwap;
1698  }
1699
1700  if (ShouldSwap)
1701    for (MachineRegisterInfo::use_instr_iterator
1702         I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1703         I != IE; ++I) {
1704      MachineInstr *UseMI = &*I;
1705      if (UseMI->getOpcode() == PPC::BCC) {
1706        PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1707        assert((!equalityOnly ||
1708                Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1709               "Invalid predicate for equality-only optimization");
1710        PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1711                                PPC::getSwappedPredicate(Pred)));
1712      } else if (UseMI->getOpcode() == PPC::ISEL ||
1713                 UseMI->getOpcode() == PPC::ISEL8) {
1714        unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1715        assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1716               "Invalid CR bit for equality-only optimization");
1717
1718        if (NewSubReg == PPC::sub_lt)
1719          NewSubReg = PPC::sub_gt;
1720        else if (NewSubReg == PPC::sub_gt)
1721          NewSubReg = PPC::sub_lt;
1722
1723        SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1724                                                 NewSubReg));
1725      } else // We need to abort on a user we don't understand.
1726        return false;
1727    }
1728
1729  // Create a new virtual register to hold the value of the CR set by the
1730  // record-form instruction. If the instruction was not previously in
1731  // record form, then set the kill flag on the CR.
1732  CmpInstr->eraseFromParent();
1733
1734  MachineBasicBlock::iterator MII = MI;
1735  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1736          get(TargetOpcode::COPY), CRReg)
1737    .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1738
1739  if (MIOpC != NewOpC) {
1740    // We need to be careful here: we're replacing one instruction with
1741    // another, and we need to make sure that we get all of the right
1742    // implicit uses and defs. On the other hand, the caller may be holding
1743    // an iterator to this instruction, and so we can't delete it (this is
1744    // specifically the case if this is the instruction directly after the
1745    // compare).
1746
1747    const MCInstrDesc &NewDesc = get(NewOpC);
1748    MI->setDesc(NewDesc);
1749
1750    if (NewDesc.ImplicitDefs)
1751      for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1752           *ImpDefs; ++ImpDefs)
1753        if (!MI->definesRegister(*ImpDefs))
1754          MI->addOperand(*MI->getParent()->getParent(),
1755                         MachineOperand::CreateReg(*ImpDefs, true, true));
1756    if (NewDesc.ImplicitUses)
1757      for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1758           *ImpUses; ++ImpUses)
1759        if (!MI->readsRegister(*ImpUses))
1760          MI->addOperand(*MI->getParent()->getParent(),
1761                         MachineOperand::CreateReg(*ImpUses, false, true));
1762  }
1763
1764  // Modify the condition code of operands in OperandsToUpdate.
1765  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1766  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1767  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1768    PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1769
1770  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1771    SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1772
1773  return true;
1774}
1775
1776/// GetInstSize - Return the number of bytes of code the specified
1777/// instruction may be.  This returns the maximum number of bytes.
1778///
1779unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1780  unsigned Opcode = MI->getOpcode();
1781
1782  if (Opcode == PPC::INLINEASM) {
1783    const MachineFunction *MF = MI->getParent()->getParent();
1784    const char *AsmStr = MI->getOperand(0).getSymbolName();
1785    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1786  } else if (Opcode == TargetOpcode::STACKMAP) {
1787    return MI->getOperand(1).getImm();
1788  } else if (Opcode == TargetOpcode::PATCHPOINT) {
1789    PatchPointOpers Opers(MI);
1790    return Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
1791  } else {
1792    const MCInstrDesc &Desc = get(Opcode);
1793    return Desc.getSize();
1794  }
1795}
1796
1797std::pair<unsigned, unsigned>
1798PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
1799  const unsigned Mask = PPCII::MO_ACCESS_MASK;
1800  return std::make_pair(TF & Mask, TF & ~Mask);
1801}
1802
1803ArrayRef<std::pair<unsigned, const char *>>
1804PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
1805  using namespace PPCII;
1806  static const std::pair<unsigned, const char *> TargetFlags[] = {
1807      {MO_LO, "ppc-lo"},
1808      {MO_HA, "ppc-ha"},
1809      {MO_TPREL_LO, "ppc-tprel-lo"},
1810      {MO_TPREL_HA, "ppc-tprel-ha"},
1811      {MO_DTPREL_LO, "ppc-dtprel-lo"},
1812      {MO_TLSLD_LO, "ppc-tlsld-lo"},
1813      {MO_TOC_LO, "ppc-toc-lo"},
1814      {MO_TLS, "ppc-tls"}};
1815  return makeArrayRef(TargetFlags);
1816}
1817
1818ArrayRef<std::pair<unsigned, const char *>>
1819PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
1820  using namespace PPCII;
1821  static const std::pair<unsigned, const char *> TargetFlags[] = {
1822      {MO_PLT_OR_STUB, "ppc-plt-or-stub"},
1823      {MO_PIC_FLAG, "ppc-pic"},
1824      {MO_NLP_FLAG, "ppc-nlp"},
1825      {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
1826  return makeArrayRef(TargetFlags);
1827}
1828
1829